2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
62 #include <machine/bus.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/tsec/if_tsec.h>
68 #include <dev/tsec/if_tsecreg.h>
70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
73 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74 static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
76 static void tsec_free_dma(struct tsec_softc *sc);
77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78 static int tsec_ifmedia_upd(struct ifnet *ifp);
79 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85 static void tsec_init(void *xsc);
86 static void tsec_init_locked(struct tsec_softc *sc);
87 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88 static void tsec_reset_mac(struct tsec_softc *sc);
89 static void tsec_setfilter(struct tsec_softc *sc);
90 static void tsec_set_mac_address(struct tsec_softc *sc);
91 static void tsec_start(struct ifnet *ifp);
92 static void tsec_start_locked(struct ifnet *ifp);
93 static void tsec_stop(struct tsec_softc *sc);
94 static void tsec_tick(void *arg);
95 static void tsec_watchdog(struct tsec_softc *sc);
96 static void tsec_add_sysctls(struct tsec_softc *sc);
97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99 static void tsec_set_rxic(struct tsec_softc *sc);
100 static void tsec_set_txic(struct tsec_softc *sc);
101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_offload_setup(struct tsec_softc *sc);
105 static void tsec_offload_process_frame(struct tsec_softc *sc,
107 static void tsec_setup_multicast(struct tsec_softc *sc);
108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
110 devclass_t tsec_devclass;
111 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112 MODULE_DEPEND(tsec, ether, 1, 1, 1);
113 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115 struct mtx tsec_phy_mtx;
118 tsec_attach(struct tsec_softc *sc)
120 uint8_t hwaddr[ETHER_ADDR_LEN];
122 bus_dmamap_t *map_ptr;
123 bus_dmamap_t **map_pptr;
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
134 /* Stop DMA engine if enabled by firmware */
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
150 tsec_add_sysctls(sc);
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_NUM_DESC - 1, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
183 device_printf(sc->dev, "failed to allocate busdma tag "
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
201 device_printf(sc->dev, "failed to allocate busdma tag "
207 /* Create TX busdma maps */
208 map_ptr = sc->tx_map_data;
209 map_pptr = sc->tx_map_unused_data;
211 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
212 map_pptr[i] = &map_ptr[i];
213 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
215 device_printf(sc->dev, "failed to init TX ring\n");
221 /* Create RX busdma maps and zero mbuf handlers */
222 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
223 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
224 &sc->rx_data[i].map);
226 device_printf(sc->dev, "failed to init RX ring\n");
230 sc->rx_data[i].mbuf = NULL;
233 /* Create mbufs for RX buffers */
234 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
235 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
236 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
238 device_printf(sc->dev, "can't load rx DMA map %d, "
239 "error = %d\n", i, error);
245 /* Create network interface for upper layers */
246 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
248 device_printf(sc->dev, "if_alloc() failed\n");
254 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
255 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
256 ifp->if_init = tsec_init;
257 ifp->if_start = tsec_start;
258 ifp->if_ioctl = tsec_ioctl;
260 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
261 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
262 IFQ_SET_READY(&ifp->if_snd);
264 ifp->if_capabilities = IFCAP_VLAN_MTU;
266 ifp->if_capabilities |= IFCAP_HWCSUM;
268 ifp->if_capenable = ifp->if_capabilities;
270 #ifdef DEVICE_POLLING
271 /* Advertise that polling is supported */
272 ifp->if_capabilities |= IFCAP_POLLING;
276 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
277 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
280 device_printf(sc->dev, "attaching PHYs failed\n");
286 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
288 /* Set MAC address */
289 tsec_get_hwaddr(sc, hwaddr);
290 ether_ifattach(ifp, hwaddr);
296 tsec_detach(struct tsec_softc *sc)
299 if (sc->tsec_ifp != NULL) {
300 #ifdef DEVICE_POLLING
301 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
302 ether_poll_deregister(sc->tsec_ifp);
305 /* Stop TSEC controller and free TX queue */
307 tsec_shutdown(sc->dev);
309 /* Detach network interface */
310 ether_ifdetach(sc->tsec_ifp);
311 if_free(sc->tsec_ifp);
315 /* Free DMA resources */
322 tsec_shutdown(device_t dev)
324 struct tsec_softc *sc;
326 sc = device_get_softc(dev);
328 TSEC_GLOBAL_LOCK(sc);
330 TSEC_GLOBAL_UNLOCK(sc);
335 tsec_suspend(device_t dev)
338 /* TODO not implemented! */
343 tsec_resume(device_t dev)
346 /* TODO not implemented! */
353 struct tsec_softc *sc = xsc;
355 TSEC_GLOBAL_LOCK(sc);
356 tsec_init_locked(sc);
357 TSEC_GLOBAL_UNLOCK(sc);
361 tsec_init_locked(struct tsec_softc *sc)
363 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
364 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
365 struct ifnet *ifp = sc->tsec_ifp;
366 uint32_t timeout, val, i;
368 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
371 TSEC_GLOBAL_LOCK_ASSERT(sc);
375 * These steps are according to the MPC8555E PowerQUICCIII RM:
376 * 14.7 Initialization/Application Information
379 /* Step 1: soft reset MAC */
382 /* Step 2: Initialize MACCFG2 */
383 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
384 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
385 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
386 TSEC_MACCFG2_GMII | /* I/F Mode bit */
387 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
390 /* Step 3: Initialize ECNTRL
391 * While the documentation states that R100M is ignored if RPM is
392 * not set, it does seem to be needed to get the orange boxes to
393 * work (which have a Marvell 88E1111 PHY). Go figure.
397 * XXX kludge - use circumstancial evidence to program ECNTRL
398 * correctly. Ideally we need some board information to guide
401 i = TSEC_READ(sc, TSEC_REG_ID2);
403 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
404 : TSEC_ECNTRL_R100M; /* Orange + CDS */
405 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
407 /* Step 4: Initialize MAC station address */
408 tsec_set_mac_address(sc);
411 * Step 5: Assign a Physical address to the TBI so as to not conflict
412 * with the external PHY physical address
414 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
418 /* Step 6: Reset the management interface */
419 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
421 /* Step 7: Setup the MII Mgmt clock speed */
422 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
424 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
425 timeout = TSEC_READ_RETRY;
426 while (--timeout && (TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
428 DELAY(TSEC_READ_DELAY);
430 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
435 /* Step 9: Setup the MII Mgmt */
436 mii_mediachg(sc->tsec_mii);
438 /* Step 10: Clear IEVENT register */
439 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
441 /* Step 11: Enable interrupts */
442 #ifdef DEVICE_POLLING
444 * ...only if polling is not turned on. Disable interrupts explicitly
445 * if polling is enabled.
447 if (ifp->if_capenable & IFCAP_POLLING )
448 tsec_intrs_ctl(sc, 0);
450 #endif /* DEVICE_POLLING */
451 tsec_intrs_ctl(sc, 1);
453 /* Step 12: Initialize IADDRn */
454 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
455 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
456 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
457 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
458 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
459 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
460 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
461 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
463 /* Step 13: Initialize GADDRn */
464 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
465 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
466 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
467 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
468 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
469 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
470 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
471 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
473 /* Step 14: Initialize RCTRL */
474 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
476 /* Step 15: Initialize DMACTRL */
479 /* Step 16: Initialize FIFO_PAUSE_CTRL */
480 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
483 * Step 17: Initialize transmit/receive descriptor rings.
484 * Initialize TBASE and RBASE.
486 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
487 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
489 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
490 tx_desc[i].bufptr = 0;
491 tx_desc[i].length = 0;
492 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
495 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
498 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
499 rx_desc[i].bufptr = sc->rx_data[i].paddr;
500 rx_desc[i].length = 0;
501 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
502 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
504 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
507 /* Step 18: Initialize the maximum receive buffer length */
508 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
510 /* Step 19: Configure ethernet frame sizes */
511 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
512 tsec_set_mtu(sc, ifp->if_mtu);
514 /* Step 20: Enable Rx and RxBD sdata snooping */
515 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
516 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
518 /* Step 21: Reset collision counters in hardware */
519 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
520 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
521 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
522 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
523 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
525 /* Step 22: Mask all CAM interrupts */
526 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
527 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
529 /* Step 23: Enable Rx and Tx */
530 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
531 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
532 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
534 /* Step 24: Reset TSEC counters for Tx and Rx rings */
535 TSEC_TX_RX_COUNTERS_INIT(sc);
537 /* Step 25: Setup TCP/IP Off-Load engine */
539 tsec_offload_setup(sc);
541 /* Step 26: Setup multicast filters */
542 tsec_setup_multicast(sc);
544 /* Step 27: Activate network interface */
545 ifp->if_drv_flags |= IFF_DRV_RUNNING;
546 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
547 sc->tsec_if_flags = ifp->if_flags;
548 sc->tsec_watchdog = 0;
550 /* Schedule watchdog timeout */
551 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
555 tsec_set_mac_address(struct tsec_softc *sc)
557 uint32_t macbuf[2] = { 0, 0 };
558 char *macbufp, *curmac;
561 TSEC_GLOBAL_LOCK_ASSERT(sc);
563 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
564 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
567 macbufp = (char *)macbuf;
568 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
570 /* Correct order of MAC address bytes */
571 for (i = 1; i <= ETHER_ADDR_LEN; i++)
572 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
574 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
575 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
576 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
580 * DMA control function, if argument state is:
581 * 0 - DMA engine will be disabled
582 * 1 - DMA engine will be enabled
585 tsec_dma_ctl(struct tsec_softc *sc, int state)
588 uint32_t dma_flags, timeout;
592 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
596 /* Temporarily clear stop graceful stop bits. */
597 tsec_dma_ctl(sc, 1000);
600 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
604 /* Set write with response (WWR), wait (WOP) and snoop bits */
605 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
606 DMACTRL_WWR | DMACTRL_WOP);
608 /* Clear graceful stop bits */
609 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
612 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
616 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
620 /* Wait for DMA stop */
621 timeout = TSEC_READ_RETRY;
622 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
623 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
624 DELAY(TSEC_READ_DELAY);
627 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
630 /* Restart transmission function */
631 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
636 * Interrupts control function, if argument state is:
637 * 0 - all TSEC interrupts will be masked
638 * 1 - all TSEC interrupts will be unmasked
641 tsec_intrs_ctl(struct tsec_softc *sc, int state)
649 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
652 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
653 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
654 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
655 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
658 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
664 tsec_reset_mac(struct tsec_softc *sc)
666 uint32_t maccfg1_flags;
668 /* Set soft reset bit */
669 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
670 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
671 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
673 /* Clear soft reset bit */
674 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
675 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
676 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
680 tsec_watchdog(struct tsec_softc *sc)
684 TSEC_GLOBAL_LOCK_ASSERT(sc);
686 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
690 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
691 if_printf(ifp, "watchdog timeout\n");
694 tsec_init_locked(sc);
698 tsec_start(struct ifnet *ifp)
700 struct tsec_softc *sc = ifp->if_softc;
702 TSEC_TRANSMIT_LOCK(sc);
703 tsec_start_locked(ifp);
704 TSEC_TRANSMIT_UNLOCK(sc);
708 tsec_start_locked(struct ifnet *ifp)
710 struct tsec_softc *sc;
711 struct mbuf *m0, *mtmp;
712 struct tsec_tx_fcb *tx_fcb;
713 unsigned int queued = 0;
714 int csum_flags, fcb_inserted = 0;
718 TSEC_TRANSMIT_LOCK_ASSERT(sc);
720 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
724 if (sc->tsec_link == 0)
727 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
728 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
730 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
731 /* Get packet from the queue */
732 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
736 /* Insert TCP/IP Off-load frame control block */
737 csum_flags = m0->m_pkthdr.csum_flags;
740 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
744 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
746 tx_fcb->l3_offset = ETHER_HDR_LEN;
747 tx_fcb->l4_offset = sizeof(struct ip);
749 if (csum_flags & CSUM_IP)
750 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
753 if (csum_flags & CSUM_TCP)
754 tx_fcb->flags |= TSEC_TX_FCB_TCP |
755 TSEC_TX_FCB_CSUM_TCP_UDP;
757 if (csum_flags & CSUM_UDP)
758 tx_fcb->flags |= TSEC_TX_FCB_UDP |
759 TSEC_TX_FCB_CSUM_TCP_UDP;
764 mtmp = m_defrag(m0, M_NOWAIT);
768 if (tsec_encap(sc, m0, fcb_inserted)) {
769 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
770 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
776 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
780 /* Enable transmitter and watchdog timer */
781 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
782 sc->tsec_watchdog = 5;
787 tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
789 struct tsec_desc *tx_desc = NULL;
791 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
793 int csum_flag = 0, error, seg, nsegs;
795 TSEC_TRANSMIT_LOCK_ASSERT(sc);
799 if (TSEC_FREE_TX_DESC(sc) == 0) {
800 /* No free descriptors */
804 /* Fetch unused map */
805 mapp = TSEC_ALLOC_TX_MAP(sc);
807 /* Create mapping in DMA memory */
808 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
809 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
810 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
811 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
812 TSEC_FREE_TX_MAP(sc, mapp);
813 return ((error != 0) ? error : -1);
815 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
817 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
818 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
821 csum_flag = TSEC_TXBD_TOE;
823 /* Everything is ok, now we can send buffers */
824 for (seg = 0; seg < nsegs; seg++) {
825 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
827 tx_desc->length = segs[seg].ds_len;
828 tx_desc->bufptr = segs[seg].ds_addr;
835 * - transmit the CRC sequence after the last data byte
836 * - interrupt after the last buffer
839 (tx_desc->flags & TSEC_TXBD_W) |
840 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
841 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
844 /* Save mbuf and DMA mapping for release at later stage */
845 TSEC_PUT_TX_MBUF(sc, m0);
846 TSEC_PUT_TX_MAP(sc, mapp);
852 tsec_setfilter(struct tsec_softc *sc)
858 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
860 /* Promiscuous mode */
861 if (ifp->if_flags & IFF_PROMISC)
862 flags |= TSEC_RCTRL_PROM;
864 flags &= ~TSEC_RCTRL_PROM;
866 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
869 #ifdef DEVICE_POLLING
870 static poll_handler_t tsec_poll;
873 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
876 struct tsec_softc *sc = ifp->if_softc;
881 TSEC_GLOBAL_LOCK(sc);
882 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
883 TSEC_GLOBAL_UNLOCK(sc);
887 if (cmd == POLL_AND_CHECK_STATUS) {
888 tsec_error_intr_locked(sc, count);
890 /* Clear all events reported */
891 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
892 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
895 tsec_transmit_intr_locked(sc);
897 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
899 rx_npkts = tsec_receive_intr_locked(sc, count);
901 TSEC_RECEIVE_UNLOCK(sc);
905 #endif /* DEVICE_POLLING */
908 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
910 struct tsec_softc *sc = ifp->if_softc;
911 struct ifreq *ifr = (struct ifreq *)data;
919 TSEC_GLOBAL_LOCK(sc);
920 if (tsec_set_mtu(sc, ifr->ifr_mtu))
921 ifp->if_mtu = ifr->ifr_mtu;
924 TSEC_GLOBAL_UNLOCK(sc);
927 TSEC_GLOBAL_LOCK(sc);
928 if (ifp->if_flags & IFF_UP) {
929 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
930 if ((sc->tsec_if_flags ^ ifp->if_flags) &
934 if ((sc->tsec_if_flags ^ ifp->if_flags) &
936 tsec_setup_multicast(sc);
938 tsec_init_locked(sc);
939 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
942 sc->tsec_if_flags = ifp->if_flags;
943 TSEC_GLOBAL_UNLOCK(sc);
947 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
948 TSEC_GLOBAL_LOCK(sc);
949 tsec_setup_multicast(sc);
950 TSEC_GLOBAL_UNLOCK(sc);
954 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
958 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
959 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
960 TSEC_GLOBAL_LOCK(sc);
961 ifp->if_capenable &= ~IFCAP_HWCSUM;
962 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
963 tsec_offload_setup(sc);
964 TSEC_GLOBAL_UNLOCK(sc);
966 #ifdef DEVICE_POLLING
967 if (mask & IFCAP_POLLING) {
968 if (ifr->ifr_reqcap & IFCAP_POLLING) {
969 error = ether_poll_register(tsec_poll, ifp);
973 TSEC_GLOBAL_LOCK(sc);
974 /* Disable interrupts */
975 tsec_intrs_ctl(sc, 0);
976 ifp->if_capenable |= IFCAP_POLLING;
977 TSEC_GLOBAL_UNLOCK(sc);
979 error = ether_poll_deregister(ifp);
980 TSEC_GLOBAL_LOCK(sc);
981 /* Enable interrupts */
982 tsec_intrs_ctl(sc, 1);
983 ifp->if_capenable &= ~IFCAP_POLLING;
984 TSEC_GLOBAL_UNLOCK(sc);
991 error = ether_ioctl(ifp, command, data);
994 /* Flush buffers if not empty */
995 if (ifp->if_flags & IFF_UP)
1001 tsec_ifmedia_upd(struct ifnet *ifp)
1003 struct tsec_softc *sc = ifp->if_softc;
1004 struct mii_data *mii;
1006 TSEC_TRANSMIT_LOCK(sc);
1011 TSEC_TRANSMIT_UNLOCK(sc);
1016 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1018 struct tsec_softc *sc = ifp->if_softc;
1019 struct mii_data *mii;
1021 TSEC_TRANSMIT_LOCK(sc);
1026 ifmr->ifm_active = mii->mii_media_active;
1027 ifmr->ifm_status = mii->mii_media_status;
1029 TSEC_TRANSMIT_UNLOCK(sc);
1033 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1036 struct mbuf *new_mbuf;
1037 bus_dma_segment_t seg[1];
1040 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1042 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1043 if (new_mbuf == NULL)
1045 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1048 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1049 bus_dmamap_unload(tag, map);
1052 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1054 KASSERT(nsegs == 1, ("Too many segments returned!"));
1055 if (nsegs != 1 || error)
1056 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1060 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1068 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1069 ("Wrong alignment of RX buffer!"));
1071 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1073 (*mbufp) = new_mbuf;
1074 (*paddr) = seg->ds_addr;
1079 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1083 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1085 *paddr = segs->ds_addr;
1089 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1090 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1094 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1095 error = bus_dma_tag_create(NULL, /* parent */
1096 PAGE_SIZE, 0, /* alignment, boundary */
1097 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1098 BUS_SPACE_MAXADDR, /* highaddr */
1099 NULL, NULL, /* filtfunc, filtfuncarg */
1100 dsize, 1, /* maxsize, nsegments */
1101 dsize, 0, /* maxsegsz, flags */
1102 NULL, NULL, /* lockfunc, lockfuncarg */
1106 device_printf(dev, "failed to allocate busdma %s tag\n",
1112 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1115 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1117 bus_dma_tag_destroy(*dtag);
1122 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1123 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1125 device_printf(dev, "cannot get address of the %s "
1126 "descriptors\n", dname);
1127 bus_dmamem_free(*dtag, *vaddr, *dmap);
1128 bus_dma_tag_destroy(*dtag);
1137 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1143 /* Unmap descriptors from DMA memory */
1144 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1145 BUS_DMASYNC_POSTWRITE);
1146 bus_dmamap_unload(dtag, dmap);
1148 /* Free descriptors memory */
1149 bus_dmamem_free(dtag, vaddr, dmap);
1151 /* Destroy descriptors tag */
1152 bus_dma_tag_destroy(dtag);
1156 tsec_free_dma(struct tsec_softc *sc)
1161 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1162 if (sc->tx_map_data[i] != NULL)
1163 bus_dmamap_destroy(sc->tsec_tx_mtag,
1164 sc->tx_map_data[i]);
1165 /* Destroy tag for TX mbufs */
1166 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1168 /* Free RX mbufs and maps */
1169 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1170 if (sc->rx_data[i].mbuf) {
1171 /* Unload buffer from DMA */
1172 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1173 BUS_DMASYNC_POSTREAD);
1174 bus_dmamap_unload(sc->tsec_rx_mtag,
1175 sc->rx_data[i].map);
1178 m_freem(sc->rx_data[i].mbuf);
1180 /* Destroy map for this buffer */
1181 if (sc->rx_data[i].map != NULL)
1182 bus_dmamap_destroy(sc->tsec_rx_mtag,
1183 sc->rx_data[i].map);
1185 /* Destroy tag for RX mbufs */
1186 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1188 /* Unload TX/RX descriptors */
1189 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1191 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1196 tsec_stop(struct tsec_softc *sc)
1203 TSEC_GLOBAL_LOCK_ASSERT(sc);
1207 /* Disable interface and watchdog timer */
1208 callout_stop(&sc->tsec_callout);
1209 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1210 sc->tsec_watchdog = 0;
1212 /* Disable all interrupts and stop DMA */
1213 tsec_intrs_ctl(sc, 0);
1214 tsec_dma_ctl(sc, 0);
1216 /* Remove pending data from TX queue */
1217 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1218 m0 = TSEC_GET_TX_MBUF(sc);
1219 mapp = TSEC_GET_TX_MAP(sc);
1221 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1222 BUS_DMASYNC_POSTWRITE);
1223 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1225 TSEC_FREE_TX_MAP(sc, mapp);
1229 /* Disable RX and TX */
1230 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1231 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1232 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1237 tsec_tick(void *arg)
1239 struct tsec_softc *sc = arg;
1243 TSEC_GLOBAL_LOCK(sc);
1248 link = sc->tsec_link;
1250 mii_tick(sc->tsec_mii);
1252 if (link == 0 && sc->tsec_link == 1 &&
1253 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1254 tsec_start_locked(ifp);
1256 /* Schedule another timeout one second from now. */
1257 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1259 TSEC_GLOBAL_UNLOCK(sc);
1263 * This is the core RX routine. It replenishes mbufs in the descriptor and
1264 * sends data which have been dma'ed into host memory to upper layer.
1266 * Loops at most count times if count is > 0, or until done if count < 0.
1269 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1271 struct tsec_desc *rx_desc;
1273 struct rx_data_type *rx_data;
1280 TSEC_RECEIVE_LOCK_ASSERT(sc);
1283 rx_data = sc->rx_data;
1287 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1290 for (c = 0; ; c++) {
1291 if (count >= 0 && count-- == 0)
1294 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1295 flags = rx_desc->flags;
1297 /* Check if there is anything to receive */
1298 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1300 * Avoid generating another interrupt
1302 if (flags & TSEC_RXBD_E)
1303 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1304 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1306 * We didn't consume current descriptor and have to
1307 * return it to the queue
1309 TSEC_BACK_CUR_RX_DESC(sc);
1313 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1314 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1316 rx_desc->length = 0;
1317 rx_desc->flags = (rx_desc->flags &
1318 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1320 if (sc->frame != NULL) {
1328 /* Ok... process frame */
1329 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1330 m = rx_data[i].mbuf;
1331 m->m_len = rx_desc->length;
1333 if (sc->frame != NULL) {
1334 if ((flags & TSEC_RXBD_L) != 0)
1335 m->m_len -= m_length(sc->frame, NULL);
1337 m->m_flags &= ~M_PKTHDR;
1338 m_cat(sc->frame, m);
1345 if ((flags & TSEC_RXBD_L) != 0) {
1350 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1351 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1352 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1354 * We ran out of mbufs; didn't consume current
1355 * descriptor and have to return it to the queue.
1357 TSEC_BACK_CUR_RX_DESC(sc);
1361 /* Attach new buffer to descriptor and clear flags */
1362 rx_desc->bufptr = rx_data[i].paddr;
1363 rx_desc->length = 0;
1364 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1365 TSEC_RXBD_E | TSEC_RXBD_I;
1368 m->m_pkthdr.rcvif = ifp;
1371 m_adj(m, -ETHER_CRC_LEN);
1374 tsec_offload_process_frame(sc, m);
1376 TSEC_RECEIVE_UNLOCK(sc);
1377 (*ifp->if_input)(ifp, m);
1378 TSEC_RECEIVE_LOCK(sc);
1383 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1387 * Make sure TSEC receiver is not halted.
1389 * Various conditions can stop the TSEC receiver, but not all are
1390 * signaled and handled by error interrupt, so make sure the receiver
1391 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1392 * halted, and is harmless if already running.
1394 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1399 tsec_receive_intr(void *arg)
1401 struct tsec_softc *sc = arg;
1403 TSEC_RECEIVE_LOCK(sc);
1405 #ifdef DEVICE_POLLING
1406 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1407 TSEC_RECEIVE_UNLOCK(sc);
1412 /* Confirm the interrupt was received by driver */
1413 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1414 tsec_receive_intr_locked(sc, -1);
1416 TSEC_RECEIVE_UNLOCK(sc);
1420 tsec_transmit_intr_locked(struct tsec_softc *sc)
1422 struct tsec_desc *tx_desc;
1428 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1432 /* Update collision statistics */
1433 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1435 /* Reset collision counters in hardware */
1436 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1437 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1438 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1439 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1440 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1442 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1443 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1445 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1446 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1447 if (tx_desc->flags & TSEC_TXBD_R) {
1448 TSEC_BACK_DIRTY_TX_DESC(sc);
1452 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1456 * This is the last buf in this packet, so unmap and free it.
1458 m0 = TSEC_GET_TX_MBUF(sc);
1459 mapp = TSEC_GET_TX_MAP(sc);
1461 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1462 BUS_DMASYNC_POSTWRITE);
1463 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1465 TSEC_FREE_TX_MAP(sc, mapp);
1468 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1471 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1475 /* Now send anything that was pending */
1476 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1477 tsec_start_locked(ifp);
1479 /* Stop wathdog if all sent */
1480 if (TSEC_EMPTYQ_TX_MBUF(sc))
1481 sc->tsec_watchdog = 0;
1486 tsec_transmit_intr(void *arg)
1488 struct tsec_softc *sc = arg;
1490 TSEC_TRANSMIT_LOCK(sc);
1492 #ifdef DEVICE_POLLING
1493 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1494 TSEC_TRANSMIT_UNLOCK(sc);
1498 /* Confirm the interrupt was received by driver */
1499 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1500 tsec_transmit_intr_locked(sc);
1502 TSEC_TRANSMIT_UNLOCK(sc);
1506 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1511 TSEC_GLOBAL_LOCK_ASSERT(sc);
1515 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1517 /* Clear events bits in hardware */
1518 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1519 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1520 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1521 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1523 /* Check transmitter errors */
1524 if (eflags & TSEC_IEVENT_TXE) {
1525 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1527 if (eflags & TSEC_IEVENT_LC)
1528 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1530 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1533 /* Check receiver errors */
1534 if (eflags & TSEC_IEVENT_BSY) {
1535 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1536 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1538 /* Get data from RX buffers */
1539 tsec_receive_intr_locked(sc, count);
1542 if (ifp->if_flags & IFF_DEBUG)
1543 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1546 if (eflags & TSEC_IEVENT_EBERR) {
1547 if_printf(ifp, "System bus error occurred during"
1548 "DMA transaction (flags: 0x%x)\n", eflags);
1549 tsec_init_locked(sc);
1552 if (eflags & TSEC_IEVENT_BABT)
1553 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1555 if (eflags & TSEC_IEVENT_BABR)
1556 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1560 tsec_error_intr(void *arg)
1562 struct tsec_softc *sc = arg;
1564 TSEC_GLOBAL_LOCK(sc);
1565 tsec_error_intr_locked(sc, -1);
1566 TSEC_GLOBAL_UNLOCK(sc);
1570 tsec_miibus_readreg(device_t dev, int phy, int reg)
1572 struct tsec_softc *sc;
1576 sc = device_get_softc(dev);
1579 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1581 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1583 timeout = TSEC_READ_RETRY;
1584 while (--timeout && TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
1585 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1586 DELAY(TSEC_READ_DELAY);
1589 device_printf(dev, "Timeout while reading from PHY!\n");
1591 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1598 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1600 struct tsec_softc *sc;
1603 sc = device_get_softc(dev);
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1607 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1609 timeout = TSEC_READ_RETRY;
1610 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
1612 DELAY(TSEC_READ_DELAY);
1616 device_printf(dev, "Timeout while writing to PHY!\n");
1622 tsec_miibus_statchg(device_t dev)
1624 struct tsec_softc *sc;
1625 struct mii_data *mii;
1626 uint32_t ecntrl, id, tmp;
1629 sc = device_get_softc(dev);
1631 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1633 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1635 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1636 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1638 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1640 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1643 tmp |= TSEC_MACCFG2_GMII;
1644 sc->tsec_link = link;
1648 tmp |= TSEC_MACCFG2_MII;
1649 sc->tsec_link = link;
1653 device_printf(dev, "No speed selected but link "
1659 device_printf(dev, "Unknown speed (%d), link %s!\n",
1660 IFM_SUBTYPE(mii->mii_media_active),
1661 ((link) ? "up" : "down"));
1664 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1666 /* XXX kludge - use circumstantial evidence for reduced mode. */
1667 id = TSEC_READ(sc, TSEC_REG_ID2);
1669 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1670 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1671 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1676 tsec_add_sysctls(struct tsec_softc *sc)
1678 struct sysctl_ctx_list *ctx;
1679 struct sysctl_oid_list *children;
1680 struct sysctl_oid *tree;
1682 ctx = device_get_sysctl_ctx(sc->dev);
1683 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1684 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1685 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1686 children = SYSCTL_CHILDREN(tree);
1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1689 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1690 "I", "IC RX time threshold (0-65535)");
1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1692 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1693 "I", "IC RX frame count threshold (0-255)");
1695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1696 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1697 "I", "IC TX time threshold (0-65535)");
1698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1699 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1700 "I", "IC TX frame count threshold (0-255)");
1704 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1705 * interrupt is raised either upon:
1707 * - threshold-defined period of time elapsed, or
1708 * - threshold-defined number of frames is received/transmitted,
1709 * whichever occurs first.
1711 * The following sysctls regulate IC behaviour (for TX/RX separately):
1713 * dev.tsec.<unit>.int_coal.rx_time
1714 * dev.tsec.<unit>.int_coal.rx_count
1715 * dev.tsec.<unit>.int_coal.tx_time
1716 * dev.tsec.<unit>.int_coal.tx_count
1720 * - 0 for either time or count disables IC on the given TX/RX path
1722 * - count: 1-255 (expresses frame count number; note that value of 1 is
1723 * effectively IC off)
1725 * - time: 1-65535 (value corresponds to a real time period and is
1726 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1727 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1728 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1729 * TSEC reference manual.
1732 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1736 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1738 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1740 error = sysctl_handle_int(oidp, &time, 0, req);
1748 if (arg2 == TSEC_IC_RX) {
1749 sc->rx_ic_time = time;
1752 sc->tx_ic_time = time;
1761 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1765 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1767 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1769 error = sysctl_handle_int(oidp, &count, 0, req);
1777 if (arg2 == TSEC_IC_RX) {
1778 sc->rx_ic_count = count;
1781 sc->tx_ic_count = count;
1790 tsec_set_rxic(struct tsec_softc *sc)
1794 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1798 rxic_val = 0x80000000;
1799 rxic_val |= (sc->rx_ic_count << 21);
1800 rxic_val |= sc->rx_ic_time;
1803 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1807 tsec_set_txic(struct tsec_softc *sc)
1811 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1815 txic_val = 0x80000000;
1816 txic_val |= (sc->tx_ic_count << 21);
1817 txic_val |= sc->tx_ic_time;
1820 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1824 tsec_offload_setup(struct tsec_softc *sc)
1826 struct ifnet *ifp = sc->tsec_ifp;
1829 TSEC_GLOBAL_LOCK_ASSERT(sc);
1831 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1832 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1834 if (ifp->if_capenable & IFCAP_TXCSUM)
1835 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1837 ifp->if_hwassist = 0;
1839 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1841 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1842 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1843 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1845 if (ifp->if_capenable & IFCAP_RXCSUM)
1846 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1847 TSEC_RCTRL_PRSDEP_PARSE_L234;
1849 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1854 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1856 struct tsec_rx_fcb rx_fcb;
1858 int protocol, flags;
1860 TSEC_RECEIVE_LOCK_ASSERT(sc);
1862 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1863 flags = rx_fcb.flags;
1864 protocol = rx_fcb.protocol;
1866 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1867 csum_flags |= CSUM_IP_CHECKED;
1869 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1870 csum_flags |= CSUM_IP_VALID;
1873 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1874 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1875 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1877 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1878 m->m_pkthdr.csum_data = 0xFFFF;
1881 m->m_pkthdr.csum_flags = csum_flags;
1883 if (flags & TSEC_RX_FCB_VLAN) {
1884 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1885 m->m_flags |= M_VLANTAG;
1888 m_adj(m, sizeof(struct tsec_rx_fcb));
1892 tsec_setup_multicast(struct tsec_softc *sc)
1894 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1895 struct ifnet *ifp = sc->tsec_ifp;
1896 struct ifmultiaddr *ifma;
1900 TSEC_GLOBAL_LOCK_ASSERT(sc);
1902 if (ifp->if_flags & IFF_ALLMULTI) {
1903 for (i = 0; i < 8; i++)
1904 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1909 if_maddr_rlock(ifp);
1910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1912 if (ifma->ifma_addr->sa_family != AF_LINK)
1915 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1916 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1918 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1920 if_maddr_runlock(ifp);
1922 for (i = 0; i < 8; i++)
1923 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1927 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1930 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1932 TSEC_GLOBAL_LOCK_ASSERT(sc);
1934 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1935 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);