2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
61 #include <machine/bus.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/tsec/if_tsec.h>
67 #include <dev/tsec/if_tsecreg.h>
69 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
72 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
73 static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
75 static void tsec_free_dma(struct tsec_softc *sc);
76 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
77 static int tsec_ifmedia_upd(struct ifnet *ifp);
78 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
79 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
80 struct mbuf **mbufp, uint32_t *paddr);
81 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
83 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
84 static void tsec_init(void *xsc);
85 static void tsec_init_locked(struct tsec_softc *sc);
86 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
87 static void tsec_reset_mac(struct tsec_softc *sc);
88 static void tsec_setfilter(struct tsec_softc *sc);
89 static void tsec_set_mac_address(struct tsec_softc *sc);
90 static void tsec_start(struct ifnet *ifp);
91 static void tsec_start_locked(struct ifnet *ifp);
92 static void tsec_stop(struct tsec_softc *sc);
93 static void tsec_tick(void *arg);
94 static void tsec_watchdog(struct tsec_softc *sc);
95 static void tsec_add_sysctls(struct tsec_softc *sc);
96 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
97 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
98 static void tsec_set_rxic(struct tsec_softc *sc);
99 static void tsec_set_txic(struct tsec_softc *sc);
100 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
101 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
102 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
103 static void tsec_offload_setup(struct tsec_softc *sc);
104 static void tsec_offload_process_frame(struct tsec_softc *sc,
106 static void tsec_setup_multicast(struct tsec_softc *sc);
107 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
109 devclass_t tsec_devclass;
110 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
111 MODULE_DEPEND(tsec, ether, 1, 1, 1);
112 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115 tsec_attach(struct tsec_softc *sc)
117 uint8_t hwaddr[ETHER_ADDR_LEN];
119 bus_dmamap_t *map_ptr;
120 bus_dmamap_t **map_pptr;
124 /* Reset all TSEC counters */
125 TSEC_TX_RX_COUNTERS_INIT(sc);
127 /* Stop DMA engine if enabled by firmware */
133 /* Disable interrupts for now */
134 tsec_intrs_ctl(sc, 0);
136 /* Configure defaults for interrupts coalescing */
137 sc->rx_ic_time = 768;
138 sc->rx_ic_count = 16;
139 sc->tx_ic_time = 768;
140 sc->tx_ic_count = 16;
143 tsec_add_sysctls(sc);
145 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
146 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
147 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
148 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
155 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
156 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
157 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
158 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
164 /* Allocate a busdma tag for TX mbufs. */
165 error = bus_dma_tag_create(NULL, /* parent */
166 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
167 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
168 BUS_SPACE_MAXADDR, /* highaddr */
169 NULL, NULL, /* filtfunc, filtfuncarg */
170 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
171 TSEC_TX_NUM_DESC - 1, /* nsegments */
172 MCLBYTES, 0, /* maxsegsz, flags */
173 NULL, NULL, /* lockfunc, lockfuncarg */
174 &sc->tsec_tx_mtag); /* dmat */
176 device_printf(sc->dev, "failed to allocate busdma tag "
182 /* Allocate a busdma tag for RX mbufs. */
183 error = bus_dma_tag_create(NULL, /* parent */
184 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
185 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
186 BUS_SPACE_MAXADDR, /* highaddr */
187 NULL, NULL, /* filtfunc, filtfuncarg */
188 MCLBYTES, /* maxsize */
190 MCLBYTES, 0, /* maxsegsz, flags */
191 NULL, NULL, /* lockfunc, lockfuncarg */
192 &sc->tsec_rx_mtag); /* dmat */
194 device_printf(sc->dev, "failed to allocate busdma tag "
200 /* Create TX busdma maps */
201 map_ptr = sc->tx_map_data;
202 map_pptr = sc->tx_map_unused_data;
204 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
205 map_pptr[i] = &map_ptr[i];
206 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
208 device_printf(sc->dev, "failed to init TX ring\n");
214 /* Create RX busdma maps and zero mbuf handlers */
215 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
216 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
217 &sc->rx_data[i].map);
219 device_printf(sc->dev, "failed to init RX ring\n");
223 sc->rx_data[i].mbuf = NULL;
226 /* Create mbufs for RX buffers */
227 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
228 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
229 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
231 device_printf(sc->dev, "can't load rx DMA map %d, "
232 "error = %d\n", i, error);
238 /* Create network interface for upper layers */
239 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
241 device_printf(sc->dev, "if_alloc() failed\n");
247 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
248 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
249 ifp->if_init = tsec_init;
250 ifp->if_start = tsec_start;
251 ifp->if_ioctl = tsec_ioctl;
253 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
254 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
255 IFQ_SET_READY(&ifp->if_snd);
257 ifp->if_capabilities = IFCAP_VLAN_MTU;
259 ifp->if_capabilities |= IFCAP_HWCSUM;
261 ifp->if_capenable = ifp->if_capabilities;
263 #ifdef DEVICE_POLLING
264 /* Advertise that polling is supported */
265 ifp->if_capabilities |= IFCAP_POLLING;
269 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
270 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
273 device_printf(sc->dev, "attaching PHYs failed\n");
279 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
281 /* Set MAC address */
282 tsec_get_hwaddr(sc, hwaddr);
283 ether_ifattach(ifp, hwaddr);
289 tsec_detach(struct tsec_softc *sc)
292 if (sc->tsec_ifp != NULL) {
293 #ifdef DEVICE_POLLING
294 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
295 ether_poll_deregister(sc->tsec_ifp);
298 /* Stop TSEC controller and free TX queue */
300 tsec_shutdown(sc->dev);
302 /* Detach network interface */
303 ether_ifdetach(sc->tsec_ifp);
304 if_free(sc->tsec_ifp);
308 /* Free DMA resources */
315 tsec_shutdown(device_t dev)
317 struct tsec_softc *sc;
319 sc = device_get_softc(dev);
321 TSEC_GLOBAL_LOCK(sc);
323 TSEC_GLOBAL_UNLOCK(sc);
328 tsec_suspend(device_t dev)
331 /* TODO not implemented! */
336 tsec_resume(device_t dev)
339 /* TODO not implemented! */
346 struct tsec_softc *sc = xsc;
348 TSEC_GLOBAL_LOCK(sc);
349 tsec_init_locked(sc);
350 TSEC_GLOBAL_UNLOCK(sc);
354 tsec_init_locked(struct tsec_softc *sc)
356 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
357 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
358 struct ifnet *ifp = sc->tsec_ifp;
359 uint32_t timeout, val, i;
361 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
364 TSEC_GLOBAL_LOCK_ASSERT(sc);
368 * These steps are according to the MPC8555E PowerQUICCIII RM:
369 * 14.7 Initialization/Application Information
372 /* Step 1: soft reset MAC */
375 /* Step 2: Initialize MACCFG2 */
376 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
377 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
378 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
379 TSEC_MACCFG2_GMII | /* I/F Mode bit */
380 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
383 /* Step 3: Initialize ECNTRL
384 * While the documentation states that R100M is ignored if RPM is
385 * not set, it does seem to be needed to get the orange boxes to
386 * work (which have a Marvell 88E1111 PHY). Go figure.
390 * XXX kludge - use circumstancial evidence to program ECNTRL
391 * correctly. Ideally we need some board information to guide
394 i = TSEC_READ(sc, TSEC_REG_ID2);
396 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
397 : TSEC_ECNTRL_R100M; /* Orange + CDS */
398 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
400 /* Step 4: Initialize MAC station address */
401 tsec_set_mac_address(sc);
404 * Step 5: Assign a Physical address to the TBI so as to not conflict
405 * with the external PHY physical address
407 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
409 /* Step 6: Reset the management interface */
410 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
412 /* Step 7: Setup the MII Mgmt clock speed */
413 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
415 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
416 timeout = TSEC_READ_RETRY;
417 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
419 DELAY(TSEC_READ_DELAY);
421 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
425 /* Step 9: Setup the MII Mgmt */
426 mii_mediachg(sc->tsec_mii);
428 /* Step 10: Clear IEVENT register */
429 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
431 /* Step 11: Enable interrupts */
432 #ifdef DEVICE_POLLING
434 * ...only if polling is not turned on. Disable interrupts explicitly
435 * if polling is enabled.
437 if (ifp->if_capenable & IFCAP_POLLING )
438 tsec_intrs_ctl(sc, 0);
440 #endif /* DEVICE_POLLING */
441 tsec_intrs_ctl(sc, 1);
443 /* Step 12: Initialize IADDRn */
444 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
445 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
446 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
447 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
448 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
449 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
450 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
451 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
453 /* Step 13: Initialize GADDRn */
454 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
455 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
456 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
457 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
458 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
459 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
460 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
461 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
463 /* Step 14: Initialize RCTRL */
464 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
466 /* Step 15: Initialize DMACTRL */
469 /* Step 16: Initialize FIFO_PAUSE_CTRL */
470 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
473 * Step 17: Initialize transmit/receive descriptor rings.
474 * Initialize TBASE and RBASE.
476 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
477 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
479 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
480 tx_desc[i].bufptr = 0;
481 tx_desc[i].length = 0;
482 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
485 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
486 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
488 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
489 rx_desc[i].bufptr = sc->rx_data[i].paddr;
490 rx_desc[i].length = 0;
491 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
492 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
494 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
497 /* Step 18: Initialize the maximum receive buffer length */
498 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
500 /* Step 19: Configure ethernet frame sizes */
501 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
502 tsec_set_mtu(sc, ifp->if_mtu);
504 /* Step 20: Enable Rx and RxBD sdata snooping */
505 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
506 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
508 /* Step 21: Reset collision counters in hardware */
509 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
510 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
511 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
512 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
513 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
515 /* Step 22: Mask all CAM interrupts */
516 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
517 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
519 /* Step 23: Enable Rx and Tx */
520 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
521 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
522 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
524 /* Step 24: Reset TSEC counters for Tx and Rx rings */
525 TSEC_TX_RX_COUNTERS_INIT(sc);
527 /* Step 25: Setup TCP/IP Off-Load engine */
529 tsec_offload_setup(sc);
531 /* Step 26: Setup multicast filters */
532 tsec_setup_multicast(sc);
534 /* Step 27: Activate network interface */
535 ifp->if_drv_flags |= IFF_DRV_RUNNING;
536 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
537 sc->tsec_if_flags = ifp->if_flags;
538 sc->tsec_watchdog = 0;
540 /* Schedule watchdog timeout */
541 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
545 tsec_set_mac_address(struct tsec_softc *sc)
547 uint32_t macbuf[2] = { 0, 0 };
548 char *macbufp, *curmac;
551 TSEC_GLOBAL_LOCK_ASSERT(sc);
553 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
554 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
557 macbufp = (char *)macbuf;
558 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
560 /* Correct order of MAC address bytes */
561 for (i = 1; i <= ETHER_ADDR_LEN; i++)
562 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
564 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
565 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
566 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
570 * DMA control function, if argument state is:
571 * 0 - DMA engine will be disabled
572 * 1 - DMA engine will be enabled
575 tsec_dma_ctl(struct tsec_softc *sc, int state)
578 uint32_t dma_flags, timeout;
582 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
586 /* Temporarily clear stop graceful stop bits. */
587 tsec_dma_ctl(sc, 1000);
590 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
594 /* Set write with response (WWR), wait (WOP) and snoop bits */
595 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
596 DMACTRL_WWR | DMACTRL_WOP);
598 /* Clear graceful stop bits */
599 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
602 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
606 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
610 /* Wait for DMA stop */
611 timeout = TSEC_READ_RETRY;
612 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
613 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
614 DELAY(TSEC_READ_DELAY);
617 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
620 /* Restart transmission function */
621 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
626 * Interrupts control function, if argument state is:
627 * 0 - all TSEC interrupts will be masked
628 * 1 - all TSEC interrupts will be unmasked
631 tsec_intrs_ctl(struct tsec_softc *sc, int state)
639 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
642 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
643 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
644 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
645 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
648 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
654 tsec_reset_mac(struct tsec_softc *sc)
656 uint32_t maccfg1_flags;
658 /* Set soft reset bit */
659 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
660 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
661 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
663 /* Clear soft reset bit */
664 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
665 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
666 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
670 tsec_watchdog(struct tsec_softc *sc)
674 TSEC_GLOBAL_LOCK_ASSERT(sc);
676 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
681 if_printf(ifp, "watchdog timeout\n");
684 tsec_init_locked(sc);
688 tsec_start(struct ifnet *ifp)
690 struct tsec_softc *sc = ifp->if_softc;
692 TSEC_TRANSMIT_LOCK(sc);
693 tsec_start_locked(ifp);
694 TSEC_TRANSMIT_UNLOCK(sc);
698 tsec_start_locked(struct ifnet *ifp)
700 struct tsec_softc *sc;
701 struct mbuf *m0, *mtmp;
702 struct tsec_tx_fcb *tx_fcb;
703 unsigned int queued = 0;
704 int csum_flags, fcb_inserted = 0;
708 TSEC_TRANSMIT_LOCK_ASSERT(sc);
710 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
714 if (sc->tsec_link == 0)
717 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
718 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
720 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
721 /* Get packet from the queue */
722 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
726 /* Insert TCP/IP Off-load frame control block */
727 csum_flags = m0->m_pkthdr.csum_flags;
730 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
734 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
736 tx_fcb->l3_offset = ETHER_HDR_LEN;
737 tx_fcb->l4_offset = sizeof(struct ip);
739 if (csum_flags & CSUM_IP)
740 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
743 if (csum_flags & CSUM_TCP)
744 tx_fcb->flags |= TSEC_TX_FCB_TCP |
745 TSEC_TX_FCB_CSUM_TCP_UDP;
747 if (csum_flags & CSUM_UDP)
748 tx_fcb->flags |= TSEC_TX_FCB_UDP |
749 TSEC_TX_FCB_CSUM_TCP_UDP;
754 mtmp = m_defrag(m0, M_NOWAIT);
758 if (tsec_encap(sc, m0, fcb_inserted)) {
759 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
760 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
766 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
767 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
770 /* Enable transmitter and watchdog timer */
771 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
772 sc->tsec_watchdog = 5;
777 tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
779 struct tsec_desc *tx_desc = NULL;
781 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
783 int csum_flag = 0, error, seg, nsegs;
785 TSEC_TRANSMIT_LOCK_ASSERT(sc);
789 if (TSEC_FREE_TX_DESC(sc) == 0) {
790 /* No free descriptors */
794 /* Fetch unused map */
795 mapp = TSEC_ALLOC_TX_MAP(sc);
797 /* Create mapping in DMA memory */
798 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
799 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
800 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
801 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
802 TSEC_FREE_TX_MAP(sc, mapp);
803 return ((error != 0) ? error : -1);
805 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
807 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
808 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
811 csum_flag = TSEC_TXBD_TOE;
813 /* Everything is ok, now we can send buffers */
814 for (seg = 0; seg < nsegs; seg++) {
815 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
817 tx_desc->length = segs[seg].ds_len;
818 tx_desc->bufptr = segs[seg].ds_addr;
825 * - transmit the CRC sequence after the last data byte
826 * - interrupt after the last buffer
829 (tx_desc->flags & TSEC_TXBD_W) |
830 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
831 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
834 /* Save mbuf and DMA mapping for release at later stage */
835 TSEC_PUT_TX_MBUF(sc, m0);
836 TSEC_PUT_TX_MAP(sc, mapp);
842 tsec_setfilter(struct tsec_softc *sc)
848 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
850 /* Promiscuous mode */
851 if (ifp->if_flags & IFF_PROMISC)
852 flags |= TSEC_RCTRL_PROM;
854 flags &= ~TSEC_RCTRL_PROM;
856 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
859 #ifdef DEVICE_POLLING
860 static poll_handler_t tsec_poll;
863 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
866 struct tsec_softc *sc = ifp->if_softc;
871 TSEC_GLOBAL_LOCK(sc);
872 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
873 TSEC_GLOBAL_UNLOCK(sc);
877 if (cmd == POLL_AND_CHECK_STATUS) {
878 tsec_error_intr_locked(sc, count);
880 /* Clear all events reported */
881 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
882 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
885 tsec_transmit_intr_locked(sc);
887 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
889 rx_npkts = tsec_receive_intr_locked(sc, count);
891 TSEC_RECEIVE_UNLOCK(sc);
895 #endif /* DEVICE_POLLING */
898 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
900 struct tsec_softc *sc = ifp->if_softc;
901 struct ifreq *ifr = (struct ifreq *)data;
909 TSEC_GLOBAL_LOCK(sc);
910 if (tsec_set_mtu(sc, ifr->ifr_mtu))
911 ifp->if_mtu = ifr->ifr_mtu;
914 TSEC_GLOBAL_UNLOCK(sc);
917 TSEC_GLOBAL_LOCK(sc);
918 if (ifp->if_flags & IFF_UP) {
919 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
920 if ((sc->tsec_if_flags ^ ifp->if_flags) &
924 if ((sc->tsec_if_flags ^ ifp->if_flags) &
926 tsec_setup_multicast(sc);
928 tsec_init_locked(sc);
929 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
932 sc->tsec_if_flags = ifp->if_flags;
933 TSEC_GLOBAL_UNLOCK(sc);
937 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
938 TSEC_GLOBAL_LOCK(sc);
939 tsec_setup_multicast(sc);
940 TSEC_GLOBAL_UNLOCK(sc);
944 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
948 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
949 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
950 TSEC_GLOBAL_LOCK(sc);
951 ifp->if_capenable &= ~IFCAP_HWCSUM;
952 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
953 tsec_offload_setup(sc);
954 TSEC_GLOBAL_UNLOCK(sc);
956 #ifdef DEVICE_POLLING
957 if (mask & IFCAP_POLLING) {
958 if (ifr->ifr_reqcap & IFCAP_POLLING) {
959 error = ether_poll_register(tsec_poll, ifp);
963 TSEC_GLOBAL_LOCK(sc);
964 /* Disable interrupts */
965 tsec_intrs_ctl(sc, 0);
966 ifp->if_capenable |= IFCAP_POLLING;
967 TSEC_GLOBAL_UNLOCK(sc);
969 error = ether_poll_deregister(ifp);
970 TSEC_GLOBAL_LOCK(sc);
971 /* Enable interrupts */
972 tsec_intrs_ctl(sc, 1);
973 ifp->if_capenable &= ~IFCAP_POLLING;
974 TSEC_GLOBAL_UNLOCK(sc);
981 error = ether_ioctl(ifp, command, data);
984 /* Flush buffers if not empty */
985 if (ifp->if_flags & IFF_UP)
991 tsec_ifmedia_upd(struct ifnet *ifp)
993 struct tsec_softc *sc = ifp->if_softc;
994 struct mii_data *mii;
996 TSEC_TRANSMIT_LOCK(sc);
1001 TSEC_TRANSMIT_UNLOCK(sc);
1006 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1008 struct tsec_softc *sc = ifp->if_softc;
1009 struct mii_data *mii;
1011 TSEC_TRANSMIT_LOCK(sc);
1016 ifmr->ifm_active = mii->mii_media_active;
1017 ifmr->ifm_status = mii->mii_media_status;
1019 TSEC_TRANSMIT_UNLOCK(sc);
1023 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1026 struct mbuf *new_mbuf;
1027 bus_dma_segment_t seg[1];
1030 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1032 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1033 if (new_mbuf == NULL)
1035 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1038 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1039 bus_dmamap_unload(tag, map);
1042 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1044 KASSERT(nsegs == 1, ("Too many segments returned!"));
1045 if (nsegs != 1 || error)
1046 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1050 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1058 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1059 ("Wrong alignment of RX buffer!"));
1061 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1063 (*mbufp) = new_mbuf;
1064 (*paddr) = seg->ds_addr;
1069 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1073 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1075 *paddr = segs->ds_addr;
1079 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1080 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1084 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1085 error = bus_dma_tag_create(NULL, /* parent */
1086 PAGE_SIZE, 0, /* alignment, boundary */
1087 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1088 BUS_SPACE_MAXADDR, /* highaddr */
1089 NULL, NULL, /* filtfunc, filtfuncarg */
1090 dsize, 1, /* maxsize, nsegments */
1091 dsize, 0, /* maxsegsz, flags */
1092 NULL, NULL, /* lockfunc, lockfuncarg */
1096 device_printf(dev, "failed to allocate busdma %s tag\n",
1102 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1105 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1107 bus_dma_tag_destroy(*dtag);
1112 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1113 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1115 device_printf(dev, "cannot get address of the %s "
1116 "descriptors\n", dname);
1117 bus_dmamem_free(*dtag, *vaddr, *dmap);
1118 bus_dma_tag_destroy(*dtag);
1127 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1133 /* Unmap descriptors from DMA memory */
1134 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1135 BUS_DMASYNC_POSTWRITE);
1136 bus_dmamap_unload(dtag, dmap);
1138 /* Free descriptors memory */
1139 bus_dmamem_free(dtag, vaddr, dmap);
1141 /* Destroy descriptors tag */
1142 bus_dma_tag_destroy(dtag);
1146 tsec_free_dma(struct tsec_softc *sc)
1151 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1152 if (sc->tx_map_data[i] != NULL)
1153 bus_dmamap_destroy(sc->tsec_tx_mtag,
1154 sc->tx_map_data[i]);
1155 /* Destroy tag for TX mbufs */
1156 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1158 /* Free RX mbufs and maps */
1159 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1160 if (sc->rx_data[i].mbuf) {
1161 /* Unload buffer from DMA */
1162 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1163 BUS_DMASYNC_POSTREAD);
1164 bus_dmamap_unload(sc->tsec_rx_mtag,
1165 sc->rx_data[i].map);
1168 m_freem(sc->rx_data[i].mbuf);
1170 /* Destroy map for this buffer */
1171 if (sc->rx_data[i].map != NULL)
1172 bus_dmamap_destroy(sc->tsec_rx_mtag,
1173 sc->rx_data[i].map);
1175 /* Destroy tag for RX mbufs */
1176 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1178 /* Unload TX/RX descriptors */
1179 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1181 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1186 tsec_stop(struct tsec_softc *sc)
1193 TSEC_GLOBAL_LOCK_ASSERT(sc);
1197 /* Disable interface and watchdog timer */
1198 callout_stop(&sc->tsec_callout);
1199 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1200 sc->tsec_watchdog = 0;
1202 /* Disable all interrupts and stop DMA */
1203 tsec_intrs_ctl(sc, 0);
1204 tsec_dma_ctl(sc, 0);
1206 /* Remove pending data from TX queue */
1207 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1208 m0 = TSEC_GET_TX_MBUF(sc);
1209 mapp = TSEC_GET_TX_MAP(sc);
1211 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1212 BUS_DMASYNC_POSTWRITE);
1213 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1215 TSEC_FREE_TX_MAP(sc, mapp);
1219 /* Disable RX and TX */
1220 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1221 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1222 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1227 tsec_tick(void *arg)
1229 struct tsec_softc *sc = arg;
1233 TSEC_GLOBAL_LOCK(sc);
1238 link = sc->tsec_link;
1240 mii_tick(sc->tsec_mii);
1242 if (link == 0 && sc->tsec_link == 1 &&
1243 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1244 tsec_start_locked(ifp);
1246 /* Schedule another timeout one second from now. */
1247 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1249 TSEC_GLOBAL_UNLOCK(sc);
1253 * This is the core RX routine. It replenishes mbufs in the descriptor and
1254 * sends data which have been dma'ed into host memory to upper layer.
1256 * Loops at most count times if count is > 0, or until done if count < 0.
1259 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1261 struct tsec_desc *rx_desc;
1263 struct rx_data_type *rx_data;
1270 TSEC_RECEIVE_LOCK_ASSERT(sc);
1273 rx_data = sc->rx_data;
1277 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1278 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1280 for (c = 0; ; c++) {
1281 if (count >= 0 && count-- == 0)
1284 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1285 flags = rx_desc->flags;
1287 /* Check if there is anything to receive */
1288 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1290 * Avoid generating another interrupt
1292 if (flags & TSEC_RXBD_E)
1293 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1294 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1296 * We didn't consume current descriptor and have to
1297 * return it to the queue
1299 TSEC_BACK_CUR_RX_DESC(sc);
1303 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1304 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1306 rx_desc->length = 0;
1307 rx_desc->flags = (rx_desc->flags &
1308 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1310 if (sc->frame != NULL) {
1318 /* Ok... process frame */
1319 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1320 m = rx_data[i].mbuf;
1321 m->m_len = rx_desc->length;
1323 if (sc->frame != NULL) {
1324 if ((flags & TSEC_RXBD_L) != 0)
1325 m->m_len -= m_length(sc->frame, NULL);
1327 m->m_flags &= ~M_PKTHDR;
1328 m_cat(sc->frame, m);
1335 if ((flags & TSEC_RXBD_L) != 0) {
1340 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1341 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1344 * We ran out of mbufs; didn't consume current
1345 * descriptor and have to return it to the queue.
1347 TSEC_BACK_CUR_RX_DESC(sc);
1351 /* Attach new buffer to descriptor and clear flags */
1352 rx_desc->bufptr = rx_data[i].paddr;
1353 rx_desc->length = 0;
1354 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1355 TSEC_RXBD_E | TSEC_RXBD_I;
1358 m->m_pkthdr.rcvif = ifp;
1361 m_adj(m, -ETHER_CRC_LEN);
1364 tsec_offload_process_frame(sc, m);
1366 TSEC_RECEIVE_UNLOCK(sc);
1367 (*ifp->if_input)(ifp, m);
1368 TSEC_RECEIVE_LOCK(sc);
1373 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1377 * Make sure TSEC receiver is not halted.
1379 * Various conditions can stop the TSEC receiver, but not all are
1380 * signaled and handled by error interrupt, so make sure the receiver
1381 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1382 * halted, and is harmless if already running.
1384 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1389 tsec_receive_intr(void *arg)
1391 struct tsec_softc *sc = arg;
1393 TSEC_RECEIVE_LOCK(sc);
1395 #ifdef DEVICE_POLLING
1396 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1397 TSEC_RECEIVE_UNLOCK(sc);
1402 /* Confirm the interrupt was received by driver */
1403 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1404 tsec_receive_intr_locked(sc, -1);
1406 TSEC_RECEIVE_UNLOCK(sc);
1410 tsec_transmit_intr_locked(struct tsec_softc *sc)
1412 struct tsec_desc *tx_desc;
1418 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1422 /* Update collision statistics */
1423 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL);
1425 /* Reset collision counters in hardware */
1426 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1427 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1428 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1429 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1430 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1432 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1435 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1436 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1437 if (tx_desc->flags & TSEC_TXBD_R) {
1438 TSEC_BACK_DIRTY_TX_DESC(sc);
1442 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1446 * This is the last buf in this packet, so unmap and free it.
1448 m0 = TSEC_GET_TX_MBUF(sc);
1449 mapp = TSEC_GET_TX_MAP(sc);
1451 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1452 BUS_DMASYNC_POSTWRITE);
1453 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1455 TSEC_FREE_TX_MAP(sc, mapp);
1461 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1465 /* Now send anything that was pending */
1466 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1467 tsec_start_locked(ifp);
1469 /* Stop wathdog if all sent */
1470 if (TSEC_EMPTYQ_TX_MBUF(sc))
1471 sc->tsec_watchdog = 0;
1476 tsec_transmit_intr(void *arg)
1478 struct tsec_softc *sc = arg;
1480 TSEC_TRANSMIT_LOCK(sc);
1482 #ifdef DEVICE_POLLING
1483 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1484 TSEC_TRANSMIT_UNLOCK(sc);
1488 /* Confirm the interrupt was received by driver */
1489 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1490 tsec_transmit_intr_locked(sc);
1492 TSEC_TRANSMIT_UNLOCK(sc);
1496 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1501 TSEC_GLOBAL_LOCK_ASSERT(sc);
1505 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1507 /* Clear events bits in hardware */
1508 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1509 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1510 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1511 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1513 /* Check transmitter errors */
1514 if (eflags & TSEC_IEVENT_TXE) {
1517 if (eflags & TSEC_IEVENT_LC)
1518 ifp->if_collisions++;
1520 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1523 /* Check receiver errors */
1524 if (eflags & TSEC_IEVENT_BSY) {
1528 /* Get data from RX buffers */
1529 tsec_receive_intr_locked(sc, count);
1532 if (ifp->if_flags & IFF_DEBUG)
1533 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1536 if (eflags & TSEC_IEVENT_EBERR) {
1537 if_printf(ifp, "System bus error occurred during"
1538 "DMA transaction (flags: 0x%x)\n", eflags);
1539 tsec_init_locked(sc);
1542 if (eflags & TSEC_IEVENT_BABT)
1545 if (eflags & TSEC_IEVENT_BABR)
1550 tsec_error_intr(void *arg)
1552 struct tsec_softc *sc = arg;
1554 TSEC_GLOBAL_LOCK(sc);
1555 tsec_error_intr_locked(sc, -1);
1556 TSEC_GLOBAL_UNLOCK(sc);
1560 tsec_miibus_readreg(device_t dev, int phy, int reg)
1562 struct tsec_softc *sc;
1565 sc = device_get_softc(dev);
1567 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1568 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0);
1569 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1571 timeout = TSEC_READ_RETRY;
1572 while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
1573 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1574 DELAY(TSEC_READ_DELAY);
1577 device_printf(dev, "Timeout while reading from PHY!\n");
1579 return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT));
1583 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1585 struct tsec_softc *sc;
1588 sc = device_get_softc(dev);
1590 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1591 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value);
1593 timeout = TSEC_READ_RETRY;
1594 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
1596 DELAY(TSEC_READ_DELAY);
1599 device_printf(dev, "Timeout while writing to PHY!\n");
1605 tsec_miibus_statchg(device_t dev)
1607 struct tsec_softc *sc;
1608 struct mii_data *mii;
1609 uint32_t ecntrl, id, tmp;
1612 sc = device_get_softc(dev);
1614 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1616 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1618 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1619 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1621 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1623 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1626 tmp |= TSEC_MACCFG2_GMII;
1627 sc->tsec_link = link;
1631 tmp |= TSEC_MACCFG2_MII;
1632 sc->tsec_link = link;
1636 device_printf(dev, "No speed selected but link "
1642 device_printf(dev, "Unknown speed (%d), link %s!\n",
1643 IFM_SUBTYPE(mii->mii_media_active),
1644 ((link) ? "up" : "down"));
1647 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1649 /* XXX kludge - use circumstantial evidence for reduced mode. */
1650 id = TSEC_READ(sc, TSEC_REG_ID2);
1652 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1653 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1654 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1659 tsec_add_sysctls(struct tsec_softc *sc)
1661 struct sysctl_ctx_list *ctx;
1662 struct sysctl_oid_list *children;
1663 struct sysctl_oid *tree;
1665 ctx = device_get_sysctl_ctx(sc->dev);
1666 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1667 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1668 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1669 children = SYSCTL_CHILDREN(tree);
1671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1672 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1673 "I", "IC RX time threshold (0-65535)");
1674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1675 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1676 "I", "IC RX frame count threshold (0-255)");
1678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1679 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1680 "I", "IC TX time threshold (0-65535)");
1681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1682 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1683 "I", "IC TX frame count threshold (0-255)");
1687 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1688 * interrupt is raised either upon:
1690 * - threshold-defined period of time elapsed, or
1691 * - threshold-defined number of frames is received/transmitted,
1692 * whichever occurs first.
1694 * The following sysctls regulate IC behaviour (for TX/RX separately):
1696 * dev.tsec.<unit>.int_coal.rx_time
1697 * dev.tsec.<unit>.int_coal.rx_count
1698 * dev.tsec.<unit>.int_coal.tx_time
1699 * dev.tsec.<unit>.int_coal.tx_count
1703 * - 0 for either time or count disables IC on the given TX/RX path
1705 * - count: 1-255 (expresses frame count number; note that value of 1 is
1706 * effectively IC off)
1708 * - time: 1-65535 (value corresponds to a real time period and is
1709 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1710 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1711 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1712 * TSEC reference manual.
1715 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1719 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1721 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1723 error = sysctl_handle_int(oidp, &time, 0, req);
1731 if (arg2 == TSEC_IC_RX) {
1732 sc->rx_ic_time = time;
1735 sc->tx_ic_time = time;
1744 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1748 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1750 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1752 error = sysctl_handle_int(oidp, &count, 0, req);
1760 if (arg2 == TSEC_IC_RX) {
1761 sc->rx_ic_count = count;
1764 sc->tx_ic_count = count;
1773 tsec_set_rxic(struct tsec_softc *sc)
1777 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1781 rxic_val = 0x80000000;
1782 rxic_val |= (sc->rx_ic_count << 21);
1783 rxic_val |= sc->rx_ic_time;
1786 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1790 tsec_set_txic(struct tsec_softc *sc)
1794 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1798 txic_val = 0x80000000;
1799 txic_val |= (sc->tx_ic_count << 21);
1800 txic_val |= sc->tx_ic_time;
1803 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1807 tsec_offload_setup(struct tsec_softc *sc)
1809 struct ifnet *ifp = sc->tsec_ifp;
1812 TSEC_GLOBAL_LOCK_ASSERT(sc);
1814 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1815 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1817 if (ifp->if_capenable & IFCAP_TXCSUM)
1818 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1820 ifp->if_hwassist = 0;
1822 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1824 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1825 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1826 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1828 if (ifp->if_capenable & IFCAP_RXCSUM)
1829 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1830 TSEC_RCTRL_PRSDEP_PARSE_L234;
1832 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1837 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1839 struct tsec_rx_fcb rx_fcb;
1841 int protocol, flags;
1843 TSEC_RECEIVE_LOCK_ASSERT(sc);
1845 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1846 flags = rx_fcb.flags;
1847 protocol = rx_fcb.protocol;
1849 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1850 csum_flags |= CSUM_IP_CHECKED;
1852 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1853 csum_flags |= CSUM_IP_VALID;
1856 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1857 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1858 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1860 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1861 m->m_pkthdr.csum_data = 0xFFFF;
1864 m->m_pkthdr.csum_flags = csum_flags;
1866 if (flags & TSEC_RX_FCB_VLAN) {
1867 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1868 m->m_flags |= M_VLANTAG;
1871 m_adj(m, sizeof(struct tsec_rx_fcb));
1875 tsec_setup_multicast(struct tsec_softc *sc)
1877 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1878 struct ifnet *ifp = sc->tsec_ifp;
1879 struct ifmultiaddr *ifma;
1883 TSEC_GLOBAL_LOCK_ASSERT(sc);
1885 if (ifp->if_flags & IFF_ALLMULTI) {
1886 for (i = 0; i < 8; i++)
1887 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1892 if_maddr_rlock(ifp);
1893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1895 if (ifma->ifma_addr->sa_family != AF_LINK)
1898 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1899 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1901 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1903 if_maddr_runlock(ifp);
1905 for (i = 0; i < 8; i++)
1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1910 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1913 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1915 TSEC_GLOBAL_LOCK_ASSERT(sc);
1917 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1918 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);