2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #ifdef HAVE_KERNEL_OPTION_HEADERS
36 #include "opt_device_polling.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/endian.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <machine/bus.h>
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
69 #include <dev/tsec/if_tsec.h>
70 #include <dev/tsec/if_tsecreg.h>
72 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
73 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
75 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
76 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
77 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
78 static void tsec_free_dma(struct tsec_softc *sc);
79 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
80 static int tsec_ifmedia_upd(struct ifnet *ifp);
81 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
82 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
83 struct mbuf **mbufp, uint32_t *paddr);
84 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
86 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
87 static void tsec_init(void *xsc);
88 static void tsec_init_locked(struct tsec_softc *sc);
89 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
90 static void tsec_reset_mac(struct tsec_softc *sc);
91 static void tsec_setfilter(struct tsec_softc *sc);
92 static void tsec_set_mac_address(struct tsec_softc *sc);
93 static void tsec_start(struct ifnet *ifp);
94 static void tsec_start_locked(struct ifnet *ifp);
95 static void tsec_stop(struct tsec_softc *sc);
96 static void tsec_tick(void *arg);
97 static void tsec_watchdog(struct tsec_softc *sc);
98 static void tsec_add_sysctls(struct tsec_softc *sc);
99 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
100 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
101 static void tsec_set_rxic(struct tsec_softc *sc);
102 static void tsec_set_txic(struct tsec_softc *sc);
103 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
105 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
106 static void tsec_offload_setup(struct tsec_softc *sc);
107 static void tsec_offload_process_frame(struct tsec_softc *sc,
109 static void tsec_setup_multicast(struct tsec_softc *sc);
110 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
112 devclass_t tsec_devclass;
113 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
114 MODULE_DEPEND(tsec, ether, 1, 1, 1);
115 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
117 struct mtx tsec_phy_mtx;
120 tsec_attach(struct tsec_softc *sc)
122 uint8_t hwaddr[ETHER_ADDR_LEN];
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
134 /* Stop DMA engine if enabled by firmware */
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
150 tsec_add_sysctls(sc);
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
183 device_printf(sc->dev, "failed to allocate busdma tag "
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
201 device_printf(sc->dev, "failed to allocate busdma tag "
207 /* Create TX busdma maps */
208 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
209 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
210 &sc->tx_bufmap[i].map);
212 device_printf(sc->dev, "failed to init TX ring\n");
216 sc->tx_bufmap[i].map_initialized = 1;
219 /* Create RX busdma maps and zero mbuf handlers */
220 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
221 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
222 &sc->rx_data[i].map);
224 device_printf(sc->dev, "failed to init RX ring\n");
228 sc->rx_data[i].mbuf = NULL;
231 /* Create mbufs for RX buffers */
232 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
233 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
234 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
236 device_printf(sc->dev, "can't load rx DMA map %d, "
237 "error = %d\n", i, error);
243 /* Create network interface for upper layers */
244 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
246 device_printf(sc->dev, "if_alloc() failed\n");
252 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
253 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
254 ifp->if_init = tsec_init;
255 ifp->if_start = tsec_start;
256 ifp->if_ioctl = tsec_ioctl;
258 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
259 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
260 IFQ_SET_READY(&ifp->if_snd);
262 ifp->if_capabilities = IFCAP_VLAN_MTU;
264 ifp->if_capabilities |= IFCAP_HWCSUM;
266 ifp->if_capenable = ifp->if_capabilities;
268 #ifdef DEVICE_POLLING
269 /* Advertise that polling is supported */
270 ifp->if_capabilities |= IFCAP_POLLING;
274 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
275 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
278 device_printf(sc->dev, "attaching PHYs failed\n");
284 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
286 /* Set MAC address */
287 tsec_get_hwaddr(sc, hwaddr);
288 ether_ifattach(ifp, hwaddr);
294 tsec_detach(struct tsec_softc *sc)
297 if (sc->tsec_ifp != NULL) {
298 #ifdef DEVICE_POLLING
299 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
300 ether_poll_deregister(sc->tsec_ifp);
303 /* Stop TSEC controller and free TX queue */
305 tsec_shutdown(sc->dev);
307 /* Detach network interface */
308 ether_ifdetach(sc->tsec_ifp);
309 if_free(sc->tsec_ifp);
313 /* Free DMA resources */
320 tsec_shutdown(device_t dev)
322 struct tsec_softc *sc;
324 sc = device_get_softc(dev);
326 TSEC_GLOBAL_LOCK(sc);
328 TSEC_GLOBAL_UNLOCK(sc);
333 tsec_suspend(device_t dev)
336 /* TODO not implemented! */
341 tsec_resume(device_t dev)
344 /* TODO not implemented! */
351 struct tsec_softc *sc = xsc;
353 TSEC_GLOBAL_LOCK(sc);
354 tsec_init_locked(sc);
355 TSEC_GLOBAL_UNLOCK(sc);
359 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
364 * The status indicators are not set immediatly after a command.
365 * Discard the first value.
367 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
369 timeout = TSEC_READ_RETRY;
370 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
371 DELAY(TSEC_READ_DELAY);
373 return (timeout == 0);
377 tsec_init_locked(struct tsec_softc *sc)
379 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
380 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
381 struct ifnet *ifp = sc->tsec_ifp;
385 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
388 TSEC_GLOBAL_LOCK_ASSERT(sc);
392 * These steps are according to the MPC8555E PowerQUICCIII RM:
393 * 14.7 Initialization/Application Information
396 /* Step 1: soft reset MAC */
399 /* Step 2: Initialize MACCFG2 */
400 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
401 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
402 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
403 TSEC_MACCFG2_GMII | /* I/F Mode bit */
404 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
407 /* Step 3: Initialize ECNTRL
408 * While the documentation states that R100M is ignored if RPM is
409 * not set, it does seem to be needed to get the orange boxes to
410 * work (which have a Marvell 88E1111 PHY). Go figure.
414 * XXX kludge - use circumstancial evidence to program ECNTRL
415 * correctly. Ideally we need some board information to guide
418 i = TSEC_READ(sc, TSEC_REG_ID2);
420 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
421 : TSEC_ECNTRL_R100M; /* Orange + CDS */
422 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
424 /* Step 4: Initialize MAC station address */
425 tsec_set_mac_address(sc);
428 * Step 5: Assign a Physical address to the TBI so as to not conflict
429 * with the external PHY physical address
431 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
435 /* Step 6: Reset the management interface */
436 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
438 /* Step 7: Setup the MII Mgmt clock speed */
439 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
441 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
442 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
446 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
450 /* Step 9: Setup the MII Mgmt */
451 mii_mediachg(sc->tsec_mii);
453 /* Step 10: Clear IEVENT register */
454 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
456 /* Step 11: Enable interrupts */
457 #ifdef DEVICE_POLLING
459 * ...only if polling is not turned on. Disable interrupts explicitly
460 * if polling is enabled.
462 if (ifp->if_capenable & IFCAP_POLLING )
463 tsec_intrs_ctl(sc, 0);
465 #endif /* DEVICE_POLLING */
466 tsec_intrs_ctl(sc, 1);
468 /* Step 12: Initialize IADDRn */
469 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
470 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
471 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
472 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
473 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
474 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
475 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
476 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
478 /* Step 13: Initialize GADDRn */
479 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
480 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
481 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
482 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
483 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
484 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
485 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
486 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
488 /* Step 14: Initialize RCTRL */
489 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
491 /* Step 15: Initialize DMACTRL */
494 /* Step 16: Initialize FIFO_PAUSE_CTRL */
495 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
498 * Step 17: Initialize transmit/receive descriptor rings.
499 * Initialize TBASE and RBASE.
501 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
502 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
504 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
505 tx_desc[i].bufptr = 0;
506 tx_desc[i].length = 0;
507 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
510 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
513 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
514 rx_desc[i].bufptr = sc->rx_data[i].paddr;
515 rx_desc[i].length = 0;
516 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
517 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
519 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
522 /* Step 18: Initialize the maximum receive buffer length */
523 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
525 /* Step 19: Configure ethernet frame sizes */
526 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
527 tsec_set_mtu(sc, ifp->if_mtu);
529 /* Step 20: Enable Rx and RxBD sdata snooping */
530 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
531 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
533 /* Step 21: Reset collision counters in hardware */
534 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
535 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
536 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
537 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
538 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
540 /* Step 22: Mask all CAM interrupts */
541 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
542 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
544 /* Step 23: Enable Rx and Tx */
545 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
546 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
547 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
549 /* Step 24: Reset TSEC counters for Tx and Rx rings */
550 TSEC_TX_RX_COUNTERS_INIT(sc);
552 /* Step 25: Setup TCP/IP Off-Load engine */
554 tsec_offload_setup(sc);
556 /* Step 26: Setup multicast filters */
557 tsec_setup_multicast(sc);
559 /* Step 27: Activate network interface */
560 ifp->if_drv_flags |= IFF_DRV_RUNNING;
561 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
562 sc->tsec_if_flags = ifp->if_flags;
563 sc->tsec_watchdog = 0;
565 /* Schedule watchdog timeout */
566 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
570 tsec_set_mac_address(struct tsec_softc *sc)
572 uint32_t macbuf[2] = { 0, 0 };
573 char *macbufp, *curmac;
576 TSEC_GLOBAL_LOCK_ASSERT(sc);
578 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
579 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
582 macbufp = (char *)macbuf;
583 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
585 /* Correct order of MAC address bytes */
586 for (i = 1; i <= ETHER_ADDR_LEN; i++)
587 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
589 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
590 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
591 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
595 * DMA control function, if argument state is:
596 * 0 - DMA engine will be disabled
597 * 1 - DMA engine will be enabled
600 tsec_dma_ctl(struct tsec_softc *sc, int state)
603 uint32_t dma_flags, timeout;
607 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
611 /* Temporarily clear stop graceful stop bits. */
612 tsec_dma_ctl(sc, 1000);
615 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
619 /* Set write with response (WWR), wait (WOP) and snoop bits */
620 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
621 DMACTRL_WWR | DMACTRL_WOP);
623 /* Clear graceful stop bits */
624 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
627 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
631 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
635 /* Wait for DMA stop */
636 timeout = TSEC_READ_RETRY;
637 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
638 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
639 DELAY(TSEC_READ_DELAY);
642 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
645 /* Restart transmission function */
646 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
651 * Interrupts control function, if argument state is:
652 * 0 - all TSEC interrupts will be masked
653 * 1 - all TSEC interrupts will be unmasked
656 tsec_intrs_ctl(struct tsec_softc *sc, int state)
664 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
667 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
668 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
669 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
670 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
673 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
679 tsec_reset_mac(struct tsec_softc *sc)
681 uint32_t maccfg1_flags;
683 /* Set soft reset bit */
684 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
685 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
686 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
688 /* Clear soft reset bit */
689 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
690 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
691 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
695 tsec_watchdog(struct tsec_softc *sc)
699 TSEC_GLOBAL_LOCK_ASSERT(sc);
701 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
705 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
706 if_printf(ifp, "watchdog timeout\n");
709 tsec_init_locked(sc);
713 tsec_start(struct ifnet *ifp)
715 struct tsec_softc *sc = ifp->if_softc;
717 TSEC_TRANSMIT_LOCK(sc);
718 tsec_start_locked(ifp);
719 TSEC_TRANSMIT_UNLOCK(sc);
723 tsec_start_locked(struct ifnet *ifp)
725 struct tsec_softc *sc;
727 struct tsec_tx_fcb *tx_fcb;
735 TSEC_TRANSMIT_LOCK_ASSERT(sc);
737 if (sc->tsec_link == 0)
740 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
741 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
744 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
745 /* No free descriptors */
746 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
750 /* Get packet from the queue */
751 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
755 /* Insert TCP/IP Off-load frame control block */
757 csum_flags = m0->m_pkthdr.csum_flags;
759 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
763 if (csum_flags & CSUM_IP)
764 fcb_flags |= TSEC_TX_FCB_IP4 |
767 if (csum_flags & CSUM_TCP)
768 fcb_flags |= TSEC_TX_FCB_TCP |
769 TSEC_TX_FCB_CSUM_TCP_UDP;
771 if (csum_flags & CSUM_UDP)
772 fcb_flags |= TSEC_TX_FCB_UDP |
773 TSEC_TX_FCB_CSUM_TCP_UDP;
775 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
776 tx_fcb->flags = fcb_flags;
777 tx_fcb->l3_offset = ETHER_HDR_LEN;
778 tx_fcb->l4_offset = sizeof(struct ip);
781 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
783 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
784 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
787 /* Enable transmitter and watchdog timer */
788 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
789 sc->tsec_watchdog = 5;
794 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
795 uint16_t fcb_flags, int *start_tx)
797 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
799 struct tsec_bufmap *tx_bufmap;
803 TSEC_TRANSMIT_LOCK_ASSERT(sc);
805 tx_idx = sc->tx_idx_head;
806 tx_bufmap = &sc->tx_bufmap[tx_idx];
808 /* Create mapping in DMA memory */
809 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
810 segs, &nsegs, BUS_DMA_NOWAIT);
811 if (error == EFBIG) {
812 /* Too many segments! Defrag and try again. */
813 struct mbuf *m = m_defrag(m0, M_NOWAIT);
820 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
821 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
829 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
830 BUS_DMASYNC_PREWRITE);
831 tx_bufmap->mbuf = m0;
834 * Fill in the TX descriptors back to front so that READY bit in first
835 * descriptor is set last.
837 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
838 sc->tx_idx_head = tx_idx;
839 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
840 for (i = nsegs - 1; i >= 0; i--) {
841 struct tsec_desc *tx_desc;
843 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
844 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
845 tx_desc->length = segs[i].ds_len;
846 tx_desc->bufptr = segs[i].ds_addr;
852 flags |= TSEC_TXBD_TOE;
860 * - transmit the CRC sequence after the last data byte
861 * - interrupt after the last buffer
863 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
864 TSEC_TXBD_W : 0) | flags;
866 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
874 tsec_setfilter(struct tsec_softc *sc)
880 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
882 /* Promiscuous mode */
883 if (ifp->if_flags & IFF_PROMISC)
884 flags |= TSEC_RCTRL_PROM;
886 flags &= ~TSEC_RCTRL_PROM;
888 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
891 #ifdef DEVICE_POLLING
892 static poll_handler_t tsec_poll;
895 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
898 struct tsec_softc *sc = ifp->if_softc;
903 TSEC_GLOBAL_LOCK(sc);
904 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
905 TSEC_GLOBAL_UNLOCK(sc);
909 if (cmd == POLL_AND_CHECK_STATUS) {
910 tsec_error_intr_locked(sc, count);
912 /* Clear all events reported */
913 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
914 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
917 tsec_transmit_intr_locked(sc);
919 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
921 rx_npkts = tsec_receive_intr_locked(sc, count);
923 TSEC_RECEIVE_UNLOCK(sc);
927 #endif /* DEVICE_POLLING */
930 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
932 struct tsec_softc *sc = ifp->if_softc;
933 struct ifreq *ifr = (struct ifreq *)data;
938 TSEC_GLOBAL_LOCK(sc);
939 if (tsec_set_mtu(sc, ifr->ifr_mtu))
940 ifp->if_mtu = ifr->ifr_mtu;
943 TSEC_GLOBAL_UNLOCK(sc);
946 TSEC_GLOBAL_LOCK(sc);
947 if (ifp->if_flags & IFF_UP) {
948 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
949 if ((sc->tsec_if_flags ^ ifp->if_flags) &
953 if ((sc->tsec_if_flags ^ ifp->if_flags) &
955 tsec_setup_multicast(sc);
957 tsec_init_locked(sc);
958 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
961 sc->tsec_if_flags = ifp->if_flags;
962 TSEC_GLOBAL_UNLOCK(sc);
966 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
967 TSEC_GLOBAL_LOCK(sc);
968 tsec_setup_multicast(sc);
969 TSEC_GLOBAL_UNLOCK(sc);
973 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
977 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
978 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
979 TSEC_GLOBAL_LOCK(sc);
980 ifp->if_capenable &= ~IFCAP_HWCSUM;
981 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
982 tsec_offload_setup(sc);
983 TSEC_GLOBAL_UNLOCK(sc);
985 #ifdef DEVICE_POLLING
986 if (mask & IFCAP_POLLING) {
987 if (ifr->ifr_reqcap & IFCAP_POLLING) {
988 error = ether_poll_register(tsec_poll, ifp);
992 TSEC_GLOBAL_LOCK(sc);
993 /* Disable interrupts */
994 tsec_intrs_ctl(sc, 0);
995 ifp->if_capenable |= IFCAP_POLLING;
996 TSEC_GLOBAL_UNLOCK(sc);
998 error = ether_poll_deregister(ifp);
999 TSEC_GLOBAL_LOCK(sc);
1000 /* Enable interrupts */
1001 tsec_intrs_ctl(sc, 1);
1002 ifp->if_capenable &= ~IFCAP_POLLING;
1003 TSEC_GLOBAL_UNLOCK(sc);
1010 error = ether_ioctl(ifp, command, data);
1013 /* Flush buffers if not empty */
1014 if (ifp->if_flags & IFF_UP)
1020 tsec_ifmedia_upd(struct ifnet *ifp)
1022 struct tsec_softc *sc = ifp->if_softc;
1023 struct mii_data *mii;
1025 TSEC_TRANSMIT_LOCK(sc);
1030 TSEC_TRANSMIT_UNLOCK(sc);
1035 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1037 struct tsec_softc *sc = ifp->if_softc;
1038 struct mii_data *mii;
1040 TSEC_TRANSMIT_LOCK(sc);
1045 ifmr->ifm_active = mii->mii_media_active;
1046 ifmr->ifm_status = mii->mii_media_status;
1048 TSEC_TRANSMIT_UNLOCK(sc);
1052 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1055 struct mbuf *new_mbuf;
1056 bus_dma_segment_t seg[1];
1059 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1061 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1062 if (new_mbuf == NULL)
1064 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1067 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1068 bus_dmamap_unload(tag, map);
1071 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1073 KASSERT(nsegs == 1, ("Too many segments returned!"));
1074 if (nsegs != 1 || error)
1075 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1079 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1087 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1088 ("Wrong alignment of RX buffer!"));
1090 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1092 (*mbufp) = new_mbuf;
1093 (*paddr) = seg->ds_addr;
1098 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1102 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1104 *paddr = segs->ds_addr;
1108 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1109 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1113 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1114 error = bus_dma_tag_create(NULL, /* parent */
1115 PAGE_SIZE, 0, /* alignment, boundary */
1116 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1117 BUS_SPACE_MAXADDR, /* highaddr */
1118 NULL, NULL, /* filtfunc, filtfuncarg */
1119 dsize, 1, /* maxsize, nsegments */
1120 dsize, 0, /* maxsegsz, flags */
1121 NULL, NULL, /* lockfunc, lockfuncarg */
1125 device_printf(dev, "failed to allocate busdma %s tag\n",
1131 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1134 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1136 bus_dma_tag_destroy(*dtag);
1141 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1142 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1144 device_printf(dev, "cannot get address of the %s "
1145 "descriptors\n", dname);
1146 bus_dmamem_free(*dtag, *vaddr, *dmap);
1147 bus_dma_tag_destroy(*dtag);
1156 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1162 /* Unmap descriptors from DMA memory */
1163 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1164 BUS_DMASYNC_POSTWRITE);
1165 bus_dmamap_unload(dtag, dmap);
1167 /* Free descriptors memory */
1168 bus_dmamem_free(dtag, vaddr, dmap);
1170 /* Destroy descriptors tag */
1171 bus_dma_tag_destroy(dtag);
1175 tsec_free_dma(struct tsec_softc *sc)
1180 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1181 if (sc->tx_bufmap[i].map_initialized)
1182 bus_dmamap_destroy(sc->tsec_tx_mtag,
1183 sc->tx_bufmap[i].map);
1184 /* Destroy tag for TX mbufs */
1185 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1187 /* Free RX mbufs and maps */
1188 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1189 if (sc->rx_data[i].mbuf) {
1190 /* Unload buffer from DMA */
1191 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1192 BUS_DMASYNC_POSTREAD);
1193 bus_dmamap_unload(sc->tsec_rx_mtag,
1194 sc->rx_data[i].map);
1197 m_freem(sc->rx_data[i].mbuf);
1199 /* Destroy map for this buffer */
1200 if (sc->rx_data[i].map != NULL)
1201 bus_dmamap_destroy(sc->tsec_rx_mtag,
1202 sc->rx_data[i].map);
1204 /* Destroy tag for RX mbufs */
1205 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1207 /* Unload TX/RX descriptors */
1208 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1210 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1215 tsec_stop(struct tsec_softc *sc)
1220 TSEC_GLOBAL_LOCK_ASSERT(sc);
1224 /* Disable interface and watchdog timer */
1225 callout_stop(&sc->tsec_callout);
1226 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1227 sc->tsec_watchdog = 0;
1229 /* Disable all interrupts and stop DMA */
1230 tsec_intrs_ctl(sc, 0);
1231 tsec_dma_ctl(sc, 0);
1233 /* Remove pending data from TX queue */
1234 while (sc->tx_idx_tail != sc->tx_idx_head) {
1235 bus_dmamap_sync(sc->tsec_tx_mtag,
1236 sc->tx_bufmap[sc->tx_idx_tail].map,
1237 BUS_DMASYNC_POSTWRITE);
1238 bus_dmamap_unload(sc->tsec_tx_mtag,
1239 sc->tx_bufmap[sc->tx_idx_tail].map);
1240 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1241 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1242 & (TSEC_TX_NUM_DESC - 1);
1245 /* Disable RX and TX */
1246 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1247 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1248 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1253 tsec_tick(void *arg)
1255 struct tsec_softc *sc = arg;
1259 TSEC_GLOBAL_LOCK(sc);
1264 link = sc->tsec_link;
1266 mii_tick(sc->tsec_mii);
1268 if (link == 0 && sc->tsec_link == 1 &&
1269 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1270 tsec_start_locked(ifp);
1272 /* Schedule another timeout one second from now. */
1273 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1275 TSEC_GLOBAL_UNLOCK(sc);
1279 * This is the core RX routine. It replenishes mbufs in the descriptor and
1280 * sends data which have been dma'ed into host memory to upper layer.
1282 * Loops at most count times if count is > 0, or until done if count < 0.
1285 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1287 struct tsec_desc *rx_desc;
1289 struct rx_data_type *rx_data;
1295 TSEC_RECEIVE_LOCK_ASSERT(sc);
1298 rx_data = sc->rx_data;
1301 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1302 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1304 for (c = 0; ; c++) {
1305 if (count >= 0 && count-- == 0)
1308 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1309 flags = rx_desc->flags;
1311 /* Check if there is anything to receive */
1312 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1314 * Avoid generating another interrupt
1316 if (flags & TSEC_RXBD_E)
1317 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1318 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1320 * We didn't consume current descriptor and have to
1321 * return it to the queue
1323 TSEC_BACK_CUR_RX_DESC(sc);
1327 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1328 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1329 rx_desc->length = 0;
1330 rx_desc->flags = (rx_desc->flags &
1331 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1333 if (sc->frame != NULL) {
1341 /* Ok... process frame */
1342 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1343 m = rx_data[i].mbuf;
1344 m->m_len = rx_desc->length;
1346 if (sc->frame != NULL) {
1347 if ((flags & TSEC_RXBD_L) != 0)
1348 m->m_len -= m_length(sc->frame, NULL);
1350 m->m_flags &= ~M_PKTHDR;
1351 m_cat(sc->frame, m);
1358 if ((flags & TSEC_RXBD_L) != 0) {
1363 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1364 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1365 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1367 * We ran out of mbufs; didn't consume current
1368 * descriptor and have to return it to the queue.
1370 TSEC_BACK_CUR_RX_DESC(sc);
1374 /* Attach new buffer to descriptor and clear flags */
1375 rx_desc->bufptr = rx_data[i].paddr;
1376 rx_desc->length = 0;
1377 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1378 TSEC_RXBD_E | TSEC_RXBD_I;
1381 m->m_pkthdr.rcvif = ifp;
1384 m_adj(m, -ETHER_CRC_LEN);
1387 tsec_offload_process_frame(sc, m);
1389 TSEC_RECEIVE_UNLOCK(sc);
1390 (*ifp->if_input)(ifp, m);
1391 TSEC_RECEIVE_LOCK(sc);
1396 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1400 * Make sure TSEC receiver is not halted.
1402 * Various conditions can stop the TSEC receiver, but not all are
1403 * signaled and handled by error interrupt, so make sure the receiver
1404 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1405 * halted, and is harmless if already running.
1407 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1412 tsec_receive_intr(void *arg)
1414 struct tsec_softc *sc = arg;
1416 TSEC_RECEIVE_LOCK(sc);
1418 #ifdef DEVICE_POLLING
1419 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1420 TSEC_RECEIVE_UNLOCK(sc);
1425 /* Confirm the interrupt was received by driver */
1426 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1427 tsec_receive_intr_locked(sc, -1);
1429 TSEC_RECEIVE_UNLOCK(sc);
1433 tsec_transmit_intr_locked(struct tsec_softc *sc)
1438 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1442 /* Update collision statistics */
1443 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1445 /* Reset collision counters in hardware */
1446 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1447 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1448 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1449 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1450 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1452 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1453 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1455 tx_idx = sc->tx_idx_tail;
1456 while (tx_idx != sc->tx_idx_head) {
1457 struct tsec_desc *tx_desc;
1458 struct tsec_bufmap *tx_bufmap;
1460 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1461 if (tx_desc->flags & TSEC_TXBD_R) {
1465 tx_bufmap = &sc->tx_bufmap[tx_idx];
1466 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1467 if (tx_bufmap->mbuf == NULL)
1471 * This is the last buf in this packet, so unmap and free it.
1473 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1474 BUS_DMASYNC_POSTWRITE);
1475 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1476 m_freem(tx_bufmap->mbuf);
1477 tx_bufmap->mbuf = NULL;
1479 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1481 sc->tx_idx_tail = tx_idx;
1482 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1485 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1486 tsec_start_locked(ifp);
1488 if (sc->tx_idx_tail == sc->tx_idx_head)
1489 sc->tsec_watchdog = 0;
1493 tsec_transmit_intr(void *arg)
1495 struct tsec_softc *sc = arg;
1497 TSEC_TRANSMIT_LOCK(sc);
1499 #ifdef DEVICE_POLLING
1500 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1501 TSEC_TRANSMIT_UNLOCK(sc);
1505 /* Confirm the interrupt was received by driver */
1506 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1507 tsec_transmit_intr_locked(sc);
1509 TSEC_TRANSMIT_UNLOCK(sc);
1513 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1518 TSEC_GLOBAL_LOCK_ASSERT(sc);
1522 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1524 /* Clear events bits in hardware */
1525 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1526 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1527 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1528 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1530 /* Check transmitter errors */
1531 if (eflags & TSEC_IEVENT_TXE) {
1532 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1534 if (eflags & TSEC_IEVENT_LC)
1535 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1537 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1540 /* Check for discarded frame due to a lack of buffers */
1541 if (eflags & TSEC_IEVENT_BSY) {
1542 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1545 if (ifp->if_flags & IFF_DEBUG)
1546 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1549 if (eflags & TSEC_IEVENT_EBERR) {
1550 if_printf(ifp, "System bus error occurred during"
1551 "DMA transaction (flags: 0x%x)\n", eflags);
1552 tsec_init_locked(sc);
1555 if (eflags & TSEC_IEVENT_BABT)
1556 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1558 if (eflags & TSEC_IEVENT_BABR)
1559 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1563 tsec_error_intr(void *arg)
1565 struct tsec_softc *sc = arg;
1567 TSEC_GLOBAL_LOCK(sc);
1568 tsec_error_intr_locked(sc, -1);
1569 TSEC_GLOBAL_UNLOCK(sc);
1573 tsec_miibus_readreg(device_t dev, int phy, int reg)
1575 struct tsec_softc *sc;
1579 sc = device_get_softc(dev);
1582 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1583 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1584 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1586 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1587 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1591 device_printf(dev, "Timeout while reading from PHY!\n");
1597 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1599 struct tsec_softc *sc;
1602 sc = device_get_softc(dev);
1605 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1607 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1611 device_printf(dev, "Timeout while writing to PHY!\n");
1617 tsec_miibus_statchg(device_t dev)
1619 struct tsec_softc *sc;
1620 struct mii_data *mii;
1621 uint32_t ecntrl, id, tmp;
1624 sc = device_get_softc(dev);
1626 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1628 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1630 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1631 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1633 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1635 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1638 tmp |= TSEC_MACCFG2_GMII;
1639 sc->tsec_link = link;
1643 tmp |= TSEC_MACCFG2_MII;
1644 sc->tsec_link = link;
1648 device_printf(dev, "No speed selected but link "
1654 device_printf(dev, "Unknown speed (%d), link %s!\n",
1655 IFM_SUBTYPE(mii->mii_media_active),
1656 ((link) ? "up" : "down"));
1659 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1661 /* XXX kludge - use circumstantial evidence for reduced mode. */
1662 id = TSEC_READ(sc, TSEC_REG_ID2);
1664 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1665 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1666 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1671 tsec_add_sysctls(struct tsec_softc *sc)
1673 struct sysctl_ctx_list *ctx;
1674 struct sysctl_oid_list *children;
1675 struct sysctl_oid *tree;
1677 ctx = device_get_sysctl_ctx(sc->dev);
1678 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1679 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1680 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing");
1681 children = SYSCTL_CHILDREN(tree);
1683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1684 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1685 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)");
1686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1687 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1688 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)");
1690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1691 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1692 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)");
1693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1694 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1695 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)");
1699 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1700 * interrupt is raised either upon:
1702 * - threshold-defined period of time elapsed, or
1703 * - threshold-defined number of frames is received/transmitted,
1704 * whichever occurs first.
1706 * The following sysctls regulate IC behaviour (for TX/RX separately):
1708 * dev.tsec.<unit>.int_coal.rx_time
1709 * dev.tsec.<unit>.int_coal.rx_count
1710 * dev.tsec.<unit>.int_coal.tx_time
1711 * dev.tsec.<unit>.int_coal.tx_count
1715 * - 0 for either time or count disables IC on the given TX/RX path
1717 * - count: 1-255 (expresses frame count number; note that value of 1 is
1718 * effectively IC off)
1720 * - time: 1-65535 (value corresponds to a real time period and is
1721 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1722 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1723 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1724 * TSEC reference manual.
1727 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1731 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1733 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1735 error = sysctl_handle_int(oidp, &time, 0, req);
1743 if (arg2 == TSEC_IC_RX) {
1744 sc->rx_ic_time = time;
1747 sc->tx_ic_time = time;
1756 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1760 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1762 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1764 error = sysctl_handle_int(oidp, &count, 0, req);
1772 if (arg2 == TSEC_IC_RX) {
1773 sc->rx_ic_count = count;
1776 sc->tx_ic_count = count;
1785 tsec_set_rxic(struct tsec_softc *sc)
1789 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1793 rxic_val = 0x80000000;
1794 rxic_val |= (sc->rx_ic_count << 21);
1795 rxic_val |= sc->rx_ic_time;
1798 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1802 tsec_set_txic(struct tsec_softc *sc)
1806 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1810 txic_val = 0x80000000;
1811 txic_val |= (sc->tx_ic_count << 21);
1812 txic_val |= sc->tx_ic_time;
1815 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1819 tsec_offload_setup(struct tsec_softc *sc)
1821 struct ifnet *ifp = sc->tsec_ifp;
1824 TSEC_GLOBAL_LOCK_ASSERT(sc);
1826 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1827 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1829 if (ifp->if_capenable & IFCAP_TXCSUM)
1830 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1832 ifp->if_hwassist = 0;
1834 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1836 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1837 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1838 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1840 if (ifp->if_capenable & IFCAP_RXCSUM)
1841 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1842 TSEC_RCTRL_PRSDEP_PARSE_L234;
1844 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1848 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1850 struct tsec_rx_fcb rx_fcb;
1852 int protocol, flags;
1854 TSEC_RECEIVE_LOCK_ASSERT(sc);
1856 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1857 flags = rx_fcb.flags;
1858 protocol = rx_fcb.protocol;
1860 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1861 csum_flags |= CSUM_IP_CHECKED;
1863 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1864 csum_flags |= CSUM_IP_VALID;
1867 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1868 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1869 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1870 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1871 m->m_pkthdr.csum_data = 0xFFFF;
1874 m->m_pkthdr.csum_flags = csum_flags;
1876 if (flags & TSEC_RX_FCB_VLAN) {
1877 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1878 m->m_flags |= M_VLANTAG;
1881 m_adj(m, sizeof(struct tsec_rx_fcb));
1885 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1887 uint32_t h, *hashtable = arg;
1889 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF;
1890 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1896 tsec_setup_multicast(struct tsec_softc *sc)
1898 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1899 struct ifnet *ifp = sc->tsec_ifp;
1902 TSEC_GLOBAL_LOCK_ASSERT(sc);
1904 if (ifp->if_flags & IFF_ALLMULTI) {
1905 for (i = 0; i < 8; i++)
1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1911 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable);
1913 for (i = 0; i < 8; i++)
1914 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1918 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1921 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1923 TSEC_GLOBAL_LOCK_ASSERT(sc);
1925 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1926 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);