2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #ifdef HAVE_KERNEL_OPTION_HEADERS
34 #include "opt_device_polling.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
62 #include <machine/bus.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/tsec/if_tsec.h>
68 #include <dev/tsec/if_tsecreg.h>
70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
73 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74 static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
76 static void tsec_free_dma(struct tsec_softc *sc);
77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78 static int tsec_ifmedia_upd(struct ifnet *ifp);
79 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85 static void tsec_init(void *xsc);
86 static void tsec_init_locked(struct tsec_softc *sc);
87 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88 static void tsec_reset_mac(struct tsec_softc *sc);
89 static void tsec_setfilter(struct tsec_softc *sc);
90 static void tsec_set_mac_address(struct tsec_softc *sc);
91 static void tsec_start(struct ifnet *ifp);
92 static void tsec_start_locked(struct ifnet *ifp);
93 static void tsec_stop(struct tsec_softc *sc);
94 static void tsec_tick(void *arg);
95 static void tsec_watchdog(struct tsec_softc *sc);
96 static void tsec_add_sysctls(struct tsec_softc *sc);
97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99 static void tsec_set_rxic(struct tsec_softc *sc);
100 static void tsec_set_txic(struct tsec_softc *sc);
101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_offload_setup(struct tsec_softc *sc);
105 static void tsec_offload_process_frame(struct tsec_softc *sc,
107 static void tsec_setup_multicast(struct tsec_softc *sc);
108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
110 devclass_t tsec_devclass;
111 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112 MODULE_DEPEND(tsec, ether, 1, 1, 1);
113 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115 struct mtx tsec_phy_mtx;
118 tsec_attach(struct tsec_softc *sc)
120 uint8_t hwaddr[ETHER_ADDR_LEN];
122 bus_dmamap_t *map_ptr;
123 bus_dmamap_t **map_pptr;
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
134 /* Stop DMA engine if enabled by firmware */
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
150 tsec_add_sysctls(sc);
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_NUM_DESC - 1, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
183 device_printf(sc->dev, "failed to allocate busdma tag "
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
201 device_printf(sc->dev, "failed to allocate busdma tag "
207 /* Create TX busdma maps */
208 map_ptr = sc->tx_map_data;
209 map_pptr = sc->tx_map_unused_data;
211 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
212 map_pptr[i] = &map_ptr[i];
213 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
215 device_printf(sc->dev, "failed to init TX ring\n");
221 /* Create RX busdma maps and zero mbuf handlers */
222 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
223 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
224 &sc->rx_data[i].map);
226 device_printf(sc->dev, "failed to init RX ring\n");
230 sc->rx_data[i].mbuf = NULL;
233 /* Create mbufs for RX buffers */
234 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
235 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
236 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
238 device_printf(sc->dev, "can't load rx DMA map %d, "
239 "error = %d\n", i, error);
245 /* Create network interface for upper layers */
246 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
248 device_printf(sc->dev, "if_alloc() failed\n");
254 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
255 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
256 ifp->if_init = tsec_init;
257 ifp->if_start = tsec_start;
258 ifp->if_ioctl = tsec_ioctl;
260 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
261 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
262 IFQ_SET_READY(&ifp->if_snd);
264 ifp->if_capabilities = IFCAP_VLAN_MTU;
266 ifp->if_capabilities |= IFCAP_HWCSUM;
268 ifp->if_capenable = ifp->if_capabilities;
270 #ifdef DEVICE_POLLING
271 /* Advertise that polling is supported */
272 ifp->if_capabilities |= IFCAP_POLLING;
276 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
277 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
280 device_printf(sc->dev, "attaching PHYs failed\n");
286 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
288 /* Set MAC address */
289 tsec_get_hwaddr(sc, hwaddr);
290 ether_ifattach(ifp, hwaddr);
296 tsec_detach(struct tsec_softc *sc)
299 if (sc->tsec_ifp != NULL) {
300 #ifdef DEVICE_POLLING
301 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
302 ether_poll_deregister(sc->tsec_ifp);
305 /* Stop TSEC controller and free TX queue */
307 tsec_shutdown(sc->dev);
309 /* Detach network interface */
310 ether_ifdetach(sc->tsec_ifp);
311 if_free(sc->tsec_ifp);
315 /* Free DMA resources */
322 tsec_shutdown(device_t dev)
324 struct tsec_softc *sc;
326 sc = device_get_softc(dev);
328 TSEC_GLOBAL_LOCK(sc);
330 TSEC_GLOBAL_UNLOCK(sc);
335 tsec_suspend(device_t dev)
338 /* TODO not implemented! */
343 tsec_resume(device_t dev)
346 /* TODO not implemented! */
353 struct tsec_softc *sc = xsc;
355 TSEC_GLOBAL_LOCK(sc);
356 tsec_init_locked(sc);
357 TSEC_GLOBAL_UNLOCK(sc);
361 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
366 * The status indicators are not set immediatly after a command.
367 * Discard the first value.
369 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
371 timeout = TSEC_READ_RETRY;
372 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
373 DELAY(TSEC_READ_DELAY);
375 return (timeout == 0);
380 tsec_init_locked(struct tsec_softc *sc)
382 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
383 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
384 struct ifnet *ifp = sc->tsec_ifp;
388 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
391 TSEC_GLOBAL_LOCK_ASSERT(sc);
395 * These steps are according to the MPC8555E PowerQUICCIII RM:
396 * 14.7 Initialization/Application Information
399 /* Step 1: soft reset MAC */
402 /* Step 2: Initialize MACCFG2 */
403 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
404 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
405 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
406 TSEC_MACCFG2_GMII | /* I/F Mode bit */
407 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
410 /* Step 3: Initialize ECNTRL
411 * While the documentation states that R100M is ignored if RPM is
412 * not set, it does seem to be needed to get the orange boxes to
413 * work (which have a Marvell 88E1111 PHY). Go figure.
417 * XXX kludge - use circumstancial evidence to program ECNTRL
418 * correctly. Ideally we need some board information to guide
421 i = TSEC_READ(sc, TSEC_REG_ID2);
423 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
424 : TSEC_ECNTRL_R100M; /* Orange + CDS */
425 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
427 /* Step 4: Initialize MAC station address */
428 tsec_set_mac_address(sc);
431 * Step 5: Assign a Physical address to the TBI so as to not conflict
432 * with the external PHY physical address
434 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
438 /* Step 6: Reset the management interface */
439 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
441 /* Step 7: Setup the MII Mgmt clock speed */
442 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
444 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
445 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
449 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
453 /* Step 9: Setup the MII Mgmt */
454 mii_mediachg(sc->tsec_mii);
456 /* Step 10: Clear IEVENT register */
457 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
459 /* Step 11: Enable interrupts */
460 #ifdef DEVICE_POLLING
462 * ...only if polling is not turned on. Disable interrupts explicitly
463 * if polling is enabled.
465 if (ifp->if_capenable & IFCAP_POLLING )
466 tsec_intrs_ctl(sc, 0);
468 #endif /* DEVICE_POLLING */
469 tsec_intrs_ctl(sc, 1);
471 /* Step 12: Initialize IADDRn */
472 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
473 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
474 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
475 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
476 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
477 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
478 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
479 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
481 /* Step 13: Initialize GADDRn */
482 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
483 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
484 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
485 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
486 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
487 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
488 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
489 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
491 /* Step 14: Initialize RCTRL */
492 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
494 /* Step 15: Initialize DMACTRL */
497 /* Step 16: Initialize FIFO_PAUSE_CTRL */
498 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
501 * Step 17: Initialize transmit/receive descriptor rings.
502 * Initialize TBASE and RBASE.
504 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
505 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
507 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
508 tx_desc[i].bufptr = 0;
509 tx_desc[i].length = 0;
510 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
513 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
514 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
516 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
517 rx_desc[i].bufptr = sc->rx_data[i].paddr;
518 rx_desc[i].length = 0;
519 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
520 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
522 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
525 /* Step 18: Initialize the maximum receive buffer length */
526 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
528 /* Step 19: Configure ethernet frame sizes */
529 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
530 tsec_set_mtu(sc, ifp->if_mtu);
532 /* Step 20: Enable Rx and RxBD sdata snooping */
533 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
534 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
536 /* Step 21: Reset collision counters in hardware */
537 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
538 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
539 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
540 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
541 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
543 /* Step 22: Mask all CAM interrupts */
544 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
545 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
547 /* Step 23: Enable Rx and Tx */
548 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
549 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
550 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
552 /* Step 24: Reset TSEC counters for Tx and Rx rings */
553 TSEC_TX_RX_COUNTERS_INIT(sc);
555 /* Step 25: Setup TCP/IP Off-Load engine */
557 tsec_offload_setup(sc);
559 /* Step 26: Setup multicast filters */
560 tsec_setup_multicast(sc);
562 /* Step 27: Activate network interface */
563 ifp->if_drv_flags |= IFF_DRV_RUNNING;
564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
565 sc->tsec_if_flags = ifp->if_flags;
566 sc->tsec_watchdog = 0;
568 /* Schedule watchdog timeout */
569 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
573 tsec_set_mac_address(struct tsec_softc *sc)
575 uint32_t macbuf[2] = { 0, 0 };
576 char *macbufp, *curmac;
579 TSEC_GLOBAL_LOCK_ASSERT(sc);
581 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
582 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
585 macbufp = (char *)macbuf;
586 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
588 /* Correct order of MAC address bytes */
589 for (i = 1; i <= ETHER_ADDR_LEN; i++)
590 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
592 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
593 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
594 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
598 * DMA control function, if argument state is:
599 * 0 - DMA engine will be disabled
600 * 1 - DMA engine will be enabled
603 tsec_dma_ctl(struct tsec_softc *sc, int state)
606 uint32_t dma_flags, timeout;
610 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
614 /* Temporarily clear stop graceful stop bits. */
615 tsec_dma_ctl(sc, 1000);
618 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
622 /* Set write with response (WWR), wait (WOP) and snoop bits */
623 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
624 DMACTRL_WWR | DMACTRL_WOP);
626 /* Clear graceful stop bits */
627 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
630 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
634 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
638 /* Wait for DMA stop */
639 timeout = TSEC_READ_RETRY;
640 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
641 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
642 DELAY(TSEC_READ_DELAY);
645 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
648 /* Restart transmission function */
649 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
654 * Interrupts control function, if argument state is:
655 * 0 - all TSEC interrupts will be masked
656 * 1 - all TSEC interrupts will be unmasked
659 tsec_intrs_ctl(struct tsec_softc *sc, int state)
667 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
670 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
671 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
672 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
673 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
676 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
682 tsec_reset_mac(struct tsec_softc *sc)
684 uint32_t maccfg1_flags;
686 /* Set soft reset bit */
687 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
688 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
689 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
691 /* Clear soft reset bit */
692 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
693 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
694 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
698 tsec_watchdog(struct tsec_softc *sc)
702 TSEC_GLOBAL_LOCK_ASSERT(sc);
704 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
708 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
709 if_printf(ifp, "watchdog timeout\n");
712 tsec_init_locked(sc);
716 tsec_start(struct ifnet *ifp)
718 struct tsec_softc *sc = ifp->if_softc;
720 TSEC_TRANSMIT_LOCK(sc);
721 tsec_start_locked(ifp);
722 TSEC_TRANSMIT_UNLOCK(sc);
726 tsec_start_locked(struct ifnet *ifp)
728 struct tsec_softc *sc;
729 struct mbuf *m0, *mtmp;
730 struct tsec_tx_fcb *tx_fcb;
731 unsigned int queued = 0;
732 int csum_flags, fcb_inserted = 0;
736 TSEC_TRANSMIT_LOCK_ASSERT(sc);
738 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
742 if (sc->tsec_link == 0)
745 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
746 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
748 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
749 /* Get packet from the queue */
750 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
754 /* Insert TCP/IP Off-load frame control block */
755 csum_flags = m0->m_pkthdr.csum_flags;
758 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
762 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
764 tx_fcb->l3_offset = ETHER_HDR_LEN;
765 tx_fcb->l4_offset = sizeof(struct ip);
767 if (csum_flags & CSUM_IP)
768 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
771 if (csum_flags & CSUM_TCP)
772 tx_fcb->flags |= TSEC_TX_FCB_TCP |
773 TSEC_TX_FCB_CSUM_TCP_UDP;
775 if (csum_flags & CSUM_UDP)
776 tx_fcb->flags |= TSEC_TX_FCB_UDP |
777 TSEC_TX_FCB_CSUM_TCP_UDP;
782 mtmp = m_defrag(m0, M_NOWAIT);
786 if (tsec_encap(sc, m0, fcb_inserted)) {
787 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
788 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
794 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
798 /* Enable transmitter and watchdog timer */
799 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
800 sc->tsec_watchdog = 5;
805 tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
807 struct tsec_desc *tx_desc = NULL;
809 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
811 int csum_flag = 0, error, seg, nsegs;
813 TSEC_TRANSMIT_LOCK_ASSERT(sc);
817 if (TSEC_FREE_TX_DESC(sc) == 0) {
818 /* No free descriptors */
822 /* Fetch unused map */
823 mapp = TSEC_ALLOC_TX_MAP(sc);
825 /* Create mapping in DMA memory */
826 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
827 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
828 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
829 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
830 TSEC_FREE_TX_MAP(sc, mapp);
831 return ((error != 0) ? error : -1);
833 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
835 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
836 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
839 csum_flag = TSEC_TXBD_TOE;
841 /* Everything is ok, now we can send buffers */
842 for (seg = 0; seg < nsegs; seg++) {
843 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
845 tx_desc->length = segs[seg].ds_len;
846 tx_desc->bufptr = segs[seg].ds_addr;
853 * - transmit the CRC sequence after the last data byte
854 * - interrupt after the last buffer
857 (tx_desc->flags & TSEC_TXBD_W) |
858 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
859 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
862 /* Save mbuf and DMA mapping for release at later stage */
863 TSEC_PUT_TX_MBUF(sc, m0);
864 TSEC_PUT_TX_MAP(sc, mapp);
870 tsec_setfilter(struct tsec_softc *sc)
876 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
878 /* Promiscuous mode */
879 if (ifp->if_flags & IFF_PROMISC)
880 flags |= TSEC_RCTRL_PROM;
882 flags &= ~TSEC_RCTRL_PROM;
884 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
887 #ifdef DEVICE_POLLING
888 static poll_handler_t tsec_poll;
891 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
894 struct tsec_softc *sc = ifp->if_softc;
899 TSEC_GLOBAL_LOCK(sc);
900 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
901 TSEC_GLOBAL_UNLOCK(sc);
905 if (cmd == POLL_AND_CHECK_STATUS) {
906 tsec_error_intr_locked(sc, count);
908 /* Clear all events reported */
909 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
910 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
913 tsec_transmit_intr_locked(sc);
915 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
917 rx_npkts = tsec_receive_intr_locked(sc, count);
919 TSEC_RECEIVE_UNLOCK(sc);
923 #endif /* DEVICE_POLLING */
926 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
928 struct tsec_softc *sc = ifp->if_softc;
929 struct ifreq *ifr = (struct ifreq *)data;
934 TSEC_GLOBAL_LOCK(sc);
935 if (tsec_set_mtu(sc, ifr->ifr_mtu))
936 ifp->if_mtu = ifr->ifr_mtu;
939 TSEC_GLOBAL_UNLOCK(sc);
942 TSEC_GLOBAL_LOCK(sc);
943 if (ifp->if_flags & IFF_UP) {
944 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
945 if ((sc->tsec_if_flags ^ ifp->if_flags) &
949 if ((sc->tsec_if_flags ^ ifp->if_flags) &
951 tsec_setup_multicast(sc);
953 tsec_init_locked(sc);
954 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
957 sc->tsec_if_flags = ifp->if_flags;
958 TSEC_GLOBAL_UNLOCK(sc);
962 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
963 TSEC_GLOBAL_LOCK(sc);
964 tsec_setup_multicast(sc);
965 TSEC_GLOBAL_UNLOCK(sc);
969 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
973 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
974 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
975 TSEC_GLOBAL_LOCK(sc);
976 ifp->if_capenable &= ~IFCAP_HWCSUM;
977 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
978 tsec_offload_setup(sc);
979 TSEC_GLOBAL_UNLOCK(sc);
981 #ifdef DEVICE_POLLING
982 if (mask & IFCAP_POLLING) {
983 if (ifr->ifr_reqcap & IFCAP_POLLING) {
984 error = ether_poll_register(tsec_poll, ifp);
988 TSEC_GLOBAL_LOCK(sc);
989 /* Disable interrupts */
990 tsec_intrs_ctl(sc, 0);
991 ifp->if_capenable |= IFCAP_POLLING;
992 TSEC_GLOBAL_UNLOCK(sc);
994 error = ether_poll_deregister(ifp);
995 TSEC_GLOBAL_LOCK(sc);
996 /* Enable interrupts */
997 tsec_intrs_ctl(sc, 1);
998 ifp->if_capenable &= ~IFCAP_POLLING;
999 TSEC_GLOBAL_UNLOCK(sc);
1006 error = ether_ioctl(ifp, command, data);
1009 /* Flush buffers if not empty */
1010 if (ifp->if_flags & IFF_UP)
1016 tsec_ifmedia_upd(struct ifnet *ifp)
1018 struct tsec_softc *sc = ifp->if_softc;
1019 struct mii_data *mii;
1021 TSEC_TRANSMIT_LOCK(sc);
1026 TSEC_TRANSMIT_UNLOCK(sc);
1031 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1033 struct tsec_softc *sc = ifp->if_softc;
1034 struct mii_data *mii;
1036 TSEC_TRANSMIT_LOCK(sc);
1041 ifmr->ifm_active = mii->mii_media_active;
1042 ifmr->ifm_status = mii->mii_media_status;
1044 TSEC_TRANSMIT_UNLOCK(sc);
1048 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1051 struct mbuf *new_mbuf;
1052 bus_dma_segment_t seg[1];
1055 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1057 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1058 if (new_mbuf == NULL)
1060 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1063 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1064 bus_dmamap_unload(tag, map);
1067 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1069 KASSERT(nsegs == 1, ("Too many segments returned!"));
1070 if (nsegs != 1 || error)
1071 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1075 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1083 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1084 ("Wrong alignment of RX buffer!"));
1086 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1088 (*mbufp) = new_mbuf;
1089 (*paddr) = seg->ds_addr;
1094 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1098 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1100 *paddr = segs->ds_addr;
1104 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1105 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1109 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1110 error = bus_dma_tag_create(NULL, /* parent */
1111 PAGE_SIZE, 0, /* alignment, boundary */
1112 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1113 BUS_SPACE_MAXADDR, /* highaddr */
1114 NULL, NULL, /* filtfunc, filtfuncarg */
1115 dsize, 1, /* maxsize, nsegments */
1116 dsize, 0, /* maxsegsz, flags */
1117 NULL, NULL, /* lockfunc, lockfuncarg */
1121 device_printf(dev, "failed to allocate busdma %s tag\n",
1127 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1130 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1132 bus_dma_tag_destroy(*dtag);
1137 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1138 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1140 device_printf(dev, "cannot get address of the %s "
1141 "descriptors\n", dname);
1142 bus_dmamem_free(*dtag, *vaddr, *dmap);
1143 bus_dma_tag_destroy(*dtag);
1152 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1158 /* Unmap descriptors from DMA memory */
1159 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1160 BUS_DMASYNC_POSTWRITE);
1161 bus_dmamap_unload(dtag, dmap);
1163 /* Free descriptors memory */
1164 bus_dmamem_free(dtag, vaddr, dmap);
1166 /* Destroy descriptors tag */
1167 bus_dma_tag_destroy(dtag);
1171 tsec_free_dma(struct tsec_softc *sc)
1176 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1177 if (sc->tx_map_data[i] != NULL)
1178 bus_dmamap_destroy(sc->tsec_tx_mtag,
1179 sc->tx_map_data[i]);
1180 /* Destroy tag for TX mbufs */
1181 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1183 /* Free RX mbufs and maps */
1184 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1185 if (sc->rx_data[i].mbuf) {
1186 /* Unload buffer from DMA */
1187 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1188 BUS_DMASYNC_POSTREAD);
1189 bus_dmamap_unload(sc->tsec_rx_mtag,
1190 sc->rx_data[i].map);
1193 m_freem(sc->rx_data[i].mbuf);
1195 /* Destroy map for this buffer */
1196 if (sc->rx_data[i].map != NULL)
1197 bus_dmamap_destroy(sc->tsec_rx_mtag,
1198 sc->rx_data[i].map);
1200 /* Destroy tag for RX mbufs */
1201 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1203 /* Unload TX/RX descriptors */
1204 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1206 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1211 tsec_stop(struct tsec_softc *sc)
1218 TSEC_GLOBAL_LOCK_ASSERT(sc);
1222 /* Disable interface and watchdog timer */
1223 callout_stop(&sc->tsec_callout);
1224 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1225 sc->tsec_watchdog = 0;
1227 /* Disable all interrupts and stop DMA */
1228 tsec_intrs_ctl(sc, 0);
1229 tsec_dma_ctl(sc, 0);
1231 /* Remove pending data from TX queue */
1232 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1233 m0 = TSEC_GET_TX_MBUF(sc);
1234 mapp = TSEC_GET_TX_MAP(sc);
1236 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1237 BUS_DMASYNC_POSTWRITE);
1238 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1240 TSEC_FREE_TX_MAP(sc, mapp);
1244 /* Disable RX and TX */
1245 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1246 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1247 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1252 tsec_tick(void *arg)
1254 struct tsec_softc *sc = arg;
1258 TSEC_GLOBAL_LOCK(sc);
1263 link = sc->tsec_link;
1265 mii_tick(sc->tsec_mii);
1267 if (link == 0 && sc->tsec_link == 1 &&
1268 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1269 tsec_start_locked(ifp);
1271 /* Schedule another timeout one second from now. */
1272 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1274 TSEC_GLOBAL_UNLOCK(sc);
1278 * This is the core RX routine. It replenishes mbufs in the descriptor and
1279 * sends data which have been dma'ed into host memory to upper layer.
1281 * Loops at most count times if count is > 0, or until done if count < 0.
1284 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1286 struct tsec_desc *rx_desc;
1288 struct rx_data_type *rx_data;
1294 TSEC_RECEIVE_LOCK_ASSERT(sc);
1297 rx_data = sc->rx_data;
1300 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1303 for (c = 0; ; c++) {
1304 if (count >= 0 && count-- == 0)
1307 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1308 flags = rx_desc->flags;
1310 /* Check if there is anything to receive */
1311 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1313 * Avoid generating another interrupt
1315 if (flags & TSEC_RXBD_E)
1316 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1317 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1319 * We didn't consume current descriptor and have to
1320 * return it to the queue
1322 TSEC_BACK_CUR_RX_DESC(sc);
1326 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1327 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1329 rx_desc->length = 0;
1330 rx_desc->flags = (rx_desc->flags &
1331 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1333 if (sc->frame != NULL) {
1341 /* Ok... process frame */
1342 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1343 m = rx_data[i].mbuf;
1344 m->m_len = rx_desc->length;
1346 if (sc->frame != NULL) {
1347 if ((flags & TSEC_RXBD_L) != 0)
1348 m->m_len -= m_length(sc->frame, NULL);
1350 m->m_flags &= ~M_PKTHDR;
1351 m_cat(sc->frame, m);
1358 if ((flags & TSEC_RXBD_L) != 0) {
1363 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1364 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1365 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1367 * We ran out of mbufs; didn't consume current
1368 * descriptor and have to return it to the queue.
1370 TSEC_BACK_CUR_RX_DESC(sc);
1374 /* Attach new buffer to descriptor and clear flags */
1375 rx_desc->bufptr = rx_data[i].paddr;
1376 rx_desc->length = 0;
1377 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1378 TSEC_RXBD_E | TSEC_RXBD_I;
1381 m->m_pkthdr.rcvif = ifp;
1384 m_adj(m, -ETHER_CRC_LEN);
1387 tsec_offload_process_frame(sc, m);
1389 TSEC_RECEIVE_UNLOCK(sc);
1390 (*ifp->if_input)(ifp, m);
1391 TSEC_RECEIVE_LOCK(sc);
1396 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1400 * Make sure TSEC receiver is not halted.
1402 * Various conditions can stop the TSEC receiver, but not all are
1403 * signaled and handled by error interrupt, so make sure the receiver
1404 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1405 * halted, and is harmless if already running.
1407 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1412 tsec_receive_intr(void *arg)
1414 struct tsec_softc *sc = arg;
1416 TSEC_RECEIVE_LOCK(sc);
1418 #ifdef DEVICE_POLLING
1419 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1420 TSEC_RECEIVE_UNLOCK(sc);
1425 /* Confirm the interrupt was received by driver */
1426 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1427 tsec_receive_intr_locked(sc, -1);
1429 TSEC_RECEIVE_UNLOCK(sc);
1433 tsec_transmit_intr_locked(struct tsec_softc *sc)
1435 struct tsec_desc *tx_desc;
1441 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1445 /* Update collision statistics */
1446 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1448 /* Reset collision counters in hardware */
1449 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1450 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1451 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1452 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1453 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1455 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1456 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1458 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1459 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1460 if (tx_desc->flags & TSEC_TXBD_R) {
1461 TSEC_BACK_DIRTY_TX_DESC(sc);
1465 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1469 * This is the last buf in this packet, so unmap and free it.
1471 m0 = TSEC_GET_TX_MBUF(sc);
1472 mapp = TSEC_GET_TX_MAP(sc);
1474 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1475 BUS_DMASYNC_POSTWRITE);
1476 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1478 TSEC_FREE_TX_MAP(sc, mapp);
1481 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1484 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1488 /* Now send anything that was pending */
1489 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1490 tsec_start_locked(ifp);
1492 /* Stop wathdog if all sent */
1493 if (TSEC_EMPTYQ_TX_MBUF(sc))
1494 sc->tsec_watchdog = 0;
1499 tsec_transmit_intr(void *arg)
1501 struct tsec_softc *sc = arg;
1503 TSEC_TRANSMIT_LOCK(sc);
1505 #ifdef DEVICE_POLLING
1506 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1507 TSEC_TRANSMIT_UNLOCK(sc);
1511 /* Confirm the interrupt was received by driver */
1512 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1513 tsec_transmit_intr_locked(sc);
1515 TSEC_TRANSMIT_UNLOCK(sc);
1519 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1524 TSEC_GLOBAL_LOCK_ASSERT(sc);
1528 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1530 /* Clear events bits in hardware */
1531 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1532 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1533 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1534 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1536 /* Check transmitter errors */
1537 if (eflags & TSEC_IEVENT_TXE) {
1538 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1540 if (eflags & TSEC_IEVENT_LC)
1541 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1543 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1546 /* Check receiver errors */
1547 if (eflags & TSEC_IEVENT_BSY) {
1548 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1549 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1551 /* Get data from RX buffers */
1552 tsec_receive_intr_locked(sc, count);
1555 if (ifp->if_flags & IFF_DEBUG)
1556 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1559 if (eflags & TSEC_IEVENT_EBERR) {
1560 if_printf(ifp, "System bus error occurred during"
1561 "DMA transaction (flags: 0x%x)\n", eflags);
1562 tsec_init_locked(sc);
1565 if (eflags & TSEC_IEVENT_BABT)
1566 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1568 if (eflags & TSEC_IEVENT_BABR)
1569 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1573 tsec_error_intr(void *arg)
1575 struct tsec_softc *sc = arg;
1577 TSEC_GLOBAL_LOCK(sc);
1578 tsec_error_intr_locked(sc, -1);
1579 TSEC_GLOBAL_UNLOCK(sc);
1583 tsec_miibus_readreg(device_t dev, int phy, int reg)
1585 struct tsec_softc *sc;
1589 sc = device_get_softc(dev);
1592 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1593 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1594 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1596 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1597 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1601 device_printf(dev, "Timeout while reading from PHY!\n");
1607 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1609 struct tsec_softc *sc;
1612 sc = device_get_softc(dev);
1615 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1616 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1617 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1621 device_printf(dev, "Timeout while writing to PHY!\n");
1627 tsec_miibus_statchg(device_t dev)
1629 struct tsec_softc *sc;
1630 struct mii_data *mii;
1631 uint32_t ecntrl, id, tmp;
1634 sc = device_get_softc(dev);
1636 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1638 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1640 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1641 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1643 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1645 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1648 tmp |= TSEC_MACCFG2_GMII;
1649 sc->tsec_link = link;
1653 tmp |= TSEC_MACCFG2_MII;
1654 sc->tsec_link = link;
1658 device_printf(dev, "No speed selected but link "
1664 device_printf(dev, "Unknown speed (%d), link %s!\n",
1665 IFM_SUBTYPE(mii->mii_media_active),
1666 ((link) ? "up" : "down"));
1669 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1671 /* XXX kludge - use circumstantial evidence for reduced mode. */
1672 id = TSEC_READ(sc, TSEC_REG_ID2);
1674 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1675 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1676 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1681 tsec_add_sysctls(struct tsec_softc *sc)
1683 struct sysctl_ctx_list *ctx;
1684 struct sysctl_oid_list *children;
1685 struct sysctl_oid *tree;
1687 ctx = device_get_sysctl_ctx(sc->dev);
1688 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1689 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1690 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1691 children = SYSCTL_CHILDREN(tree);
1693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1694 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1695 "I", "IC RX time threshold (0-65535)");
1696 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1697 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1698 "I", "IC RX frame count threshold (0-255)");
1700 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1701 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1702 "I", "IC TX time threshold (0-65535)");
1703 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1704 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1705 "I", "IC TX frame count threshold (0-255)");
1709 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1710 * interrupt is raised either upon:
1712 * - threshold-defined period of time elapsed, or
1713 * - threshold-defined number of frames is received/transmitted,
1714 * whichever occurs first.
1716 * The following sysctls regulate IC behaviour (for TX/RX separately):
1718 * dev.tsec.<unit>.int_coal.rx_time
1719 * dev.tsec.<unit>.int_coal.rx_count
1720 * dev.tsec.<unit>.int_coal.tx_time
1721 * dev.tsec.<unit>.int_coal.tx_count
1725 * - 0 for either time or count disables IC on the given TX/RX path
1727 * - count: 1-255 (expresses frame count number; note that value of 1 is
1728 * effectively IC off)
1730 * - time: 1-65535 (value corresponds to a real time period and is
1731 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1732 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1733 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1734 * TSEC reference manual.
1737 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1741 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1743 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1745 error = sysctl_handle_int(oidp, &time, 0, req);
1753 if (arg2 == TSEC_IC_RX) {
1754 sc->rx_ic_time = time;
1757 sc->tx_ic_time = time;
1766 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1770 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1772 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1774 error = sysctl_handle_int(oidp, &count, 0, req);
1782 if (arg2 == TSEC_IC_RX) {
1783 sc->rx_ic_count = count;
1786 sc->tx_ic_count = count;
1795 tsec_set_rxic(struct tsec_softc *sc)
1799 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1803 rxic_val = 0x80000000;
1804 rxic_val |= (sc->rx_ic_count << 21);
1805 rxic_val |= sc->rx_ic_time;
1808 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1812 tsec_set_txic(struct tsec_softc *sc)
1816 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1820 txic_val = 0x80000000;
1821 txic_val |= (sc->tx_ic_count << 21);
1822 txic_val |= sc->tx_ic_time;
1825 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1829 tsec_offload_setup(struct tsec_softc *sc)
1831 struct ifnet *ifp = sc->tsec_ifp;
1834 TSEC_GLOBAL_LOCK_ASSERT(sc);
1836 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1837 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1839 if (ifp->if_capenable & IFCAP_TXCSUM)
1840 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1842 ifp->if_hwassist = 0;
1844 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1846 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1847 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1848 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1850 if (ifp->if_capenable & IFCAP_RXCSUM)
1851 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1852 TSEC_RCTRL_PRSDEP_PARSE_L234;
1854 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1859 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1861 struct tsec_rx_fcb rx_fcb;
1863 int protocol, flags;
1865 TSEC_RECEIVE_LOCK_ASSERT(sc);
1867 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1868 flags = rx_fcb.flags;
1869 protocol = rx_fcb.protocol;
1871 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1872 csum_flags |= CSUM_IP_CHECKED;
1874 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1875 csum_flags |= CSUM_IP_VALID;
1878 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1879 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1880 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1882 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1883 m->m_pkthdr.csum_data = 0xFFFF;
1886 m->m_pkthdr.csum_flags = csum_flags;
1888 if (flags & TSEC_RX_FCB_VLAN) {
1889 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1890 m->m_flags |= M_VLANTAG;
1893 m_adj(m, sizeof(struct tsec_rx_fcb));
1897 tsec_setup_multicast(struct tsec_softc *sc)
1899 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1900 struct ifnet *ifp = sc->tsec_ifp;
1901 struct ifmultiaddr *ifma;
1905 TSEC_GLOBAL_LOCK_ASSERT(sc);
1907 if (ifp->if_flags & IFF_ALLMULTI) {
1908 for (i = 0; i < 8; i++)
1909 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1914 if_maddr_rlock(ifp);
1915 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1917 if (ifma->ifma_addr->sa_family != AF_LINK)
1920 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1921 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1923 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1925 if_maddr_runlock(ifp);
1927 for (i = 0; i < 8; i++)
1928 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1932 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1935 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1937 TSEC_GLOBAL_LOCK_ASSERT(sc);
1939 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1940 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);