2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * OCP attachment driver for Freescale TSEC controller.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/socket.h>
40 #include <sys/sysctl.h>
43 #include <machine/bus.h>
45 #include <machine/resource.h>
47 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_arp.h>
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
56 #include <machine/bootinfo.h>
57 #include <machine/ocpbus.h>
59 #include <dev/tsec/if_tsec.h>
60 #include <dev/tsec/if_tsecreg.h>
62 #include "miibus_if.h"
64 #define OCP_TSEC_RID_TXIRQ 0
65 #define OCP_TSEC_RID_RXIRQ 1
66 #define OCP_TSEC_RID_ERRIRQ 2
68 extern struct tsec_softc *tsec0_sc;
70 static int tsec_ocp_probe(device_t dev);
71 static int tsec_ocp_attach(device_t dev);
72 static int tsec_ocp_detach(device_t dev);
73 static int tsec_setup_intr(struct tsec_softc *sc, struct resource **ires,
74 void **ihand, int *irid, driver_intr_t handler, const char *iname);
75 static void tsec_release_intr(struct tsec_softc *sc, struct resource *ires,
76 void *ihand, int irid, const char *iname);
78 static device_method_t tsec_methods[] = {
79 /* Device interface */
80 DEVMETHOD(device_probe, tsec_ocp_probe),
81 DEVMETHOD(device_attach, tsec_ocp_attach),
82 DEVMETHOD(device_detach, tsec_ocp_detach),
84 DEVMETHOD(device_shutdown, tsec_shutdown),
85 DEVMETHOD(device_suspend, tsec_suspend),
86 DEVMETHOD(device_resume, tsec_resume),
89 DEVMETHOD(bus_print_child, bus_generic_print_child),
90 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
93 DEVMETHOD(miibus_readreg, tsec_miibus_readreg),
94 DEVMETHOD(miibus_writereg, tsec_miibus_writereg),
95 DEVMETHOD(miibus_statchg, tsec_miibus_statchg),
99 static driver_t tsec_ocp_driver = {
102 sizeof(struct tsec_softc),
105 DRIVER_MODULE(tsec, ocpbus, tsec_ocp_driver, tsec_devclass, 0, 0);
106 MODULE_DEPEND(tsec, ocpbus, 1, 1, 1);
107 MODULE_DEPEND(tsec, ether, 1, 1, 1);
110 tsec_ocp_probe(device_t dev)
112 struct tsec_softc *sc;
118 parent = device_get_parent(dev);
120 error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype);
123 if (devtype != OCPBUS_DEVTYPE_TSEC)
126 sc = device_get_softc(dev);
129 sc->sc_rres = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->sc_rrid,
130 0ul, ~0ul, TSEC_IO_SIZE, RF_ACTIVE);
131 if (sc->sc_rres == NULL)
134 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
135 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
137 /* Check that we actually have a TSEC at this address */
138 id = TSEC_READ(sc, TSEC_REG_ID) | TSEC_READ(sc, TSEC_REG_ID2);
140 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
145 device_set_desc(dev, "Three-Speed Ethernet Controller");
146 return (BUS_PROBE_DEFAULT);
150 tsec_ocp_attach(device_t dev)
152 struct tsec_softc *sc;
155 sc = device_get_softc(dev);
158 /* XXX add comment on weird FSL's MII registers access design */
159 if (device_get_unit(dev) == 0)
163 callout_init(&sc->tsec_callout, 1);
166 mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "TSEC TX lock",
168 mtx_init(&sc->receive_lock, device_get_nameunit(dev), "TSEC RX lock",
171 /* Allocate IO memory for TSEC registers */
173 sc->sc_rres = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->sc_rrid,
174 0ul, ~0ul, TSEC_IO_SIZE, RF_ACTIVE);
175 if (sc->sc_rres == NULL) {
176 device_printf(dev, "could not allocate IO memory range!\n");
179 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
180 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
183 if (tsec_attach(sc) != 0) {
184 device_printf(dev, "could not be configured\n");
188 /* Set up interrupts (TX/RX/ERR) */
189 sc->sc_transmit_irid = OCP_TSEC_RID_TXIRQ;
190 error = tsec_setup_intr(sc, &sc->sc_transmit_ires,
191 &sc->sc_transmit_ihand, &sc->sc_transmit_irid,
192 tsec_transmit_intr, "TX");
196 sc->sc_receive_irid = OCP_TSEC_RID_RXIRQ;
197 error = tsec_setup_intr(sc, &sc->sc_receive_ires,
198 &sc->sc_receive_ihand, &sc->sc_receive_irid,
199 tsec_receive_intr, "RX");
203 sc->sc_error_irid = OCP_TSEC_RID_ERRIRQ;
204 error = tsec_setup_intr(sc, &sc->sc_error_ires,
205 &sc->sc_error_ihand, &sc->sc_error_irid,
206 tsec_error_intr, "ERR");
213 tsec_release_intr(sc, sc->sc_receive_ires, sc->sc_receive_ihand,
214 sc->sc_receive_irid, "RX");
216 tsec_release_intr(sc, sc->sc_transmit_ires, sc->sc_transmit_ihand,
217 sc->sc_transmit_irid, "TX");
219 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
221 mtx_destroy(&sc->receive_lock);
222 mtx_destroy(&sc->transmit_lock);
227 tsec_setup_intr(struct tsec_softc *sc, struct resource **ires, void **ihand,
228 int *irid, driver_intr_t handler, const char *iname)
232 (*ires) = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, irid, RF_ACTIVE);
233 if ((*ires) == NULL) {
234 device_printf(sc->dev, "could not allocate %s IRQ\n", iname);
237 error = bus_setup_intr(sc->dev, *ires, INTR_TYPE_NET | INTR_MPSAFE,
238 NULL, handler, sc, ihand);
240 device_printf(sc->dev, "failed to set up %s IRQ\n", iname);
241 if (bus_release_resource(sc->dev, SYS_RES_IRQ, *irid, *ires))
242 device_printf(sc->dev, "could not release %s IRQ\n", iname);
250 tsec_release_intr(struct tsec_softc *sc, struct resource *ires, void *ihand,
251 int irid, const char *iname)
258 error = bus_teardown_intr(sc->dev, ires, ihand);
260 device_printf(sc->dev, "bus_teardown_intr() failed for %s intr"
261 ", error %d\n", iname, error);
263 error = bus_release_resource(sc->dev, SYS_RES_IRQ, irid, ires);
265 device_printf(sc->dev, "bus_release_resource() failed for %s intr"
266 ", error %d\n", iname, error);
270 tsec_ocp_detach(device_t dev)
272 struct tsec_softc *sc;
275 sc = device_get_softc(dev);
277 /* Wait for stopping watchdog */
278 callout_drain(&sc->tsec_callout);
280 /* Stop and release all interrupts */
281 tsec_release_intr(sc, sc->sc_transmit_ires, sc->sc_transmit_ihand,
282 sc->sc_transmit_irid, "TX");
283 tsec_release_intr(sc, sc->sc_receive_ires, sc->sc_receive_ihand,
284 sc->sc_receive_irid, "RX");
285 tsec_release_intr(sc, sc->sc_error_ires, sc->sc_error_ihand,
286 sc->sc_error_irid, "ERR");
291 /* Free IO memory handler */
293 error = bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid,
296 device_printf(dev, "bus_release_resource() failed for"
297 " IO memory, error %d\n", error);
301 mtx_destroy(&sc->receive_lock);
302 mtx_destroy(&sc->transmit_lock);
307 tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr)
318 parent = device_get_parent(sc->dev);
319 if (BUS_READ_IVAR(parent, sc->dev, OCPBUS_IVAR_MACADDR,
321 bcopy((uint8_t *)macaddr, addr, 6);
326 * Fall back -- use the currently programmed address in the hope that
327 * it was set be firmware...
329 curmac.reg[0] = TSEC_READ(sc, TSEC_REG_MACSTNADDR1);
330 curmac.reg[1] = TSEC_READ(sc, TSEC_REG_MACSTNADDR2);
331 for (i = 0; i < 6; i++)
332 a[5-i] = curmac.addr[i];