2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
5 * Copyright (c) 2004-05 Vinod Kashyap
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * AMCC'S 3ware driver for 9000 series storage controllers.
35 * Author: Vinod Kashyap
36 * Modifications by: Adam Radford
37 * Modifications by: Manjunath Ranganathaiah
45 * Macros, structures and functions shared between OSL and CL,
49 #define TW_CL_NULL ((TW_VOID *)0)
53 #define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */
54 #define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */
55 #define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */
56 #define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */
57 #define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */
59 #define TW_CL_BAR_TYPE_IO 1 /* I/O base address */
60 #define TW_CL_BAR_TYPE_MEM 2 /* memory base address */
61 #define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */
63 #ifdef TW_OSL_ENCLOSURE_SUPPORT
64 #define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support
65 -- enclosure target id is 64 */
66 #else /* TW_OSL_ENCLOSURE_SUPPORT */
67 #define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */
68 #endif /* TW_OSL_ENCLOSURE_SUPPORT */
70 #define TW_CL_MAX_NUM_LUNS 255 /* max # of LUN's we support */
71 #define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */
74 * Though we can support 256 simultaneous requests, we advertise as capable
75 * of supporting only 255, since we want to keep one CL internal request
76 * context packet always available for internal requests.
78 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256 /* max simult reqs supported */
80 #define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */
81 #define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */
83 /* Possible values of ctlr->flags */
84 #define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */
85 #define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */
86 #define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */
87 #define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */
88 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
90 /* Possible error values from the Common Layer. */
91 #define TW_CL_ERR_REQ_SUCCESS 0
92 #define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0)
93 #define TW_CL_ERR_REQ_INVALID_TARGET (1<<1)
94 #define TW_CL_ERR_REQ_INVALID_LUN (1<<2)
95 #define TW_CL_ERR_REQ_SCSI_ERROR (1<<3)
96 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4)
97 #define TW_CL_ERR_REQ_BUS_RESET (1<<5)
98 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6)
100 /* Possible values of req_pkt->flags */
101 #define TW_CL_REQ_RETRY_ON_BUSY (1<<0)
102 #define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1)
104 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3
105 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4
106 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21
107 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22
108 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5
109 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8
110 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7
111 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10
113 #define TW_CL_SEVERITY_ERROR 0x1
114 #define TW_CL_SEVERITY_WARNING 0x2
115 #define TW_CL_SEVERITY_INFO 0x3
116 #define TW_CL_SEVERITY_DEBUG 0x4
118 #define TW_CL_SEVERITY_ERROR_STRING "ERROR"
119 #define TW_CL_SEVERITY_WARNING_STRING "WARNING"
120 #define TW_CL_SEVERITY_INFO_STRING "INFO"
121 #define TW_CL_SEVERITY_DEBUG_STRING "DEBUG"
124 * Structure, a pointer to which is used as the controller handle in
125 * communications between the OS Layer and the Common Layer.
127 struct tw_cl_ctlr_handle {
128 TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */
129 TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */
133 * Structure, a pointer to which is used as the request handle in
134 * communications between the OS Layer and the Common Layer.
136 struct tw_cl_req_handle {
137 TW_VOID *osl_req_ctxt; /* OSL's request context */
138 TW_VOID *cl_req_ctxt; /* CL's request context */
139 TW_UINT8 is_io; /* Only freeze/release simq for IOs */
142 /* Structure used to describe SCSI requests to CL. */
143 struct tw_cl_scsi_req_packet {
144 TW_UINT32 unit; /* unit # to send cmd to */
145 TW_UINT32 lun; /* LUN to send cmd to */
146 TW_UINT8 *cdb; /* ptr to SCSI cdb */
147 TW_UINT32 cdb_len; /* # of valid cdb bytes */
148 TW_UINT32 sense_len; /* # of bytes of valid sense info */
149 TW_UINT8 *sense_data; /* ptr to sense data, if any */
150 TW_UINT32 scsi_status; /* SCSI status returned by fw */
151 TW_UINT32 sgl_entries; /* # of SG descriptors */
152 TW_UINT8 *sg_list; /* ptr to SG list */
155 /* Structure used to describe pass through command packets to CL. */
156 struct tw_cl_passthru_req_packet {
157 TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */
158 TW_UINT32 cmd_pkt_length; /* size of cmd pkt */
159 TW_UINT32 sgl_entries; /* # of SG descriptors */
160 TW_UINT8 *sg_list; /* ptr to SG list */
163 /* Request packet submitted to the Common Layer, by the OS Layer. */
164 struct tw_cl_req_packet {
165 TW_UINT32 cmd; /* Common Layer cmd */
166 TW_UINT32 flags; /* flags describing request */
167 TW_UINT32 status; /* Common Layer returned status */
168 TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle);
169 /* OSL routine to be called by CL on req completion */
170 TW_VOID (*tw_osl_sgl_callback)(
171 struct tw_cl_req_handle *req_handle, TW_VOID *sg_list,
172 TW_UINT32 *num_sgl_entries);
173 /* OSL callback to get SG list. */
176 struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */
177 struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/
183 * Packet that describes an AEN/error generated by the controller,
184 * Common Layer, or even the OS Layer.
186 struct tw_cl_event_packet {
187 TW_UINT32 sequence_id;
188 TW_UINT32 time_stamp_sec;
192 TW_UINT8 repeat_count;
193 TW_UINT8 parameter_len;
194 TW_UINT8 parameter_data[98];
196 TW_UINT8 severity_str[20];
200 /* Structure to link 2 adjacent elements in a list. */
202 struct tw_cl_link *next;
203 struct tw_cl_link *prev;
207 /* Scatter/Gather list entry with 32 bit addresses. */
208 struct tw_cl_sg_desc32 {
213 /* Scatter/Gather list entry with 64 bit addresses. */
214 struct tw_cl_sg_desc64 {
221 /* Byte swap functions. Valid only if running on big endian platforms. */
222 #ifdef TW_OSL_BIG_ENDIAN
224 #define TW_CL_SWAP16_WITH_CAST(x) \
225 ((x << 8) | (x >> 8))
227 #define TW_CL_SWAP32_WITH_CAST(x) \
228 ((x << 24) | ((x << 8) & (0xFF0000)) | \
229 ((x >> 8) & (0xFF00)) | (x >> 24))
231 #define TW_CL_SWAP64_WITH_CAST(x) \
232 ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\
233 ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0]))))
235 #else /* TW_OSL_BIG_ENDIAN */
237 #define TW_CL_SWAP16_WITH_CAST(x) x
238 #define TW_CL_SWAP32_WITH_CAST(x) x
239 #define TW_CL_SWAP64_WITH_CAST(x) x
241 #endif /* TW_OSL_BIG_ENDIAN */
243 #define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x))
244 #define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x))
245 #define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x))
247 /* Queue manipulation functions. */
249 /* Initialize a queue. */
250 #define TW_CL_Q_INIT(head) do { \
251 (head)->prev = (head)->next = head; \
254 /* Insert an item at the head of the queue. */
255 #define TW_CL_Q_INSERT_HEAD(head, item) do { \
256 (item)->next = (head)->next; \
257 (item)->prev = head; \
258 (head)->next->prev = item; \
259 (head)->next = item; \
262 /* Insert an item at the tail of the queue. */
263 #define TW_CL_Q_INSERT_TAIL(head, item) do { \
264 (item)->next = head; \
265 (item)->prev = (head)->prev; \
266 (head)->prev->next = item; \
267 (head)->prev = item; \
270 /* Remove an item from the head of the queue. */
271 #define TW_CL_Q_REMOVE_ITEM(head, item) do { \
272 (item)->prev->next = (item)->next; \
273 (item)->next->prev = (item)->prev; \
276 /* Retrieve the item at the head of the queue. */
277 #define TW_CL_Q_FIRST_ITEM(head) \
278 (((head)->next != head) ? ((head)->next) : TW_CL_NULL)
280 /* Retrieve the item at the tail of the queue. */
281 #define TW_CL_Q_LAST_ITEM(head) \
282 (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL)
284 /* Retrieve the item next to a given item in the queue. */
285 #define TW_CL_Q_NEXT_ITEM(head, item) \
286 (((item)->next != head) ? ((item)->next) : TW_CL_NULL)
288 /* Retrieve the item previous to a given item in the queue. */
289 #define TW_CL_Q_PREV_ITEM(head, item) \
290 (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL)
292 /* Determine the offset of a field from the head of the structure it is in. */
293 #define TW_CL_STRUCT_OFFSET(struct_type, field) \
294 (TW_INT8 *)(&((struct_type *)0)->field)
297 * Determine the address of the head of a structure, given the address of a
300 #define TW_CL_STRUCT_HEAD(addr, struct_type, field) \
301 (struct_type *)((TW_INT8 *)addr - \
302 TW_CL_STRUCT_OFFSET(struct_type, field))
304 #ifndef TW_BUILDING_API
306 #include "tw_osl_inline.h"
309 * The following are extern declarations of OS Layer defined functions called
310 * by the Common Layer. If any function has been defined as a macro in
311 * tw_osl_share.h, we will not make the extern declaration here.
314 #ifndef tw_osl_breakpoint
315 /* Allows setting breakpoints in the CL code for debugging purposes. */
316 extern TW_VOID tw_osl_breakpoint(TW_VOID);
319 #ifndef tw_osl_timeout
320 /* Start OS timeout() routine after controller reset sequence */
321 extern TW_VOID tw_osl_timeout(struct tw_cl_req_handle *req_handle);
324 #ifndef tw_osl_untimeout
325 /* Stop OS timeout() routine during controller reset sequence */
326 extern TW_VOID tw_osl_untimeout(struct tw_cl_req_handle *req_handle);
329 #ifndef tw_osl_cur_func
330 /* Text name of current function. */
331 extern TW_INT8 *tw_osl_cur_func(TW_VOID);
335 #ifndef tw_osl_dbg_printf
336 /* Print to syslog/event log/debug console, as applicable. */
337 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle,
338 const TW_INT8 *fmt, ...);
340 #endif /* TW_OSL_DEBUG */
343 /* Cause a delay of usecs micro-seconds. */
344 extern TW_VOID tw_osl_delay(TW_INT32 usecs);
347 #ifndef tw_osl_destroy_lock
348 /* Create/initialize a lock for CL's use. */
349 extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle,
350 TW_LOCK_HANDLE *lock);
353 #ifndef tw_osl_free_lock
354 /* Free a previously held lock. */
355 extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle,
356 TW_LOCK_HANDLE *lock);
359 #ifndef tw_osl_get_local_time
360 /* Get local time. */
361 extern TW_TIME tw_osl_get_local_time(TW_VOID);
364 #ifndef tw_osl_get_lock
365 /* Acquire a lock. */
366 extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle,
367 TW_LOCK_HANDLE *lock);
370 #ifndef tw_osl_init_lock
371 /* Create/initialize a lock for CL's use. */
372 extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle,
373 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock);
376 #ifndef tw_osl_memcpy
377 /* Copy 'size' bytes from 'src' to 'dest'. */
378 extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size);
381 #ifndef tw_osl_memzero
382 /* Zero 'size' bytes starting at 'addr'. */
383 extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size);
386 #ifndef tw_osl_notify_event
387 /* Notify OSL of a controller/CL (or even OSL) event. */
388 extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle,
389 struct tw_cl_event_packet *event);
392 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
393 #ifndef tw_osl_read_pci_config
394 /* Read 'size' bytes from 'offset' in the PCI config space. */
395 extern TW_UINT32 tw_osl_read_pci_config(
396 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size);
398 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
400 #ifndef tw_osl_read_reg
401 /* Read 'size' bytes at 'offset' from base address of this controller. */
402 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle,
403 TW_INT32 offset, TW_INT32 size);
406 #ifndef tw_osl_scan_bus
407 /* Request OSL for a bus scan. */
408 extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle);
411 #ifdef TW_OSL_CAN_SLEEP
413 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */
414 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle,
415 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout);
417 #endif /* TW_OSL_CAN_SLEEP */
419 #ifndef tw_osl_sprintf
420 /* Standard sprintf. */
421 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...);
424 #ifndef tw_osl_strcpy
425 /* Copy string 'src' to 'dest'. */
426 extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
429 #ifndef tw_osl_strlen
430 /* Return length of string pointed at by 'str'. */
431 extern TW_INT32 tw_osl_strlen(TW_VOID *str);
434 #ifndef tw_osl_vsprintf
435 /* Standard vsprintf. */
436 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
439 #ifdef TW_OSL_CAN_SLEEP
440 #ifndef tw_osl_wakeup
441 /* Wake up a thread sleeping by a call to tw_osl_sleep. */
442 extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle,
443 TW_SLEEP_HANDLE *sleep_handle);
445 #endif /* TW_OSL_CAN_SLEEP */
447 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
448 #ifndef tw_osl_write_pci_config
449 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */
450 extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle,
451 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
453 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
455 #ifndef tw_osl_write_reg
457 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of
460 extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle,
461 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
464 /* Functions in the Common Layer */
466 /* Creates and queues AEN's. Also notifies OS Layer. */
467 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
468 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code,
469 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc,
470 TW_UINT8 *event_specific_desc, ...);
472 /* Indicates whether a ctlr is supported by CL. */
473 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id);
475 /* Submit a firmware cmd packet. */
476 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
477 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
479 /* Find out how much memory CL needs. */
480 extern TW_INT32 tw_cl_get_mem_requirements(
481 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
482 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
483 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
484 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
487 /* Return PCI BAR info. */
488 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
489 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size);
491 /* Initialize Common Layer for a given controller. */
492 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
493 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
494 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
495 TW_UINT64 dma_mem_phys
498 extern TW_VOID tw_cl_set_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
499 extern TW_INT32 tw_cl_is_reset_needed(struct tw_cl_ctlr_handle *ctlr_handle);
500 extern TW_INT32 tw_cl_is_active(struct tw_cl_ctlr_handle *ctlr_handle);
502 /* CL's interrupt handler. */
503 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
505 /* CL's ioctl handler. */
506 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle,
507 u_long cmd, TW_VOID *buf);
510 /* Print CL's state/statistics for a controller. */
511 extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle);
513 /* Prints CL internal details of a given request. */
514 extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle);
515 #endif /* TW_OSL_DEBUG */
517 /* Soft reset controller. */
518 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle);
521 /* Reset CL's statistics for a controller. */
522 extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle);
523 #endif /* TW_OSL_DEBUG */
525 /* Stop a controller. */
526 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
529 /* Submit a SCSI I/O request. */
530 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
531 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
533 #endif /* TW_BUILDING_API */
535 #endif /* TW_CL_SHARE_H */