2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake. (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
38 /* control register bit definitions */
39 #define TWE_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
40 #define TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
41 #define TWE_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
42 #define TWE_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
43 #define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
44 #define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
45 #define TWE_CONTROL_CLEAR_ERROR_STATUS 0x00000200
46 #define TWE_CONTROL_ISSUE_SOFT_RESET 0x00000100
47 #define TWE_CONTROL_ENABLE_INTERRUPTS 0x00000080
48 #define TWE_CONTROL_DISABLE_INTERRUPTS 0x00000040
49 #define TWE_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
50 #define TWE_CONTROL_CLEAR_PARITY_ERROR 0x00800000
51 #define TWE_CONTROL_CLEAR_PCI_ABORT 0x00100000
53 #define TWE_SOFT_RESET(sc) TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET | \
54 TWE_CONTROL_CLEAR_HOST_INTERRUPT | \
55 TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
56 TWE_CONTROL_MASK_COMMAND_INTERRUPT | \
57 TWE_CONTROL_MASK_RESPONSE_INTERRUPT | \
58 TWE_CONTROL_CLEAR_ERROR_STATUS | \
59 TWE_CONTROL_DISABLE_INTERRUPTS)
61 /* status register bit definitions */
62 #define TWE_STATUS_MAJOR_VERSION_MASK 0xF0000000
63 #define TWE_STATUS_MINOR_VERSION_MASK 0x0F000000
64 #define TWE_STATUS_PCI_PARITY_ERROR 0x00800000
65 #define TWE_STATUS_QUEUE_ERROR 0x00400000
66 #define TWE_STATUS_MICROCONTROLLER_ERROR 0x00200000
67 #define TWE_STATUS_PCI_ABORT 0x00100000
68 #define TWE_STATUS_HOST_INTERRUPT 0x00080000
69 #define TWE_STATUS_ATTENTION_INTERRUPT 0x00040000
70 #define TWE_STATUS_COMMAND_INTERRUPT 0x00020000
71 #define TWE_STATUS_RESPONSE_INTERRUPT 0x00010000
72 #define TWE_STATUS_COMMAND_QUEUE_FULL 0x00008000
73 #define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
74 #define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
75 #define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
76 #define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
77 #define TWE_STATUS_CLEARABLE_BITS 0x00D00000
78 #define TWE_STATUS_EXPECTED_BITS 0x00002000
79 #define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
81 /* XXX this is a little harsh, but necessary to chase down firmware problems */
82 #define TWE_STATUS_PANIC_BITS (TWE_STATUS_MICROCONTROLLER_ERROR)
84 /* for use with the %b printf format */
85 #define TWE_STATUS_BITS_DESCRIPTION \
86 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
88 /* detect inconsistencies in the status register */
89 #define TWE_STATUS_ERRORS(x) \
90 (((x & TWE_STATUS_PCI_ABORT) || \
91 (x & TWE_STATUS_PCI_PARITY_ERROR) || \
92 (x & TWE_STATUS_QUEUE_ERROR) || \
93 (x & TWE_STATUS_MICROCONTROLLER_ERROR)) && \
94 (x & TWE_STATUS_MICROCONTROLLER_READY))
96 /* Response queue bit definitions */
97 #define TWE_RESPONSE_ID_MASK 0x00000FF0
99 /* PCI related defines */
100 #define TWE_IO_CONFIG_REG 0x10
101 #define TWE_DEVICE_NAME "3ware Storage Controller"
102 #define TWE_VENDOR_ID 0x13C1
103 #define TWE_DEVICE_ID 0x1000
104 #define TWE_DEVICE_ID_ASIC 0x1001
105 #define TWE_PCI_CLEAR_PARITY_ERROR 0xc100
106 #define TWE_PCI_CLEAR_PCI_ABORT 0x2000
108 /* command packet opcodes */
109 #define TWE_OP_NOP 0x00
110 #define TWE_OP_INIT_CONNECTION 0x01
111 #define TWE_OP_READ 0x02
112 #define TWE_OP_WRITE 0x03
113 #define TWE_OP_READVERIFY 0x04
114 #define TWE_OP_VERIFY 0x05
115 #define TWE_OP_ZEROUNIT 0x08
116 #define TWE_OP_REPLACEUNIT 0x09
117 #define TWE_OP_HOTSWAP 0x0a
118 #define TWE_OP_SETATAFEATURE 0x0c
119 #define TWE_OP_FLUSH 0x0e
120 #define TWE_OP_ABORT 0x0f
121 #define TWE_OP_CHECKSTATUS 0x10
122 #define TWE_OP_GET_PARAM 0x12
123 #define TWE_OP_SET_PARAM 0x13
124 #define TWE_OP_CREATEUNIT 0x14
125 #define TWE_OP_DELETEUNIT 0x15
126 #define TWE_OP_REBUILDUNIT 0x17
127 #define TWE_OP_SECTOR_INFO 0x1a
128 #define TWE_OP_AEN_LISTEN 0x1c
129 #define TWE_OP_CMD_PACKET 0x1d
130 #define TWE_OP_ATA_PASSTHROUGH 0x1e
131 #define TWE_OP_CMD_WITH_DATA 0x1f
133 /* command status values */
134 #define TWE_STATUS_RESET 0xff /* controller requests reset */
135 #define TWE_STATUS_FATAL 0xc0 /* fatal errors not requiring reset */
136 #define TWE_STATUS_WARNING 0x80 /* warnings */
137 #define TWE_STAUS_INFO 0x40 /* informative status */
140 #define TWE_ALIGNMENT 0x200
141 #define TWE_MAX_UNITS 16
142 #define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
143 #define TWE_INIT_MESSAGE_CREDITS 0xff /* older firmware has issues with 256 commands */
144 #define TWE_SHUTDOWN_MESSAGE_CREDITS 0x001
145 #define TWE_INIT_COMMAND_PACKET_SIZE 0x3
146 #define TWE_MAX_SGL_LENGTH 62
147 #define TWE_MAX_ATA_SGL_LENGTH 60
148 #define TWE_MAX_PASSTHROUGH 4096
149 #define TWE_Q_LENGTH TWE_INIT_MESSAGE_CREDITS
150 #define TWE_Q_START 0
151 #define TWE_MAX_RESET_TRIES 3
152 #define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
153 #define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
154 #define TWE_IOCTL 0x80
155 #define TWE_MAX_AEN_TRIES 100
156 #define TWE_UNIT_ONLINE 1
158 /* scatter/gather list entry */
163 } TWE_SG_Entry __packed;
166 u_int8_t opcode:5; /* TWE_OP_INITCONNECTION */
174 u_int16_t message_credits;
175 u_int32_t response_queue_pointer;
176 } TWE_Command_INITCONNECTION __packed;
180 u_int8_t opcode:5; /* TWE_OP_READ/TWE_OP_WRITE */
188 u_int16_t block_count;
190 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
191 } TWE_Command_IO __packed;
195 u_int8_t opcode:5; /* TWE_OP_HOTSWAP */
204 #define TWE_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */
205 #define TWE_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */
206 #define TWE_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */
208 } TWE_Command_HOTSWAP __packed;
212 u_int8_t opcode:5; /* TWE_OP_SETATAFEATURE */
221 #define TWE_OP_SETATAFEATURE_WCE 0x02
222 #define TWE_OP_SETATAFEATURE_DIS_WCE 0x82
223 u_int8_t feature_mode;
225 u_int16_t persistence;
226 } TWE_Command_SETATAFEATURE __packed;
230 u_int8_t opcode:5; /* TWE_OP_CHECKSTATUS */
238 u_int16_t target_status; /* set low byte to target request's ID */
239 } TWE_Command_CHECKSTATUS __packed;
243 u_int8_t opcode:5; /* TWE_OP_GETPARAM, TWE_OP_SETPARAM */
251 u_int16_t param_count;
252 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
253 } TWE_Command_PARAM __packed;
257 u_int8_t opcode:5; /* TWE_OP_REBUILDUNIT */
266 #define TWE_OP_REBUILDUNIT_NOP 0
267 #define TWE_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */
268 #define TWE_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */
269 #define TWE_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */
270 u_int8_t cs:1; /* request state change on src_unit */
271 u_int8_t logical_subunit; /* for RAID10 rebuild of logical subunit */
272 } TWE_Command_REBUILDUNIT __packed;
277 u_int8_t sgl_offset:3;
285 u_int16_t sector_count;
286 u_int16_t sector_num;
287 u_int16_t cylinder_lo;
288 u_int16_t cylinder_hi;
291 TWE_SG_Entry sgl[TWE_MAX_ATA_SGL_LENGTH];
292 } TWE_Command_ATA __packed;
297 u_int8_t sgl_offset:3;
304 #define TWE_FLAGS_SUCCESS 0x00
305 #define TWE_FLAGS_INFORMATIONAL 0x01
306 #define TWE_FLAGS_WARNING 0x02
307 #define TWE_FLAGS_FATAL 0x03
308 #define TWE_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */
309 u_int16_t count; /* block count, parameter count, message credits */
310 } TWE_Command_Generic __packed;
312 /* command packet - must be TWE_ALIGNMENT aligned */
315 TWE_Command_INITCONNECTION initconnection;
317 TWE_Command_PARAM param;
318 TWE_Command_CHECKSTATUS checkstatus;
319 TWE_Command_REBUILDUNIT rebuildunit;
320 TWE_Command_SETATAFEATURE setatafeature;
322 TWE_Command_Generic generic;
326 /* response queue entry */
331 u_int32_t undefined_1:4;
332 u_int32_t response_id:8;
333 u_int32_t undefined_2:20;
336 } TWE_Response_Queue;
339 * From 3ware's documentation:
340 * All parameters maintained by the controller are grouped into related tables.
341 * Tables are are accessed indirectly via get and set parameter commands.
342 * To access a specific parameter in a table, the table ID and parameter index
343 * are used to uniquely identify a parameter. Table 0xffff is the directory
344 * table and provides a list of the table IDs and sizes of all other tables.
345 * Index zero in each table specifies the entire table, and index one specifies
346 * the size of the table. An entire table can be read or set by using index zero.
349 #define TWE_PARAM_PARAM_ALL 0
350 #define TWE_PARAM_PARAM_SIZE 1
352 #define TWE_PARAM_DIRECTORY 0xffff /* size is 4 * number of tables */
353 #define TWE_PARAM_DIRECTORY_TABLES 2 /* 16 bits * number of tables */
354 #define TWE_PARAM_DIRECTORY_SIZES 3 /* 16 bits * number of tables */
356 #define TWE_PARAM_DRIVESUMMARY 0x0002
357 #define TWE_PARAM_DRIVESUMMARY_Num 2 /* number of physical drives [2] */
358 #define TWE_PARAM_DRIVESUMMARY_Status 3 /* array giving drive status per aport */
359 #define TWE_PARAM_DRIVESTATUS_Missing 0x00
360 #define TWE_PARAM_DRIVESTATUS_NotSupp 0xfe
361 #define TWE_PARAM_DRIVESTATUS_Present 0xff
363 #define TWE_PARAM_UNITSUMMARY 0x0003
364 #define TWE_PARAM_UNITSUMMARY_Num 2 /* number of logical units [2] */
365 #define TWE_PARAM_UNITSUMMARY_Status 3 /* array giving unit status [16] */
366 #define TWE_PARAM_UNITSTATUS_Online (1<<0)
367 #define TWE_PARAM_UNITSTATUS_Complete (1<<1)
368 #define TWE_PARAM_UNITSTATUS_MASK 0xfc
369 #define TWE_PARAM_UNITSTATUS_Normal 0xfc
370 #define TWE_PARAM_UNITSTATUS_Initialising 0xf4 /* cannot be incomplete */
371 #define TWE_PARAM_UNITSTATUS_Degraded 0xec
372 #define TWE_PARAM_UNITSTATUS_Rebuilding 0xdc /* cannot be incomplete */
373 #define TWE_PARAM_UNITSTATUS_Verifying 0xcc /* cannot be incomplete */
374 #define TWE_PARAM_UNITSTATUS_Corrupt 0xbc /* cannot be complete */
375 #define TWE_PARAM_UNITSTATUS_Missing 0x00 /* cannot be complete or online */
377 #define TWE_PARAM_DRIVEINFO 0x0200 /* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
378 #define TWE_PARAM_DRIVEINFO_Size 2 /* size in blocks [4] */
379 #define TWE_PARAM_DRIVEINFO_Model 3 /* drive model string [40] */
380 #define TWE_PARAM_DRIVEINFO_Serial 4 /* drive serial number [20] */
381 #define TWE_PARAM_DRIVEINFO_PhysCylNum 5 /* physical geometry [2] */
382 #define TWE_PARAM_DRIVEINFO_PhysHeadNum 6 /* [2] */
383 #define TWE_PARAM_DRIVEINFO_PhysSectorNym 7 /* [2] */
384 #define TWE_PARAM_DRIVEINFO_LogCylNum 8 /* logical geometry [2] */
385 #define TWE_PARAM_DRIVEINFO_LogHeadNum 9 /* [2] */
386 #define TWE_PARAM_DRIVEINFO_LogSectorNum 10 /* [2] */
387 #define TWE_PARAM_DRIVEINFO_UnitNum 11 /* unit number this drive is associated with or 0xff [1] */
388 #define TWE_PARAM_DRIVEINFO_DriveFlags 12 /* N/A [1] */
390 #define TWE_PARAM_APORTTIMEOUT 0x02c0 /* add (aport_number * 3) to parameter index */
391 #define TWE_PARAM_APORTTIMEOUT_READ 2 /* read timeouts last 24hrs [2] */
392 #define TWE_PARAM_APORTTIMEOUT_WRITE 3 /* write timeouts last 24hrs [2] */
393 #define TWE_PARAM_APORTTIMEOUT_DEGRADE 4 /* degrade threshold [2] */
395 #define TWE_PARAM_UNITINFO 0x0300 /* add unit number 0x00-0x0f */
396 #define TWE_PARAM_UNITINFO_Number 2 /* unit number [1] */
397 #define TWE_PARAM_UNITINFO_Status 3 /* unit status [1] */
398 #define TWE_PARAM_UNITINFO_Capacity 4 /* unit capacity in blocks [4] */
399 #define TWE_PARAM_UNITINFO_DescriptorSize 5 /* unit descriptor size + 3 bytes [2] */
400 #define TWE_PARAM_UNITINFO_Descriptor 6 /* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
401 #define TWE_PARAM_UNITINFO_Flags 7 /* unit flags [1] */
402 #define TWE_PARAM_UNITFLAGS_WCE (1<<0)
404 #define TWE_PARAM_AEN 0x0401
405 #define TWE_PARAM_AEN_UnitCode 2 /* (unit number << 8) | AEN code [2] */
406 #define TWE_AEN_QUEUE_EMPTY 0x00
407 #define TWE_AEN_SOFT_RESET 0x01
408 #define TWE_AEN_DEGRADED_MIRROR 0x02 /* reports unit */
409 #define TWE_AEN_CONTROLLER_ERROR 0x03
410 #define TWE_AEN_REBUILD_FAIL 0x04 /* reports unit */
411 #define TWE_AEN_REBUILD_DONE 0x05 /* reports unit */
412 #define TWE_AEN_INCOMP_UNIT 0x06 /* reports unit */
413 #define TWE_AEN_INIT_DONE 0x07 /* reports unit */
414 #define TWE_AEN_UNCLEAN_SHUTDOWN 0x08 /* reports unit */
415 #define TWE_AEN_APORT_TIMEOUT 0x09 /* reports unit, rate limited to 1 per 2^16 errors */
416 #define TWE_AEN_DRIVE_ERROR 0x0a /* reports unit */
417 #define TWE_AEN_REBUILD_STARTED 0x0b /* reports unit */
418 #define TWE_AEN_QUEUE_FULL 0xff
419 #define TWE_AEN_TABLE_UNDEFINED 0x15
420 #define TWE_AEN_CODE(x) ((x) & 0xff)
421 #define TWE_AEN_UNIT(x) ((x) >> 8)
423 #define TWE_PARAM_VERSION 0x0402
424 #define TWE_PARAM_VERSION_Mon 2 /* monitor version [16] */
425 #define TWE_PARAM_VERSION_FW 3 /* firmware version [16] */
426 #define TWE_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
427 #define TWE_PARAM_VERSION_PCB 5 /* PCB version [8] */
428 #define TWE_PARAM_VERSION_ATA 6 /* A-chip version [8] */
429 #define TWE_PARAM_VERSION_PCI 7 /* P-chip version [8] */
430 #define TWE_PARAM_VERSION_CtrlModel 8 /* N/A */
431 #define TWE_PARAM_VERSION_CtrlSerial 9 /* N/A */
432 #define TWE_PARAM_VERSION_SBufSize 10 /* N/A */
433 #define TWE_PARAM_VERSION_CompCode 11 /* compatibility code [4] */
435 #define TWE_PARAM_CONTROLLER 0x0403
436 #define TWE_PARAM_CONTROLLER_DCBSectors 2 /* # sectors reserved for DCB per drive [2] */
437 #define TWE_PARAM_CONTROLLER_PortCount 3 /* number of drive ports [1] */
439 #define TWE_PARAM_FEATURES 0x404
440 #define TWE_PARAM_FEATURES_DriverShutdown 2 /* set to 1 if driver supports shutdown notification [1] */
444 u_int8_t num_subunits; /* must be zero */
445 u_int8_t configuration;
446 #define TWE_UD_CONFIG_CBOD 0x0c /* JBOD with DCB, used for mirrors */
447 #define TWE_UD_CONFIG_SPARE 0x0d /* same as CBOD, but firmware will use as spare */
448 #define TWE_UD_CONFIG_SUBUNIT 0x0e /* drive is a subunit in an array */
449 #define TWE_UD_CONFIG_JBOD 0x0f /* plain drive */
450 u_int8_t phys_drv_num; /* may be 0xff if port can't be determined at runtime */
451 u_int8_t log_drv_num; /* must be zero for configuration == 0x0f */
453 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
454 } TWE_Unit_Descriptor __packed;
458 u_int8_t flag; /* must be 0xff */
460 u_int8_t mirunit_status[4]; /* bitmap of functional subunits in each mirror */
462 } TWE_Mirror_Descriptor __packed;
466 u_int8_t num_subunits; /* number of subunits, or number of mirror units in RAID10 */
467 u_int8_t configuration;
468 #define TWE_UD_CONFIG_RAID0 0x00
469 #define TWE_UD_CONFIG_RAID1 0x01
470 #define TWE_UD_CONFIG_TwinStor 0x02
471 #define TWE_UD_CONFIG_RAID5 0x05
472 #define TWE_UD_CONFIG_RAID10 0x06
473 u_int8_t stripe_size;
474 #define TWE_UD_STRIPE_4k 0x03
475 #define TWE_UD_STRIPE_8k 0x04
476 #define TWE_UD_STRIPE_16k 0x05
477 #define TWE_UD_STRIPE_32k 0x06
478 #define TWE_UD_STRIPE_64k 0x07
479 u_int8_t log_drv_status; /* bitmap of functional subunits, or mirror units in RAID10 */
481 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
482 TWE_Unit_Descriptor subunit[0]; /* subunit descriptors, in RAID10 mode is [mirunit][subunit] */
483 } TWE_Array_Descriptor __packed;
488 u_int8_t parameter_id;
489 u_int8_t parameter_size_bytes;
491 } TWE_Param __packed;