2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2010, LSI Corp.
6 * Author : Manjunath Ranganathaiah
7 * Support: freebsdraid@lsi.com
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
19 * 3. Neither the name of the <ORGANIZATION> nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <dev/tws/tws.h>
41 #include <dev/tws/tws_services.h>
42 #include <dev/tws/tws_hdm.h>
45 #include <cam/cam_ccb.h>
47 MALLOC_DEFINE(M_TWS, "twsbuf", "buffers used by tws driver");
48 int tws_queue_depth = TWS_MAX_REQS;
49 int tws_enable_msi = 0;
50 int tws_enable_msix = 0;
55 extern int tws_cam_attach(struct tws_softc *sc);
56 extern void tws_cam_detach(struct tws_softc *sc);
57 extern int tws_init_ctlr(struct tws_softc *sc);
58 extern boolean tws_ctlr_ready(struct tws_softc *sc);
59 extern void tws_turn_off_interrupts(struct tws_softc *sc);
60 extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req,
62 extern struct tws_request *tws_q_remove_request(struct tws_softc *sc,
63 struct tws_request *req, u_int8_t q_type );
64 extern struct tws_request *tws_q_remove_head(struct tws_softc *sc,
66 extern boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id);
67 extern boolean tws_ctlr_reset(struct tws_softc *sc);
68 extern void tws_intr(void *arg);
69 extern int tws_use_32bit_sgls;
72 struct tws_request *tws_get_request(struct tws_softc *sc, u_int16_t type);
73 int tws_init_connect(struct tws_softc *sc, u_int16_t mc);
74 void tws_send_event(struct tws_softc *sc, u_int8_t event);
75 uint8_t tws_get_state(struct tws_softc *sc);
76 void tws_release_request(struct tws_request *req);
80 /* Function prototypes */
81 static d_open_t tws_open;
82 static d_close_t tws_close;
83 static d_read_t tws_read;
84 static d_write_t tws_write;
85 extern d_ioctl_t tws_ioctl;
87 static int tws_init(struct tws_softc *sc);
88 static void tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
91 static int tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size);
92 static int tws_init_aen_q(struct tws_softc *sc);
93 static int tws_init_trace_q(struct tws_softc *sc);
94 static int tws_setup_irq(struct tws_softc *sc);
95 int tws_setup_intr(struct tws_softc *sc, int irqs);
96 int tws_teardown_intr(struct tws_softc *sc);
99 /* Character device entry points */
101 static struct cdevsw tws_cdevsw = {
102 .d_version = D_VERSION,
104 .d_close = tws_close,
106 .d_write = tws_write,
107 .d_ioctl = tws_ioctl,
112 * In the cdevsw routines, we find our softc by using the si_drv1 member
113 * of struct cdev. We set this variable to point to our softc in our
114 * attach routine when we create the /dev entry.
118 tws_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
120 struct tws_softc *sc = dev->si_drv1;
123 TWS_TRACE_DEBUG(sc, "entry", dev, oflags);
128 tws_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
130 struct tws_softc *sc = dev->si_drv1;
133 TWS_TRACE_DEBUG(sc, "entry", dev, fflag);
138 tws_read(struct cdev *dev, struct uio *uio, int ioflag)
140 struct tws_softc *sc = dev->si_drv1;
143 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
148 tws_write(struct cdev *dev, struct uio *uio, int ioflag)
150 struct tws_softc *sc = dev->si_drv1;
153 TWS_TRACE_DEBUG(sc, "entry", dev, ioflag);
157 /* PCI Support Functions */
160 * Compare the device ID of this device against the IDs that this driver
161 * supports. If there is a match, set the description and return success.
164 tws_probe(device_t dev)
166 static u_int8_t first_ctlr = 1;
168 if ((pci_get_vendor(dev) == TWS_VENDOR_ID) &&
169 (pci_get_device(dev) == TWS_DEVICE_ID)) {
170 device_set_desc(dev, "LSI 3ware SAS/SATA Storage Controller");
172 printf("LSI 3ware device driver for SAS/SATA storage "
173 "controllers, version: %s\n", TWS_DRIVER_VERSION_STRING);
177 return(BUS_PROBE_DEFAULT);
182 /* Attach function is only called if the probe is successful. */
185 tws_attach(device_t dev)
187 struct tws_softc *sc = device_get_softc(dev);
192 /* Look up our softc and initialize its fields. */
194 sc->device_id = pci_get_device(dev);
195 sc->subvendor_id = pci_get_subvendor(dev);
196 sc->subdevice_id = pci_get_subdevice(dev);
198 /* Intialize mutexes */
199 mtx_init( &sc->q_lock, "tws_q_lock", NULL, MTX_DEF);
200 mtx_init( &sc->sim_lock, "tws_sim_lock", NULL, MTX_DEF);
201 mtx_init( &sc->gen_lock, "tws_gen_lock", NULL, MTX_DEF);
202 mtx_init( &sc->io_lock, "tws_io_lock", NULL, MTX_DEF | MTX_RECURSE);
203 callout_init(&sc->stats_timer, 1);
205 if ( tws_init_trace_q(sc) == FAILURE )
206 printf("trace init failure\n");
207 /* send init event */
208 mtx_lock(&sc->gen_lock);
209 tws_send_event(sc, TWS_INIT_START);
210 mtx_unlock(&sc->gen_lock);
213 #if _BYTE_ORDER == _BIG_ENDIAN
214 TWS_TRACE(sc, "BIG endian", 0, 0);
216 /* sysctl context setup */
217 sysctl_ctx_init(&sc->tws_clist);
218 sc->tws_oidp = SYSCTL_ADD_NODE(&sc->tws_clist,
219 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
220 device_get_nameunit(dev),
222 if ( sc->tws_oidp == NULL ) {
223 tws_log(sc, SYSCTL_TREE_NODE_ADD);
226 SYSCTL_ADD_STRING(&sc->tws_clist, SYSCTL_CHILDREN(sc->tws_oidp),
227 OID_AUTO, "driver_version", CTLFLAG_RD,
228 TWS_DRIVER_VERSION_STRING, 0, "TWS driver version");
230 pci_enable_busmaster(dev);
232 bar = pci_read_config(dev, TWS_PCI_BAR0, 4);
233 TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0);
234 bar = pci_read_config(dev, TWS_PCI_BAR1, 4);
235 bar = bar & ~TWS_BIT2;
236 TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0);
238 /* MFA base address is BAR2 register used for
239 * push mode. Firmware will evatualy move to
240 * pull mode during witch this needs to change
242 #ifndef TWS_PULL_MODE_ENABLE
243 sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4);
244 sc->mfa_base = sc->mfa_base & ~TWS_BIT2;
245 TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0);
248 /* allocate MMIO register space */
249 sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */
250 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
251 &(sc->reg_res_id), RF_ACTIVE))
253 tws_log(sc, ALLOC_MEMORY_RES);
256 sc->bus_tag = rman_get_bustag(sc->reg_res);
257 sc->bus_handle = rman_get_bushandle(sc->reg_res);
259 #ifndef TWS_PULL_MODE_ENABLE
260 /* Allocate bus space for inbound mfa */
261 sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */
262 if ((sc->mfa_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
263 &(sc->mfa_res_id), RF_ACTIVE))
265 tws_log(sc, ALLOC_MEMORY_RES);
268 sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res);
269 sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res);
272 /* Allocate and register our interrupt. */
273 sc->intr_type = TWS_INTx; /* default */
275 if ( tws_enable_msi )
276 sc->intr_type = TWS_MSI;
277 if ( tws_setup_irq(sc) == FAILURE ) {
278 tws_log(sc, ALLOC_MEMORY_RES);
283 * Create a /dev entry for this device. The kernel will assign us
284 * a major number automatically. We use the unit number of this
285 * device as the minor number and name the character device
288 sc->tws_cdev = make_dev(&tws_cdevsw, device_get_unit(dev),
289 UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u",
290 device_get_unit(dev));
291 sc->tws_cdev->si_drv1 = sc;
293 if ( tws_init(sc) == FAILURE ) {
294 tws_log(sc, TWS_INIT_FAILURE);
297 if ( tws_init_ctlr(sc) == FAILURE ) {
298 tws_log(sc, TWS_CTLR_INIT_FAILURE);
301 if ((error = tws_cam_attach(sc))) {
302 tws_log(sc, TWS_CAM_ATTACH);
305 /* send init complete event */
306 mtx_lock(&sc->gen_lock);
307 tws_send_event(sc, TWS_INIT_COMPLETE);
308 mtx_unlock(&sc->gen_lock);
310 TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id);
314 tws_teardown_intr(sc);
315 destroy_dev(sc->tws_cdev);
316 if (sc->dma_mem_phys)
317 bus_dmamap_unload(sc->cmd_tag, sc->cmd_map);
319 bus_dmamem_free(sc->cmd_tag, sc->dma_mem, sc->cmd_map);
321 bus_dma_tag_destroy(sc->cmd_tag);
323 for(i=0;i<sc->irqs;i++) {
324 if ( sc->irq_res[i] ){
325 if (bus_release_resource(sc->tws_dev,
326 SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
327 TWS_TRACE(sc, "bus irq res", 0, 0);
330 #ifndef TWS_PULL_MODE_ENABLE
334 if (bus_release_resource(sc->tws_dev,
335 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
336 TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id);
339 if (bus_release_resource(sc->tws_dev,
340 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
341 TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id);
344 mtx_destroy(&sc->q_lock);
345 mtx_destroy(&sc->sim_lock);
346 mtx_destroy(&sc->gen_lock);
347 mtx_destroy(&sc->io_lock);
348 sysctl_ctx_free(&sc->tws_clist);
355 tws_detach(device_t dev)
357 struct tws_softc *sc = device_get_softc(dev);
361 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
363 mtx_lock(&sc->gen_lock);
364 tws_send_event(sc, TWS_UNINIT_START);
365 mtx_unlock(&sc->gen_lock);
367 /* needs to disable interrupt before detaching from cam */
368 tws_turn_off_interrupts(sc);
369 /* clear door bell */
370 tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
371 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
372 TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);
373 sc->obfl_q_overrun = false;
374 tws_init_connect(sc, 1);
376 /* Teardown the state in our softc created in our attach routine. */
377 /* Disconnect the interrupt handler. */
378 tws_teardown_intr(sc);
380 /* Release irq resource */
381 for(i=0;i<sc->irqs;i++) {
382 if ( sc->irq_res[i] ){
383 if (bus_release_resource(sc->tws_dev,
384 SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
385 TWS_TRACE(sc, "bus release irq resource",
386 i, sc->irq_res_id[i]);
389 if ( sc->intr_type == TWS_MSI ) {
390 pci_release_msi(sc->tws_dev);
395 if (sc->dma_mem_phys)
396 bus_dmamap_unload(sc->cmd_tag, sc->cmd_map);
398 bus_dmamem_free(sc->cmd_tag, sc->dma_mem, sc->cmd_map);
400 bus_dma_tag_destroy(sc->cmd_tag);
402 /* Release memory resource */
404 if (bus_release_resource(sc->tws_dev,
405 SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
406 TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id);
409 if (bus_release_resource(sc->tws_dev,
410 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
411 TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id);
414 for ( i=0; i< tws_queue_depth; i++) {
415 if (sc->reqs[i].dma_map)
416 bus_dmamap_destroy(sc->data_tag, sc->reqs[i].dma_map);
417 callout_drain(&sc->reqs[i].timeout);
420 callout_drain(&sc->stats_timer);
421 free(sc->reqs, M_TWS);
422 free(sc->sense_bufs, M_TWS);
423 free(sc->scan_ccb, M_TWS);
424 if (sc->ioctl_data_mem)
425 bus_dmamem_free(sc->data_tag, sc->ioctl_data_mem, sc->ioctl_data_map);
427 bus_dma_tag_destroy(sc->data_tag);
428 free(sc->aen_q.q, M_TWS);
429 free(sc->trace_q.q, M_TWS);
430 mtx_destroy(&sc->q_lock);
431 mtx_destroy(&sc->sim_lock);
432 mtx_destroy(&sc->gen_lock);
433 mtx_destroy(&sc->io_lock);
434 destroy_dev(sc->tws_cdev);
435 sysctl_ctx_free(&sc->tws_clist);
440 tws_setup_intr(struct tws_softc *sc, int irqs)
444 for(i=0;i<irqs;i++) {
445 if (!(sc->intr_handle[i])) {
446 if ((error = bus_setup_intr(sc->tws_dev, sc->irq_res[i],
447 INTR_TYPE_CAM | INTR_MPSAFE,
449 tws_intr, sc, &sc->intr_handle[i]))) {
450 tws_log(sc, SETUP_INTR_RES);
461 tws_teardown_intr(struct tws_softc *sc)
465 for(i=0;i<sc->irqs;i++) {
466 if (sc->intr_handle[i]) {
467 error = bus_teardown_intr(sc->tws_dev,
468 sc->irq_res[i], sc->intr_handle[i]);
469 sc->intr_handle[i] = NULL;
477 tws_setup_irq(struct tws_softc *sc)
481 switch(sc->intr_type) {
484 sc->irq_res_id[0] = 0;
485 sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
486 &sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
487 if ( ! sc->irq_res[0] )
489 if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
491 device_printf(sc->tws_dev, "Using legacy INTx\n");
495 sc->irq_res_id[0] = 1;
497 if (pci_alloc_msi(sc->tws_dev, &messages) != 0 ) {
498 TWS_TRACE(sc, "pci alloc msi fail", 0, messages);
501 sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
502 &sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
504 if ( !sc->irq_res[0] )
506 if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
508 device_printf(sc->tws_dev, "Using MSI\n");
517 tws_init(struct tws_softc *sc)
520 u_int32_t max_sg_elements;
521 u_int32_t dma_mem_size;
526 if ( tws_queue_depth > TWS_MAX_REQS )
527 tws_queue_depth = TWS_MAX_REQS;
528 if (tws_queue_depth < TWS_RESERVED_REQS+1)
529 tws_queue_depth = TWS_RESERVED_REQS+1;
530 sc->is64bit = (sizeof(bus_addr_t) == 8) ? true : false;
531 max_sg_elements = (sc->is64bit && !tws_use_32bit_sgls) ?
532 TWS_MAX_64BIT_SG_ELEMENTS :
533 TWS_MAX_32BIT_SG_ELEMENTS;
534 dma_mem_size = (sizeof(struct tws_command_packet) * tws_queue_depth) +
536 if ( bus_dma_tag_create(bus_get_dma_tag(sc->tws_dev), /* PCI parent */
537 TWS_ALIGNMENT, /* alignment */
539 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
540 BUS_SPACE_MAXADDR, /* highaddr */
541 NULL, NULL, /* filter, filterarg */
542 BUS_SPACE_MAXSIZE, /* maxsize */
543 max_sg_elements, /* numsegs */
544 BUS_SPACE_MAXSIZE, /* maxsegsize */
546 NULL, NULL, /* lockfunc, lockfuncarg */
547 &sc->parent_tag /* tag */
549 TWS_TRACE_DEBUG(sc, "DMA parent tag Create fail", max_sg_elements,
553 /* In bound message frame requires 16byte alignment.
554 * Outbound MF's can live with 4byte alignment - for now just
557 if ( bus_dma_tag_create(sc->parent_tag, /* parent */
558 TWS_IN_MF_ALIGNMENT, /* alignment */
560 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
561 BUS_SPACE_MAXADDR, /* highaddr */
562 NULL, NULL, /* filter, filterarg */
563 dma_mem_size, /* maxsize */
565 BUS_SPACE_MAXSIZE, /* maxsegsize */
567 NULL, NULL, /* lockfunc, lockfuncarg */
568 &sc->cmd_tag /* tag */
570 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
574 if (bus_dmamem_alloc(sc->cmd_tag, &sc->dma_mem,
575 BUS_DMA_NOWAIT, &sc->cmd_map)) {
576 TWS_TRACE_DEBUG(sc, "DMA mem alloc fail", max_sg_elements, sc->is64bit);
580 /* if bus_dmamem_alloc succeeds then bus_dmamap_load will succeed */
582 error = bus_dmamap_load(sc->cmd_tag, sc->cmd_map, sc->dma_mem,
583 dma_mem_size, tws_dmamap_cmds_load_cbfn,
584 &sc->dma_mem_phys, 0);
587 * Create a dma tag for data buffers; size will be the maximum
588 * possible I/O size (128kB).
590 if (bus_dma_tag_create(sc->parent_tag, /* parent */
591 TWS_ALIGNMENT, /* alignment */
593 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
594 BUS_SPACE_MAXADDR, /* highaddr */
595 NULL, NULL, /* filter, filterarg */
596 TWS_MAX_IO_SIZE, /* maxsize */
597 max_sg_elements, /* nsegments */
598 TWS_MAX_IO_SIZE, /* maxsegsize */
599 BUS_DMA_ALLOCNOW, /* flags */
600 busdma_lock_mutex, /* lockfunc */
601 &sc->io_lock, /* lockfuncarg */
602 &sc->data_tag /* tag */)) {
603 TWS_TRACE_DEBUG(sc, "DMA cmd tag Create fail", max_sg_elements, sc->is64bit);
607 sc->reqs = malloc(sizeof(struct tws_request) * tws_queue_depth, M_TWS,
609 sc->sense_bufs = malloc(sizeof(struct tws_sense) * tws_queue_depth, M_TWS,
611 sc->scan_ccb = malloc(sizeof(union ccb), M_TWS, M_WAITOK | M_ZERO);
612 if (bus_dmamem_alloc(sc->data_tag, (void **)&sc->ioctl_data_mem,
613 (BUS_DMA_NOWAIT | BUS_DMA_ZERO), &sc->ioctl_data_map)) {
614 device_printf(sc->tws_dev, "Cannot allocate ioctl data mem\n");
618 if ( !tws_ctlr_ready(sc) )
619 if( !tws_ctlr_reset(sc) )
622 bzero(&sc->stats, sizeof(struct tws_stats));
624 tws_turn_off_interrupts(sc);
627 * enable pull mode by setting bit1 .
628 * setting bit0 to 1 will enable interrupt coalesing
632 #ifdef TWS_PULL_MODE_ENABLE
634 reg = tws_read_reg(sc, TWS_I2O0_CTL, 4);
635 TWS_TRACE_DEBUG(sc, "i20 ctl", reg, TWS_I2O0_CTL);
636 tws_write_reg(sc, TWS_I2O0_CTL, reg | TWS_BIT1, 4);
640 TWS_TRACE_DEBUG(sc, "dma_mem_phys", sc->dma_mem_phys, TWS_I2O0_CTL);
641 if ( tws_init_reqs(sc, dma_mem_size) == FAILURE )
643 if ( tws_init_aen_q(sc) == FAILURE )
651 tws_init_aen_q(struct tws_softc *sc)
656 sc->aen_q.overflow=0;
657 sc->aen_q.q = malloc(sizeof(struct tws_event_packet)*sc->aen_q.depth,
658 M_TWS, M_WAITOK | M_ZERO);
663 tws_init_trace_q(struct tws_softc *sc)
667 sc->trace_q.depth=256;
668 sc->trace_q.overflow=0;
669 sc->trace_q.q = malloc(sizeof(struct tws_trace_rec)*sc->trace_q.depth,
670 M_TWS, M_WAITOK | M_ZERO);
675 tws_init_reqs(struct tws_softc *sc, u_int32_t dma_mem_size)
678 struct tws_command_packet *cmd_buf;
679 cmd_buf = (struct tws_command_packet *)sc->dma_mem;
682 bzero(cmd_buf, dma_mem_size);
683 TWS_TRACE_DEBUG(sc, "phy cmd", sc->dma_mem_phys, 0);
684 mtx_lock(&sc->q_lock);
685 for ( i=0; i< tws_queue_depth; i++)
687 if (bus_dmamap_create(sc->data_tag, 0, &sc->reqs[i].dma_map)) {
688 /* log a ENOMEM failure msg here */
689 mtx_unlock(&sc->q_lock);
692 sc->reqs[i].cmd_pkt = &cmd_buf[i];
694 sc->sense_bufs[i].hdr = &cmd_buf[i].hdr ;
695 sc->sense_bufs[i].hdr_pkt_phy = sc->dma_mem_phys +
696 (i * sizeof(struct tws_command_packet));
698 sc->reqs[i].cmd_pkt_phy = sc->dma_mem_phys +
699 sizeof(struct tws_command_header) +
700 (i * sizeof(struct tws_command_packet));
701 sc->reqs[i].request_id = i;
704 sc->reqs[i].cmd_pkt->hdr.header_desc.size_header = 128;
706 callout_init(&sc->reqs[i].timeout, 1);
707 sc->reqs[i].state = TWS_REQ_STATE_FREE;
708 if ( i >= TWS_RESERVED_REQS )
709 tws_q_insert_tail(sc, &sc->reqs[i], TWS_FREE_Q);
711 mtx_unlock(&sc->q_lock);
716 tws_dmamap_cmds_load_cbfn(void *arg, bus_dma_segment_t *segs,
720 /* printf("command load done \n"); */
722 *((bus_addr_t *)arg) = segs[0].ds_addr;
726 tws_send_event(struct tws_softc *sc, u_int8_t event)
728 mtx_assert(&sc->gen_lock, MA_OWNED);
729 TWS_TRACE_DEBUG(sc, "received event ", 0, event);
733 sc->tws_state = TWS_INIT;
736 case TWS_INIT_COMPLETE:
737 if (sc->tws_state != TWS_INIT) {
738 device_printf(sc->tws_dev, "invalid state transition %d => TWS_ONLINE\n", sc->tws_state);
740 sc->tws_state = TWS_ONLINE;
744 case TWS_RESET_START:
745 /* We can transition to reset state from any state except reset*/
746 if (sc->tws_state != TWS_RESET) {
747 sc->tws_prev_state = sc->tws_state;
748 sc->tws_state = TWS_RESET;
752 case TWS_RESET_COMPLETE:
753 if (sc->tws_state != TWS_RESET) {
754 device_printf(sc->tws_dev, "invalid state transition %d => %d (previous state)\n", sc->tws_state, sc->tws_prev_state);
756 sc->tws_state = sc->tws_prev_state;
760 case TWS_SCAN_FAILURE:
761 if (sc->tws_state != TWS_ONLINE) {
762 device_printf(sc->tws_dev, "invalid state transition %d => TWS_OFFLINE\n", sc->tws_state);
764 sc->tws_state = TWS_OFFLINE;
768 case TWS_UNINIT_START:
769 if ((sc->tws_state != TWS_ONLINE) && (sc->tws_state != TWS_OFFLINE)) {
770 device_printf(sc->tws_dev, "invalid state transition %d => TWS_UNINIT\n", sc->tws_state);
772 sc->tws_state = TWS_UNINIT;
780 tws_get_state(struct tws_softc *sc)
783 return((u_int8_t)sc->tws_state);
787 /* Called during system shutdown after sync. */
790 tws_shutdown(device_t dev)
793 struct tws_softc *sc = device_get_softc(dev);
795 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
797 tws_turn_off_interrupts(sc);
798 tws_init_connect(sc, 1);
804 * Device suspend routine.
807 tws_suspend(device_t dev)
809 struct tws_softc *sc = device_get_softc(dev);
812 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
817 * Device resume routine.
820 tws_resume(device_t dev)
823 struct tws_softc *sc = device_get_softc(dev);
826 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
832 tws_get_request(struct tws_softc *sc, u_int16_t type)
834 struct mtx *my_mutex = ((type == TWS_REQ_TYPE_SCSI_IO) ? &sc->q_lock : &sc->gen_lock);
835 struct tws_request *r = NULL;
839 if (type == TWS_REQ_TYPE_SCSI_IO) {
840 r = tws_q_remove_head(sc, TWS_FREE_Q);
842 if ( sc->reqs[type].state == TWS_REQ_STATE_FREE ) {
848 bzero(&r->cmd_pkt->cmd, sizeof(struct tws_command_apache));
852 r->flags = TWS_DIR_UNKNOWN;
853 r->error_code = TWS_REQ_RET_INVALID;
856 callout_stop(&r->timeout);
857 r->next = r->prev = NULL;
859 r->state = ((type == TWS_REQ_TYPE_SCSI_IO) ? TWS_REQ_STATE_TRAN : TWS_REQ_STATE_BUSY);
862 mtx_unlock(my_mutex);
868 tws_release_request(struct tws_request *req)
871 struct tws_softc *sc = req->sc;
873 TWS_TRACE_DEBUG(sc, "entry", sc, 0);
874 mtx_lock(&sc->q_lock);
875 tws_q_insert_tail(sc, req, TWS_FREE_Q);
876 mtx_unlock(&sc->q_lock);
879 static device_method_t tws_methods[] = {
880 /* Device interface */
881 DEVMETHOD(device_probe, tws_probe),
882 DEVMETHOD(device_attach, tws_attach),
883 DEVMETHOD(device_detach, tws_detach),
884 DEVMETHOD(device_shutdown, tws_shutdown),
885 DEVMETHOD(device_suspend, tws_suspend),
886 DEVMETHOD(device_resume, tws_resume),
891 static driver_t tws_driver = {
894 sizeof(struct tws_softc)
898 static devclass_t tws_devclass;
900 /* DEFINE_CLASS_0(tws, tws_driver, tws_methods, sizeof(struct tws_softc)); */
901 DRIVER_MODULE(tws, pci, tws_driver, tws_devclass, 0, 0);
902 MODULE_DEPEND(tws, cam, 1, 1, 1);
903 MODULE_DEPEND(tws, pci, 1, 1, 1);
905 TUNABLE_INT("hw.tws.queue_depth", &tws_queue_depth);
906 TUNABLE_INT("hw.tws.enable_msi", &tws_enable_msi);