2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
61 #include <net/if_vlan_var.h>
63 #include <machine/bus.h>
64 #include <machine/resource.h>
68 #include <dev/pci/pcireg.h>
69 #include <dev/pci/pcivar.h>
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
75 #include <dev/mii/lxtphyreg.h>
77 #include "miibus_if.h"
79 #include <dev/tx/if_txreg.h>
80 #include <dev/tx/if_txvar.h>
82 MODULE_DEPEND(tx, pci, 1, 1, 1);
83 MODULE_DEPEND(tx, ether, 1, 1, 1);
84 MODULE_DEPEND(tx, miibus, 1, 1, 1);
86 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
87 static void epic_intr(void *);
88 static void epic_tx_underrun(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifstart_locked(struct ifnet *);
91 static void epic_timer(void *);
92 static void epic_init(void *);
93 static void epic_init_locked(epic_softc_t *);
94 static void epic_stop(epic_softc_t *);
95 static void epic_rx_done(epic_softc_t *);
96 static void epic_tx_done(epic_softc_t *);
97 static int epic_init_rings(epic_softc_t *);
98 static void epic_free_rings(epic_softc_t *);
99 static void epic_stop_activity(epic_softc_t *);
100 static int epic_queue_last_packet(epic_softc_t *);
101 static void epic_start_activity(epic_softc_t *);
102 static void epic_set_rx_mode(epic_softc_t *);
103 static void epic_set_tx_mode(epic_softc_t *);
104 static void epic_set_mc_table(epic_softc_t *);
105 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
106 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
107 static u_int16_t epic_input_eepromw(epic_softc_t *);
108 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
109 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
110 static u_int8_t epic_read_eepromreg(epic_softc_t *);
112 static int epic_read_phy_reg(epic_softc_t *, int, int);
113 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
115 static int epic_miibus_readreg(device_t, int, int);
116 static int epic_miibus_writereg(device_t, int, int, int);
117 static void epic_miibus_statchg(device_t);
118 static void epic_miibus_mediainit(device_t);
120 static int epic_ifmedia_upd(struct ifnet *);
121 static int epic_ifmedia_upd_locked(struct ifnet *);
122 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
124 static int epic_probe(device_t);
125 static int epic_attach(device_t);
126 static int epic_shutdown(device_t);
127 static int epic_detach(device_t);
128 static void epic_release(epic_softc_t *);
129 static struct epic_type *epic_devtype(device_t);
131 static device_method_t epic_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, epic_probe),
134 DEVMETHOD(device_attach, epic_attach),
135 DEVMETHOD(device_detach, epic_detach),
136 DEVMETHOD(device_shutdown, epic_shutdown),
139 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
140 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
141 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
142 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
147 static driver_t epic_driver = {
153 static devclass_t epic_devclass;
155 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0);
156 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
158 static struct epic_type epic_devs[] = {
159 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" },
164 epic_probe(device_t dev)
168 t = epic_devtype(dev);
171 device_set_desc(dev, t->name);
172 return (BUS_PROBE_DEFAULT);
178 static struct epic_type *
179 epic_devtype(device_t dev)
185 while (t->name != NULL) {
186 if ((pci_get_vendor(dev) == t->ven_id) &&
187 (pci_get_device(dev) == t->dev_id)) {
195 #ifdef EPIC_USEIOSPACE
196 #define EPIC_RES SYS_RES_IOPORT
197 #define EPIC_RID PCIR_BASEIO
199 #define EPIC_RES SYS_RES_MEMORY
200 #define EPIC_RID PCIR_BASEMEM
204 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
211 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
213 *addr = segs->ds_addr;
217 * Attach routine: map registers, allocate softc, rings and descriptors.
218 * Reset to known state.
221 epic_attach(device_t dev)
229 sc = device_get_softc(dev);
231 /* Preinitialize softc structure. */
233 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
236 /* Fill ifnet structure. */
237 ifp = sc->ifp = if_alloc(IFT_ETHER);
239 device_printf(dev, "can not if_alloc()\n");
243 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
245 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
246 ifp->if_ioctl = epic_ifioctl;
247 ifp->if_start = epic_ifstart;
248 ifp->if_init = epic_init;
249 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
251 /* Enable busmastering. */
252 pci_enable_busmaster(dev);
255 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
256 if (sc->res == NULL) {
257 device_printf(dev, "couldn't map ports/memory\n");
262 /* Allocate interrupt. */
264 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
265 RF_SHAREABLE | RF_ACTIVE);
266 if (sc->irq == NULL) {
267 device_printf(dev, "couldn't map interrupt\n");
272 /* Allocate DMA tags. */
273 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
274 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
275 MCLBYTES * EPIC_MAX_FRAGS, EPIC_MAX_FRAGS, MCLBYTES, 0, NULL, NULL,
278 device_printf(dev, "couldn't allocate dma tag\n");
282 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
283 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
284 sizeof(struct epic_rx_desc) * RX_RING_SIZE,
285 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, NULL,
288 device_printf(dev, "couldn't allocate dma tag\n");
292 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
293 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
294 sizeof(struct epic_tx_desc) * TX_RING_SIZE,
295 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0,
296 NULL, NULL, &sc->ttag);
298 device_printf(dev, "couldn't allocate dma tag\n");
302 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
303 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
304 sizeof(struct epic_frag_list) * TX_RING_SIZE,
305 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0,
306 NULL, NULL, &sc->ftag);
308 device_printf(dev, "couldn't allocate dma tag\n");
312 /* Allocate DMA safe memory and get the DMA addresses. */
313 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist,
314 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap);
316 device_printf(dev, "couldn't allocate dma memory\n");
319 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist,
320 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr,
323 device_printf(dev, "couldn't map dma memory\n");
326 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
327 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap);
329 device_printf(dev, "couldn't allocate dma memory\n");
332 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
333 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr,
336 device_printf(dev, "couldn't map dma memory\n");
339 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
340 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap);
342 device_printf(dev, "couldn't allocate dma memory\n");
345 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
346 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr,
349 device_printf(dev, "couldn't map dma memory\n");
353 /* Bring the chip out of low-power mode. */
354 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
357 /* Workaround for Application Note 7-15. */
358 for (i = 0; i < 16; i++)
359 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
361 /* Read MAC address from EEPROM. */
362 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
363 ((u_int16_t *)eaddr)[i] = epic_read_eeprom(sc,i);
365 /* Set Non-Volatile Control Register from EEPROM. */
366 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
369 sc->tx_threshold = TRANSMIT_THRESHOLD;
370 sc->txcon = TXCON_DEFAULT;
371 sc->miicfg = MIICFG_SMI_ENABLE;
372 sc->phyid = EPIC_UNKN_PHY;
376 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2);
377 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2);
379 if (sc->cardvend != SMC_VENDORID)
380 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend);
382 /* Do ifmedia setup. */
383 error = mii_attach(dev, &sc->miibus, ifp, epic_ifmedia_upd,
384 epic_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
386 device_printf(dev, "attaching PHYs failed\n");
390 /* board type and ... */
392 for(i = 0x2c; i < 0x32; i++) {
393 tmp = epic_read_eeprom(sc, i);
394 if (' ' == (u_int8_t)tmp)
396 printf("%c", (u_int8_t)tmp);
398 if (' ' == (u_int8_t)tmp)
400 printf("%c", (u_int8_t)tmp);
404 /* Initialize rings. */
405 if (epic_init_rings(sc)) {
406 device_printf(dev, "failed to init rings\n");
411 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
412 ifp->if_capabilities |= IFCAP_VLAN_MTU;
413 ifp->if_capenable |= IFCAP_VLAN_MTU;
414 callout_init_mtx(&sc->timer, &sc->lock, 0);
416 /* Attach to OS's managers. */
417 ether_ifattach(ifp, eaddr);
419 /* Activate our interrupt handler. */
420 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
421 NULL, epic_intr, sc, &sc->sc_ih);
423 device_printf(dev, "couldn't set up irq\n");
435 * Free any resources allocated by the driver.
438 epic_release(epic_softc_t *sc)
443 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
445 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res);
448 bus_dmamap_unload(sc->ftag, sc->fmap);
449 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap);
452 bus_dmamap_unload(sc->ttag, sc->tmap);
453 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap);
456 bus_dmamap_unload(sc->rtag, sc->rmap);
457 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
460 bus_dma_tag_destroy(sc->mtag);
462 bus_dma_tag_destroy(sc->ftag);
464 bus_dma_tag_destroy(sc->ttag);
466 bus_dma_tag_destroy(sc->rtag);
467 mtx_destroy(&sc->lock);
471 * Detach driver and free resources.
474 epic_detach(device_t dev)
479 sc = device_get_softc(dev);
485 callout_drain(&sc->timer);
487 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
489 bus_generic_detach(dev);
490 device_delete_child(dev, sc->miibus);
500 * Stop all chip I/O so that the kernel's probe routines don't
501 * get confused by errant DMAs when rebooting.
504 epic_shutdown(device_t dev)
508 sc = device_get_softc(dev);
517 * This is if_ioctl handler.
520 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data)
522 epic_softc_t *sc = ifp->if_softc;
523 struct mii_data *mii;
524 struct ifreq *ifr = (struct ifreq *) data;
529 if (ifp->if_mtu == ifr->ifr_mtu)
532 /* XXX Though the datasheet doesn't imply any
533 * limitations on RX and TX sizes beside max 64Kb
534 * DMA transfer, seems we can't send more then 1600
535 * data bytes per ethernet packet (transmitter hangs
536 * up if more data is sent).
539 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
540 ifp->if_mtu = ifr->ifr_mtu;
542 epic_init_locked(sc);
550 * If the interface is marked up and stopped, then start it.
551 * If it is marked down and running, then stop it.
554 if (ifp->if_flags & IFF_UP) {
555 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
556 epic_init_locked(sc);
561 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
568 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
569 epic_stop_activity(sc);
570 epic_set_mc_table(sc);
571 epic_set_rx_mode(sc);
572 epic_start_activity(sc);
579 epic_set_mc_table(sc);
586 mii = device_get_softc(sc->miibus);
587 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
591 error = ether_ioctl(ifp, command, data);
598 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
599 bus_size_t mapsize, int error)
601 struct epic_frag_list *flist;
607 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments"));
609 /* Fill fragments list. */
610 for (i = 0; i < nseg; i++) {
611 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
612 flist->frag[i].fraglen = segs[i].ds_len;
613 flist->frag[i].fragaddr = segs[i].ds_addr;
615 flist->numfrags = nseg;
619 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
620 bus_size_t mapsize, int error)
622 struct epic_rx_desc *desc;
627 KASSERT(nseg == 1, ("too many DMA segments"));
629 desc->bufaddr = segs->ds_addr;
633 * This is if_start handler. It takes mbufs from if_snd queue
634 * and queue them for transmit, one by one, until TX ring become full
635 * or queue become empty.
638 epic_ifstart(struct ifnet * ifp)
640 epic_softc_t *sc = ifp->if_softc;
643 epic_ifstart_locked(ifp);
648 epic_ifstart_locked(struct ifnet * ifp)
650 epic_softc_t *sc = ifp->if_softc;
651 struct epic_tx_buffer *buf;
652 struct epic_tx_desc *desc;
653 struct epic_frag_list *flist;
657 while (sc->pending_txs < TX_RING_SIZE) {
658 buf = sc->tx_buffer + sc->cur_tx;
659 desc = sc->tx_desc + sc->cur_tx;
660 flist = sc->tx_flist + sc->cur_tx;
662 /* Get next packet to send. */
663 IF_DEQUEUE(&ifp->if_snd, m0);
665 /* If nothing to send, return. */
669 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
670 epic_dma_map_txbuf, flist, 0);
672 if (error && error != EFBIG) {
674 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
679 * If packet was more than EPIC_MAX_FRAGS parts,
680 * recopy packet to a newly allocated mbuf cluster.
683 m = m_defrag(m0, M_NOWAIT);
686 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
692 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
693 epic_dma_map_txbuf, flist, 0);
696 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
700 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
704 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
705 desc->control = 0x01;
707 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
708 desc->status = 0x8000;
709 bus_dmamap_sync(sc->ttag, sc->tmap,
710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
711 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
712 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
714 /* Set watchdog timer. */
720 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
724 * Synopsis: Finish all received frames.
727 epic_rx_done(epic_softc_t *sc)
729 struct ifnet *ifp = sc->ifp;
731 struct epic_rx_buffer *buf;
732 struct epic_rx_desc *desc;
737 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD);
738 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
739 buf = sc->rx_buffer + sc->cur_rx;
740 desc = sc->rx_desc + sc->cur_rx;
742 /* Switch to next descriptor. */
743 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK;
746 * Check for RX errors. This should only happen if
747 * SAVE_ERRORED_PACKETS is set. RX errors generate
748 * RXE interrupt usually.
750 if ((desc->status & 1) == 0) {
751 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
752 desc->status = 0x8000;
756 /* Save packet length and mbuf contained packet. */
757 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
758 len = desc->rxlength - ETHER_CRC_LEN;
761 /* Try to get an mbuf cluster. */
762 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
763 if (buf->mbuf == NULL) {
765 desc->status = 0x8000;
766 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
769 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
770 m_adj(buf->mbuf, ETHER_ALIGN);
772 /* Point to new mbuf, and give descriptor to chip. */
773 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf,
774 epic_dma_map_rxbuf, desc, 0);
777 desc->status = 0x8000;
778 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
782 desc->status = 0x8000;
783 bus_dmamap_unload(sc->mtag, buf->map);
785 buf->map = sc->sparemap;
787 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
789 /* First mbuf in packet holds the ethernet and packet headers */
790 m->m_pkthdr.rcvif = ifp;
791 m->m_pkthdr.len = m->m_len = len;
793 /* Give mbuf to OS. */
795 (*ifp->if_input)(ifp, m);
798 /* Successfuly received frame */
799 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
801 bus_dmamap_sync(sc->rtag, sc->rmap,
802 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
806 * Synopsis: Do last phase of transmission. I.e. if desc is
807 * transmitted, decrease pending_txs counter, free mbuf contained
808 * packet, switch to next descriptor and repeat until no packets
809 * are pending or descriptor is not transmitted yet.
812 epic_tx_done(epic_softc_t *sc)
814 struct epic_tx_buffer *buf;
815 struct epic_tx_desc *desc;
818 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD);
819 while (sc->pending_txs > 0) {
820 buf = sc->tx_buffer + sc->dirty_tx;
821 desc = sc->tx_desc + sc->dirty_tx;
822 status = desc->status;
825 * If packet is not transmitted, thou followed
826 * packets are not transmitted too.
831 /* Packet is transmitted. Switch to next and free mbuf. */
833 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
834 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
835 bus_dmamap_unload(sc->mtag, buf->map);
839 /* Check for errors and collisions. */
841 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
843 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
844 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, (status >> 8) & 0x1F);
846 if ((status & 0x1001) == 0x1001)
847 device_printf(sc->dev,
848 "Tx ERROR: excessive coll. number\n");
852 if (sc->pending_txs < TX_RING_SIZE)
853 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
854 bus_dmamap_sync(sc->ttag, sc->tmap,
855 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
870 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
871 CSR_WRITE_4(sc, INTSTAT, status);
873 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
875 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
877 if (status & INTSTAT_OVW)
878 device_printf(sc->dev, "RX buffer overflow\n");
879 if (status & INTSTAT_RQE)
880 device_printf(sc->dev, "RX FIFO overflow\n");
882 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
883 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
884 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
888 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
890 if (sc->ifp->if_snd.ifq_head != NULL)
891 epic_ifstart_locked(sc->ifp);
894 /* Check for rare errors */
895 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
896 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
897 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
898 INTSTAT_APE|INTSTAT_DPE)) {
899 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
900 (status & INTSTAT_PMA) ? "PMA " : "",
901 (status & INTSTAT_PTA) ? "PTA " : "",
902 (status & INTSTAT_APE) ? "APE " : "",
903 (status & INTSTAT_DPE) ? "DPE" : "");
906 epic_init_locked(sc);
910 if (status & INTSTAT_RXE) {
912 device_printf(sc->dev, "CRC/Alignment error\n");
914 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
917 if (status & INTSTAT_TXU) {
918 epic_tx_underrun(sc);
919 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
924 /* If no packets are pending, then no timeouts. */
925 if (sc->pending_txs == 0)
931 * Handle the TX underrun error: increase the TX threshold
932 * and restart the transmitter.
935 epic_tx_underrun(epic_softc_t *sc)
937 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
938 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
940 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
943 sc->tx_threshold += 0x40;
945 device_printf(sc->dev,
946 "Tx UNDERRUN: TX threshold increased to %d\n",
951 /* We must set TXUGO to reset the stuck transmitter. */
952 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
954 /* Update the TX threshold */
955 epic_stop_activity(sc);
956 epic_set_tx_mode(sc);
957 epic_start_activity(sc);
961 * This function is called once a second when the interface is running
962 * and performs two functions. First, it provides a timer for the mii
963 * to help with autonegotiation. Second, it checks for transmit
967 epic_timer(void *arg)
969 epic_softc_t *sc = arg;
970 struct mii_data *mii;
974 EPIC_ASSERT_LOCKED(sc);
975 if (sc->tx_timeout && --sc->tx_timeout == 0) {
976 device_printf(sc->dev, "device timeout %d packets\n",
979 /* Try to finish queued packets. */
982 /* If not successful. */
983 if (sc->pending_txs > 0) {
984 if_inc_counter(ifp, IFCOUNTER_OERRORS, sc->pending_txs);
986 /* Reinitialize board. */
987 device_printf(sc->dev, "reinitialization\n");
989 epic_init_locked(sc);
991 device_printf(sc->dev,
992 "seems we can continue normaly\n");
995 if (ifp->if_snd.ifq_head)
996 epic_ifstart_locked(ifp);
999 mii = device_get_softc(sc->miibus);
1002 callout_reset(&sc->timer, hz, epic_timer, sc);
1006 * Set media options.
1009 epic_ifmedia_upd(struct ifnet *ifp)
1016 error = epic_ifmedia_upd_locked(ifp);
1022 epic_ifmedia_upd_locked(struct ifnet *ifp)
1025 struct mii_data *mii;
1026 struct ifmedia *ifm;
1027 struct mii_softc *miisc;
1031 mii = device_get_softc(sc->miibus);
1032 ifm = &mii->mii_media;
1033 media = ifm->ifm_cur->ifm_media;
1035 /* Do not do anything if interface is not up. */
1036 if ((ifp->if_flags & IFF_UP) == 0)
1040 * Lookup current selected PHY.
1042 if (IFM_INST(media) == sc->serinst) {
1043 sc->phyid = EPIC_SERIAL;
1046 /* If we're not selecting serial interface, select MII mode. */
1047 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1048 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1050 /* Default to unknown PHY. */
1051 sc->phyid = EPIC_UNKN_PHY;
1053 /* Lookup selected PHY. */
1054 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1055 if (IFM_INST(media) == miisc->mii_inst) {
1061 /* Identify selected PHY. */
1063 int id1, id2, model, oui;
1065 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1066 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1068 oui = MII_OUI(id1, id2);
1069 model = MII_MODEL(id2);
1071 case MII_OUI_xxQUALSEMI:
1072 if (model == MII_MODEL_xxQUALSEMI_QS6612)
1073 sc->phyid = EPIC_QS6612_PHY;
1075 case MII_OUI_ALTIMA:
1076 if (model == MII_MODEL_ALTIMA_AC101)
1077 sc->phyid = EPIC_AC101_PHY;
1079 case MII_OUI_xxLEVEL1:
1080 if (model == MII_MODEL_xxLEVEL1_LXT970)
1081 sc->phyid = EPIC_LXT970_PHY;
1088 * Do PHY specific card setup.
1092 * Call this, to isolate all not selected PHYs and
1097 /* Do our own setup. */
1098 switch (sc->phyid) {
1099 case EPIC_QS6612_PHY:
1101 case EPIC_AC101_PHY:
1102 /* We have to powerup fiber tranceivers. */
1103 if (IFM_SUBTYPE(media) == IFM_100_FX)
1104 sc->miicfg |= MIICFG_694_ENABLE;
1106 sc->miicfg &= ~MIICFG_694_ENABLE;
1107 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1110 case EPIC_LXT970_PHY:
1111 /* We have to powerup fiber tranceivers. */
1112 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1113 if (IFM_SUBTYPE(media) == IFM_100_FX)
1114 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1116 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1117 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1121 /* Select serial PHY (10base2/BNC usually). */
1122 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1123 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1125 /* There is no driver to fill this. */
1126 mii->mii_media_active = media;
1127 mii->mii_media_status = 0;
1130 * We need to call this manually as it wasn't called
1131 * in mii_mediachg().
1133 epic_miibus_statchg(sc->dev);
1136 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1144 * Report current media status.
1147 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1150 struct mii_data *mii;
1153 mii = device_get_softc(sc->miibus);
1156 /* Nothing should be selected if interface is down. */
1157 if ((ifp->if_flags & IFF_UP) == 0) {
1158 ifmr->ifm_active = IFM_NONE;
1159 ifmr->ifm_status = 0;
1164 /* Call underlying pollstat, if not serial PHY. */
1165 if (sc->phyid != EPIC_SERIAL)
1168 /* Simply copy media info. */
1169 ifmr->ifm_active = mii->mii_media_active;
1170 ifmr->ifm_status = mii->mii_media_status;
1175 * Callback routine, called on media change.
1178 epic_miibus_statchg(device_t dev)
1181 struct mii_data *mii;
1184 sc = device_get_softc(dev);
1185 mii = device_get_softc(sc->miibus);
1186 media = mii->mii_media_active;
1188 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1191 * If we are in full-duplex mode or loopback operation,
1192 * we need to decouple receiver and transmitter.
1194 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1195 sc->txcon |= TXCON_FULL_DUPLEX;
1197 /* On some cards we need manualy set fullduplex led. */
1198 if (sc->cardid == SMC9432FTX ||
1199 sc->cardid == SMC9432FTX_SC) {
1200 if (IFM_OPTIONS(media) & IFM_FDX)
1201 sc->miicfg |= MIICFG_694_ENABLE;
1203 sc->miicfg &= ~MIICFG_694_ENABLE;
1205 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1208 epic_stop_activity(sc);
1209 epic_set_tx_mode(sc);
1210 epic_start_activity(sc);
1214 epic_miibus_mediainit(device_t dev)
1217 struct mii_data *mii;
1218 struct ifmedia *ifm;
1221 sc = device_get_softc(dev);
1222 mii = device_get_softc(sc->miibus);
1223 ifm = &mii->mii_media;
1226 * Add Serial Media Interface if present, this applies to
1229 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1230 /* Store its instance. */
1231 sc->serinst = mii->mii_instance++;
1233 /* Add as 10base2/BNC media. */
1234 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1235 ifmedia_add(ifm, media, 0, NULL);
1237 /* Report to user. */
1238 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1243 * Reset chip and update media.
1246 epic_init(void *xsc)
1248 epic_softc_t *sc = xsc;
1251 epic_init_locked(sc);
1256 epic_init_locked(epic_softc_t *sc)
1258 struct ifnet *ifp = sc->ifp;
1261 /* If interface is already running, then we need not do anything. */
1262 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1266 /* Soft reset the chip (we have to power up card before). */
1267 CSR_WRITE_4(sc, GENCTL, 0);
1268 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1271 * Reset takes 15 pci ticks which depends on PCI bus speed.
1272 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1277 CSR_WRITE_4(sc, GENCTL, 0);
1279 /* Workaround for Application Note 7-15 */
1280 for (i = 0; i < 16; i++)
1281 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1283 /* Give rings to EPIC */
1284 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1285 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1287 /* Put node address to EPIC. */
1288 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IF_LLADDR(sc->ifp))[0]);
1289 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IF_LLADDR(sc->ifp))[1]);
1290 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IF_LLADDR(sc->ifp))[2]);
1292 /* Set tx mode, includeing transmit threshold. */
1293 epic_set_tx_mode(sc);
1295 /* Compute and set RXCON. */
1296 epic_set_rx_mode(sc);
1298 /* Set multicast table. */
1299 epic_set_mc_table(sc);
1301 /* Enable interrupts by setting the interrupt mask. */
1302 CSR_WRITE_4(sc, INTMASK,
1303 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1304 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1307 /* Acknowledge all pending interrupts. */
1308 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1310 /* Enable interrupts, set for PCI read multiple and etc */
1311 CSR_WRITE_4(sc, GENCTL,
1312 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1313 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1315 /* Mark interface running ... */
1316 if (ifp->if_flags & IFF_UP)
1317 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1319 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1322 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1324 /* Start Rx process */
1325 epic_start_activity(sc);
1327 /* Set appropriate media */
1328 epic_ifmedia_upd_locked(ifp);
1330 callout_reset(&sc->timer, hz, epic_timer, sc);
1334 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1338 epic_set_rx_mode(epic_softc_t *sc)
1343 flags = sc->ifp->if_flags;
1344 rxcon = RXCON_DEFAULT;
1346 #ifdef EPIC_EARLY_RX
1347 rxcon |= RXCON_EARLY_RX;
1350 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1352 CSR_WRITE_4(sc, RXCON, rxcon);
1356 * Synopsis: Set transmit control register. Chip must be in idle state to
1360 epic_set_tx_mode(epic_softc_t *sc)
1363 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1364 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1366 CSR_WRITE_4(sc, TXCON, sc->txcon);
1370 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1371 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch
1372 * individual frames, multicast filter must be manually programmed).
1374 * Note: EPIC must be in idle state.
1377 epic_set_mc_table(epic_softc_t *sc)
1380 struct ifmultiaddr *ifma;
1381 u_int16_t filter[4];
1385 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1386 CSR_WRITE_4(sc, MC0, 0xFFFF);
1387 CSR_WRITE_4(sc, MC1, 0xFFFF);
1388 CSR_WRITE_4(sc, MC2, 0xFFFF);
1389 CSR_WRITE_4(sc, MC3, 0xFFFF);
1398 if_maddr_rlock(ifp);
1399 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1400 if (ifma->ifma_addr->sa_family != AF_LINK)
1402 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1403 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1404 filter[h >> 4] |= 1 << (h & 0xF);
1406 if_maddr_runlock(ifp);
1408 CSR_WRITE_4(sc, MC0, filter[0]);
1409 CSR_WRITE_4(sc, MC1, filter[1]);
1410 CSR_WRITE_4(sc, MC2, filter[2]);
1411 CSR_WRITE_4(sc, MC3, filter[3]);
1416 * Synopsis: Start receive process and transmit one, if they need.
1419 epic_start_activity(epic_softc_t *sc)
1422 /* Start rx process. */
1423 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1424 (sc->pending_txs ? COMMAND_TXQUEUED : 0));
1428 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1429 * packet needs to be queued to stop Tx DMA.
1432 epic_stop_activity(epic_softc_t *sc)
1436 /* Stop Tx and Rx DMA. */
1437 CSR_WRITE_4(sc, COMMAND,
1438 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1440 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */
1441 for (i = 0; i < 0x1000; i++) {
1442 status = CSR_READ_4(sc, INTSTAT) &
1443 (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1444 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1449 /* Catch all finished packets. */
1453 status = CSR_READ_4(sc, INTSTAT);
1455 if ((status & INTSTAT_RXIDLE) == 0)
1456 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1458 if ((status & INTSTAT_TXIDLE) == 0)
1459 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1462 * May need to queue one more packet if TQE, this is rare
1463 * but existing case.
1465 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1466 (void)epic_queue_last_packet(sc);
1470 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1471 * a packet from current descriptor will be copied to internal RAM. We
1472 * compose a dummy packet here and queue it for transmission.
1474 * XXX the packet will then be actually sent over network...
1477 epic_queue_last_packet(epic_softc_t *sc)
1479 struct epic_tx_desc *desc;
1480 struct epic_frag_list *flist;
1481 struct epic_tx_buffer *buf;
1485 device_printf(sc->dev, "queue last packet\n");
1487 desc = sc->tx_desc + sc->cur_tx;
1488 flist = sc->tx_flist + sc->cur_tx;
1489 buf = sc->tx_buffer + sc->cur_tx;
1491 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1494 MGETHDR(m0, M_NOWAIT, MT_DATA);
1499 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN);
1500 m0->m_pkthdr.len = m0->m_len;
1501 m0->m_pkthdr.rcvif = sc->ifp;
1502 bzero(mtod(m0, caddr_t), m0->m_len);
1504 /* Fill fragments list. */
1505 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
1506 epic_dma_map_txbuf, flist, 0);
1511 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
1513 /* Fill in descriptor. */
1516 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1517 desc->control = 0x01;
1518 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
1519 desc->status = 0x8000;
1520 bus_dmamap_sync(sc->ttag, sc->tmap,
1521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1522 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1524 /* Launch transmission. */
1525 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1527 /* Wait Tx DMA to stop (for how long??? XXX) */
1528 for (i = 0; i < 1000; i++) {
1529 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1534 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1535 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1543 * Synopsis: Shut down board and deallocates rings.
1546 epic_stop(epic_softc_t *sc)
1549 EPIC_ASSERT_LOCKED(sc);
1552 callout_stop(&sc->timer);
1554 /* Disable interrupts */
1555 CSR_WRITE_4(sc, INTMASK, 0);
1556 CSR_WRITE_4(sc, GENCTL, 0);
1558 /* Try to stop Rx and TX processes */
1559 epic_stop_activity(sc);
1562 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1565 /* Make chip go to bed */
1566 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1568 /* Mark as stopped */
1569 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1573 * Synopsis: This function should free all memory allocated for rings.
1576 epic_free_rings(epic_softc_t *sc)
1580 for (i = 0; i < RX_RING_SIZE; i++) {
1581 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1582 struct epic_rx_desc *desc = sc->rx_desc + i;
1585 desc->buflength = 0;
1589 bus_dmamap_unload(sc->mtag, buf->map);
1590 bus_dmamap_destroy(sc->mtag, buf->map);
1596 if (sc->sparemap != NULL)
1597 bus_dmamap_destroy(sc->mtag, sc->sparemap);
1599 for (i = 0; i < TX_RING_SIZE; i++) {
1600 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1601 struct epic_tx_desc *desc = sc->tx_desc + i;
1604 desc->buflength = 0;
1608 bus_dmamap_unload(sc->mtag, buf->map);
1609 bus_dmamap_destroy(sc->mtag, buf->map);
1617 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1618 * Point Tx descs to fragment lists. Check that all descs and fraglists
1619 * are bounded and aligned properly.
1622 epic_init_rings(epic_softc_t *sc)
1626 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1628 /* Initialize the RX descriptor ring. */
1629 for (i = 0; i < RX_RING_SIZE; i++) {
1630 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1631 struct epic_rx_desc *desc = sc->rx_desc + i;
1633 desc->status = 0; /* Owned by driver */
1634 desc->next = sc->rx_addr +
1635 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc);
1637 if ((desc->next & 3) ||
1638 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1639 epic_free_rings(sc);
1643 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1644 if (buf->mbuf == NULL) {
1645 epic_free_rings(sc);
1648 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1649 m_adj(buf->mbuf, ETHER_ALIGN);
1651 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1653 epic_free_rings(sc);
1656 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1657 epic_dma_map_rxbuf, desc, 0);
1659 epic_free_rings(sc);
1662 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1664 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */
1665 desc->status = 0x8000; /* Set owner bit to NIC */
1667 bus_dmamap_sync(sc->rtag, sc->rmap,
1668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1670 /* Create the spare DMA map. */
1671 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap);
1673 epic_free_rings(sc);
1677 /* Initialize the TX descriptor ring. */
1678 for (i = 0; i < TX_RING_SIZE; i++) {
1679 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1680 struct epic_tx_desc *desc = sc->tx_desc + i;
1683 desc->next = sc->tx_addr +
1684 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc);
1686 if ((desc->next & 3) ||
1687 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1688 epic_free_rings(sc);
1693 desc->bufaddr = sc->frag_addr +
1694 i * sizeof(struct epic_frag_list);
1696 if ((desc->bufaddr & 3) ||
1697 ((desc->bufaddr & PAGE_MASK) +
1698 sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1699 epic_free_rings(sc);
1703 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1705 epic_free_rings(sc);
1709 bus_dmamap_sync(sc->ttag, sc->tmap,
1710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1711 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1717 * EEPROM operation functions
1720 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1724 CSR_WRITE_1(sc, EECTL, val);
1726 for (i = 0; i < 0xFF; i++) {
1727 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0)
1733 epic_read_eepromreg(epic_softc_t *sc)
1736 return (CSR_READ_1(sc, EECTL));
1740 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1743 epic_write_eepromreg(sc, val);
1744 epic_write_eepromreg(sc, (val | 0x4));
1745 epic_write_eepromreg(sc, val);
1747 return (epic_read_eepromreg(sc));
1751 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1755 for (i = 0xF; i >= 0; i--) {
1757 epic_eeprom_clock(sc, 0x0B);
1759 epic_eeprom_clock(sc, 0x03);
1764 epic_input_eepromw(epic_softc_t *sc)
1766 u_int16_t retval = 0;
1769 for (i = 0xF; i >= 0; i--) {
1770 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1778 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1783 epic_write_eepromreg(sc, 3);
1785 if (epic_read_eepromreg(sc) & 0x40)
1786 read_cmd = (loc & 0x3F) | 0x180;
1788 read_cmd = (loc & 0xFF) | 0x600;
1790 epic_output_eepromw(sc, read_cmd);
1792 dataval = epic_input_eepromw(sc);
1794 epic_write_eepromreg(sc, 1);
1800 * Here goes MII read/write routines.
1803 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1807 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1809 for (i = 0; i < 0x100; i++) {
1810 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1815 return (CSR_READ_4(sc, MIIDATA));
1819 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1823 CSR_WRITE_4(sc, MIIDATA, val);
1824 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1826 for(i = 0; i < 0x100; i++) {
1827 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0)
1834 epic_miibus_readreg(device_t dev, int phy, int reg)
1838 sc = device_get_softc(dev);
1840 return (PHY_READ_2(sc, phy, reg));
1844 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1848 sc = device_get_softc(dev);
1850 PHY_WRITE_2(sc, phy, reg, data);