2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/queue.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
76 #include <dev/mii/lxtphyreg.h>
78 #include "miibus_if.h"
80 #include <dev/tx/if_txreg.h>
81 #include <dev/tx/if_txvar.h>
83 MODULE_DEPEND(tx, pci, 1, 1, 1);
84 MODULE_DEPEND(tx, ether, 1, 1, 1);
85 MODULE_DEPEND(tx, miibus, 1, 1, 1);
87 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
88 static void epic_intr(void *);
89 static void epic_tx_underrun(epic_softc_t *);
90 static void epic_ifstart(struct ifnet *);
91 static void epic_ifstart_locked(struct ifnet *);
92 static void epic_timer(void *);
93 static void epic_init(void *);
94 static void epic_init_locked(epic_softc_t *);
95 static void epic_stop(epic_softc_t *);
96 static void epic_rx_done(epic_softc_t *);
97 static void epic_tx_done(epic_softc_t *);
98 static int epic_init_rings(epic_softc_t *);
99 static void epic_free_rings(epic_softc_t *);
100 static void epic_stop_activity(epic_softc_t *);
101 static int epic_queue_last_packet(epic_softc_t *);
102 static void epic_start_activity(epic_softc_t *);
103 static void epic_set_rx_mode(epic_softc_t *);
104 static void epic_set_tx_mode(epic_softc_t *);
105 static void epic_set_mc_table(epic_softc_t *);
106 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
107 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
108 static u_int16_t epic_input_eepromw(epic_softc_t *);
109 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
110 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
111 static u_int8_t epic_read_eepromreg(epic_softc_t *);
113 static int epic_read_phy_reg(epic_softc_t *, int, int);
114 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
116 static int epic_miibus_readreg(device_t, int, int);
117 static int epic_miibus_writereg(device_t, int, int, int);
118 static void epic_miibus_statchg(device_t);
119 static void epic_miibus_mediainit(device_t);
121 static int epic_ifmedia_upd(struct ifnet *);
122 static int epic_ifmedia_upd_locked(struct ifnet *);
123 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125 static int epic_probe(device_t);
126 static int epic_attach(device_t);
127 static int epic_shutdown(device_t);
128 static int epic_detach(device_t);
129 static void epic_release(epic_softc_t *);
130 static struct epic_type *epic_devtype(device_t);
132 static device_method_t epic_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, epic_probe),
135 DEVMETHOD(device_attach, epic_attach),
136 DEVMETHOD(device_detach, epic_detach),
137 DEVMETHOD(device_shutdown, epic_shutdown),
140 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
141 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
142 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
143 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
148 static driver_t epic_driver = {
154 static devclass_t epic_devclass;
156 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0);
157 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
159 static struct epic_type epic_devs[] = {
160 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" },
165 epic_probe(device_t dev)
169 t = epic_devtype(dev);
172 device_set_desc(dev, t->name);
173 return (BUS_PROBE_DEFAULT);
179 static struct epic_type *
180 epic_devtype(device_t dev)
186 while (t->name != NULL) {
187 if ((pci_get_vendor(dev) == t->ven_id) &&
188 (pci_get_device(dev) == t->dev_id)) {
196 #ifdef EPIC_USEIOSPACE
197 #define EPIC_RES SYS_RES_IOPORT
198 #define EPIC_RID PCIR_BASEIO
200 #define EPIC_RES SYS_RES_MEMORY
201 #define EPIC_RID PCIR_BASEMEM
205 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
212 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
214 *addr = segs->ds_addr;
218 * Attach routine: map registers, allocate softc, rings and descriptors.
219 * Reset to known state.
222 epic_attach(device_t dev)
230 sc = device_get_softc(dev);
232 /* Preinitialize softc structure. */
234 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
237 /* Fill ifnet structure. */
238 ifp = sc->ifp = if_alloc(IFT_ETHER);
240 device_printf(dev, "can not if_alloc()\n");
244 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
246 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
247 ifp->if_ioctl = epic_ifioctl;
248 ifp->if_start = epic_ifstart;
249 ifp->if_init = epic_init;
250 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
252 /* Enable busmastering. */
253 pci_enable_busmaster(dev);
256 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
257 if (sc->res == NULL) {
258 device_printf(dev, "couldn't map ports/memory\n");
263 /* Allocate interrupt. */
265 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
266 RF_SHAREABLE | RF_ACTIVE);
267 if (sc->irq == NULL) {
268 device_printf(dev, "couldn't map interrupt\n");
273 /* Allocate DMA tags. */
274 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
275 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
276 MCLBYTES * EPIC_MAX_FRAGS, EPIC_MAX_FRAGS, MCLBYTES, 0, NULL, NULL,
279 device_printf(dev, "couldn't allocate dma tag\n");
283 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
284 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
285 sizeof(struct epic_rx_desc) * RX_RING_SIZE,
286 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, NULL,
289 device_printf(dev, "couldn't allocate dma tag\n");
293 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
294 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
295 sizeof(struct epic_tx_desc) * TX_RING_SIZE,
296 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0,
297 NULL, NULL, &sc->ttag);
299 device_printf(dev, "couldn't allocate dma tag\n");
303 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
304 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
305 sizeof(struct epic_frag_list) * TX_RING_SIZE,
306 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0,
307 NULL, NULL, &sc->ftag);
309 device_printf(dev, "couldn't allocate dma tag\n");
313 /* Allocate DMA safe memory and get the DMA addresses. */
314 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist,
315 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap);
317 device_printf(dev, "couldn't allocate dma memory\n");
320 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist,
321 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr,
324 device_printf(dev, "couldn't map dma memory\n");
327 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
328 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap);
330 device_printf(dev, "couldn't allocate dma memory\n");
333 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
334 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr,
337 device_printf(dev, "couldn't map dma memory\n");
340 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
341 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap);
343 device_printf(dev, "couldn't allocate dma memory\n");
346 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
347 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr,
350 device_printf(dev, "couldn't map dma memory\n");
354 /* Bring the chip out of low-power mode. */
355 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
358 /* Workaround for Application Note 7-15. */
359 for (i = 0; i < 16; i++)
360 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
362 /* Read MAC address from EEPROM. */
363 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
364 ((u_int16_t *)eaddr)[i] = epic_read_eeprom(sc,i);
366 /* Set Non-Volatile Control Register from EEPROM. */
367 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
370 sc->tx_threshold = TRANSMIT_THRESHOLD;
371 sc->txcon = TXCON_DEFAULT;
372 sc->miicfg = MIICFG_SMI_ENABLE;
373 sc->phyid = EPIC_UNKN_PHY;
377 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2);
378 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2);
380 if (sc->cardvend != SMC_VENDORID)
381 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend);
383 /* Do ifmedia setup. */
384 error = mii_attach(dev, &sc->miibus, ifp, epic_ifmedia_upd,
385 epic_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
387 device_printf(dev, "attaching PHYs failed\n");
391 /* board type and ... */
393 for(i = 0x2c; i < 0x32; i++) {
394 tmp = epic_read_eeprom(sc, i);
395 if (' ' == (u_int8_t)tmp)
397 printf("%c", (u_int8_t)tmp);
399 if (' ' == (u_int8_t)tmp)
401 printf("%c", (u_int8_t)tmp);
405 /* Initialize rings. */
406 if (epic_init_rings(sc)) {
407 device_printf(dev, "failed to init rings\n");
412 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
413 ifp->if_capabilities |= IFCAP_VLAN_MTU;
414 ifp->if_capenable |= IFCAP_VLAN_MTU;
415 callout_init_mtx(&sc->timer, &sc->lock, 0);
417 /* Attach to OS's managers. */
418 ether_ifattach(ifp, eaddr);
420 /* Activate our interrupt handler. */
421 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
422 NULL, epic_intr, sc, &sc->sc_ih);
424 device_printf(dev, "couldn't set up irq\n");
436 * Free any resources allocated by the driver.
439 epic_release(epic_softc_t *sc)
444 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
446 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res);
449 bus_dmamap_unload(sc->ftag, sc->fmap);
450 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap);
453 bus_dmamap_unload(sc->ttag, sc->tmap);
454 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap);
457 bus_dmamap_unload(sc->rtag, sc->rmap);
458 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
461 bus_dma_tag_destroy(sc->mtag);
463 bus_dma_tag_destroy(sc->ftag);
465 bus_dma_tag_destroy(sc->ttag);
467 bus_dma_tag_destroy(sc->rtag);
468 mtx_destroy(&sc->lock);
472 * Detach driver and free resources.
475 epic_detach(device_t dev)
480 sc = device_get_softc(dev);
486 callout_drain(&sc->timer);
488 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
490 bus_generic_detach(dev);
491 device_delete_child(dev, sc->miibus);
501 * Stop all chip I/O so that the kernel's probe routines don't
502 * get confused by errant DMAs when rebooting.
505 epic_shutdown(device_t dev)
509 sc = device_get_softc(dev);
518 * This is if_ioctl handler.
521 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data)
523 epic_softc_t *sc = ifp->if_softc;
524 struct mii_data *mii;
525 struct ifreq *ifr = (struct ifreq *) data;
530 if (ifp->if_mtu == ifr->ifr_mtu)
533 /* XXX Though the datasheet doesn't imply any
534 * limitations on RX and TX sizes beside max 64Kb
535 * DMA transfer, seems we can't send more then 1600
536 * data bytes per ethernet packet (transmitter hangs
537 * up if more data is sent).
540 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
541 ifp->if_mtu = ifr->ifr_mtu;
543 epic_init_locked(sc);
551 * If the interface is marked up and stopped, then start it.
552 * If it is marked down and running, then stop it.
555 if (ifp->if_flags & IFF_UP) {
556 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
557 epic_init_locked(sc);
562 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
569 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
570 epic_stop_activity(sc);
571 epic_set_mc_table(sc);
572 epic_set_rx_mode(sc);
573 epic_start_activity(sc);
580 epic_set_mc_table(sc);
587 mii = device_get_softc(sc->miibus);
588 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
592 error = ether_ioctl(ifp, command, data);
599 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
600 bus_size_t mapsize, int error)
602 struct epic_frag_list *flist;
608 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments"));
610 /* Fill fragments list. */
611 for (i = 0; i < nseg; i++) {
612 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
613 flist->frag[i].fraglen = segs[i].ds_len;
614 flist->frag[i].fragaddr = segs[i].ds_addr;
616 flist->numfrags = nseg;
620 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
621 bus_size_t mapsize, int error)
623 struct epic_rx_desc *desc;
628 KASSERT(nseg == 1, ("too many DMA segments"));
630 desc->bufaddr = segs->ds_addr;
634 * This is if_start handler. It takes mbufs from if_snd queue
635 * and queue them for transmit, one by one, until TX ring become full
636 * or queue become empty.
639 epic_ifstart(struct ifnet * ifp)
641 epic_softc_t *sc = ifp->if_softc;
644 epic_ifstart_locked(ifp);
649 epic_ifstart_locked(struct ifnet * ifp)
651 epic_softc_t *sc = ifp->if_softc;
652 struct epic_tx_buffer *buf;
653 struct epic_tx_desc *desc;
654 struct epic_frag_list *flist;
658 while (sc->pending_txs < TX_RING_SIZE) {
659 buf = sc->tx_buffer + sc->cur_tx;
660 desc = sc->tx_desc + sc->cur_tx;
661 flist = sc->tx_flist + sc->cur_tx;
663 /* Get next packet to send. */
664 IF_DEQUEUE(&ifp->if_snd, m0);
666 /* If nothing to send, return. */
670 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
671 epic_dma_map_txbuf, flist, 0);
673 if (error && error != EFBIG) {
675 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
680 * If packet was more than EPIC_MAX_FRAGS parts,
681 * recopy packet to a newly allocated mbuf cluster.
684 m = m_defrag(m0, M_NOWAIT);
687 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
693 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
694 epic_dma_map_txbuf, flist, 0);
697 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
701 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
705 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
706 desc->control = 0x01;
708 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
709 desc->status = 0x8000;
710 bus_dmamap_sync(sc->ttag, sc->tmap,
711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
712 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
713 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
715 /* Set watchdog timer. */
721 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
725 * Synopsis: Finish all received frames.
728 epic_rx_done(epic_softc_t *sc)
730 struct ifnet *ifp = sc->ifp;
732 struct epic_rx_buffer *buf;
733 struct epic_rx_desc *desc;
738 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD);
739 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
740 buf = sc->rx_buffer + sc->cur_rx;
741 desc = sc->rx_desc + sc->cur_rx;
743 /* Switch to next descriptor. */
744 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK;
747 * Check for RX errors. This should only happen if
748 * SAVE_ERRORED_PACKETS is set. RX errors generate
749 * RXE interrupt usually.
751 if ((desc->status & 1) == 0) {
752 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
753 desc->status = 0x8000;
757 /* Save packet length and mbuf contained packet. */
758 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
759 len = desc->rxlength - ETHER_CRC_LEN;
762 /* Try to get an mbuf cluster. */
763 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
764 if (buf->mbuf == NULL) {
766 desc->status = 0x8000;
767 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
770 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
771 m_adj(buf->mbuf, ETHER_ALIGN);
773 /* Point to new mbuf, and give descriptor to chip. */
774 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf,
775 epic_dma_map_rxbuf, desc, 0);
778 desc->status = 0x8000;
779 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
783 desc->status = 0x8000;
784 bus_dmamap_unload(sc->mtag, buf->map);
786 buf->map = sc->sparemap;
788 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
790 /* First mbuf in packet holds the ethernet and packet headers */
791 m->m_pkthdr.rcvif = ifp;
792 m->m_pkthdr.len = m->m_len = len;
794 /* Give mbuf to OS. */
796 (*ifp->if_input)(ifp, m);
799 /* Successfully received frame */
800 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
802 bus_dmamap_sync(sc->rtag, sc->rmap,
803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
807 * Synopsis: Do last phase of transmission. I.e. if desc is
808 * transmitted, decrease pending_txs counter, free mbuf contained
809 * packet, switch to next descriptor and repeat until no packets
810 * are pending or descriptor is not transmitted yet.
813 epic_tx_done(epic_softc_t *sc)
815 struct epic_tx_buffer *buf;
816 struct epic_tx_desc *desc;
819 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD);
820 while (sc->pending_txs > 0) {
821 buf = sc->tx_buffer + sc->dirty_tx;
822 desc = sc->tx_desc + sc->dirty_tx;
823 status = desc->status;
826 * If packet is not transmitted, thou followed
827 * packets are not transmitted too.
832 /* Packet is transmitted. Switch to next and free mbuf. */
834 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
835 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
836 bus_dmamap_unload(sc->mtag, buf->map);
840 /* Check for errors and collisions. */
842 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
844 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
845 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, (status >> 8) & 0x1F);
847 if ((status & 0x1001) == 0x1001)
848 device_printf(sc->dev,
849 "Tx ERROR: excessive coll. number\n");
853 if (sc->pending_txs < TX_RING_SIZE)
854 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
855 bus_dmamap_sync(sc->ttag, sc->tmap,
856 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
871 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
872 CSR_WRITE_4(sc, INTSTAT, status);
874 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
876 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
878 if (status & INTSTAT_OVW)
879 device_printf(sc->dev, "RX buffer overflow\n");
880 if (status & INTSTAT_RQE)
881 device_printf(sc->dev, "RX FIFO overflow\n");
883 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
884 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
885 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
889 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
891 if (sc->ifp->if_snd.ifq_head != NULL)
892 epic_ifstart_locked(sc->ifp);
895 /* Check for rare errors */
896 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
897 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
898 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
899 INTSTAT_APE|INTSTAT_DPE)) {
900 device_printf(sc->dev, "PCI fatal errors occurred: %s%s%s%s\n",
901 (status & INTSTAT_PMA) ? "PMA " : "",
902 (status & INTSTAT_PTA) ? "PTA " : "",
903 (status & INTSTAT_APE) ? "APE " : "",
904 (status & INTSTAT_DPE) ? "DPE" : "");
907 epic_init_locked(sc);
911 if (status & INTSTAT_RXE) {
913 device_printf(sc->dev, "CRC/Alignment error\n");
915 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
918 if (status & INTSTAT_TXU) {
919 epic_tx_underrun(sc);
920 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
925 /* If no packets are pending, then no timeouts. */
926 if (sc->pending_txs == 0)
932 * Handle the TX underrun error: increase the TX threshold
933 * and restart the transmitter.
936 epic_tx_underrun(epic_softc_t *sc)
938 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
939 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
941 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
944 sc->tx_threshold += 0x40;
946 device_printf(sc->dev,
947 "Tx UNDERRUN: TX threshold increased to %d\n",
952 /* We must set TXUGO to reset the stuck transmitter. */
953 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
955 /* Update the TX threshold */
956 epic_stop_activity(sc);
957 epic_set_tx_mode(sc);
958 epic_start_activity(sc);
962 * This function is called once a second when the interface is running
963 * and performs two functions. First, it provides a timer for the mii
964 * to help with autonegotiation. Second, it checks for transmit
968 epic_timer(void *arg)
970 epic_softc_t *sc = arg;
971 struct mii_data *mii;
975 EPIC_ASSERT_LOCKED(sc);
976 if (sc->tx_timeout && --sc->tx_timeout == 0) {
977 device_printf(sc->dev, "device timeout %d packets\n",
980 /* Try to finish queued packets. */
983 /* If not successful. */
984 if (sc->pending_txs > 0) {
985 if_inc_counter(ifp, IFCOUNTER_OERRORS, sc->pending_txs);
987 /* Reinitialize board. */
988 device_printf(sc->dev, "reinitialization\n");
990 epic_init_locked(sc);
992 device_printf(sc->dev,
993 "seems we can continue normaly\n");
996 if (ifp->if_snd.ifq_head)
997 epic_ifstart_locked(ifp);
1000 mii = device_get_softc(sc->miibus);
1003 callout_reset(&sc->timer, hz, epic_timer, sc);
1007 * Set media options.
1010 epic_ifmedia_upd(struct ifnet *ifp)
1017 error = epic_ifmedia_upd_locked(ifp);
1023 epic_ifmedia_upd_locked(struct ifnet *ifp)
1026 struct mii_data *mii;
1027 struct ifmedia *ifm;
1028 struct mii_softc *miisc;
1032 mii = device_get_softc(sc->miibus);
1033 ifm = &mii->mii_media;
1034 media = ifm->ifm_cur->ifm_media;
1036 /* Do not do anything if interface is not up. */
1037 if ((ifp->if_flags & IFF_UP) == 0)
1041 * Lookup current selected PHY.
1043 if (IFM_INST(media) == sc->serinst) {
1044 sc->phyid = EPIC_SERIAL;
1047 /* If we're not selecting serial interface, select MII mode. */
1048 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1049 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1051 /* Default to unknown PHY. */
1052 sc->phyid = EPIC_UNKN_PHY;
1054 /* Lookup selected PHY. */
1055 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
1056 if (IFM_INST(media) == miisc->mii_inst) {
1062 /* Identify selected PHY. */
1064 int id1, id2, model, oui;
1066 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1067 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1069 oui = MII_OUI(id1, id2);
1070 model = MII_MODEL(id2);
1072 case MII_OUI_xxQUALSEMI:
1073 if (model == MII_MODEL_xxQUALSEMI_QS6612)
1074 sc->phyid = EPIC_QS6612_PHY;
1076 case MII_OUI_ALTIMA:
1077 if (model == MII_MODEL_ALTIMA_AC101)
1078 sc->phyid = EPIC_AC101_PHY;
1080 case MII_OUI_xxLEVEL1:
1081 if (model == MII_MODEL_xxLEVEL1_LXT970)
1082 sc->phyid = EPIC_LXT970_PHY;
1089 * Do PHY specific card setup.
1093 * Call this, to isolate all not selected PHYs and
1098 /* Do our own setup. */
1099 switch (sc->phyid) {
1100 case EPIC_QS6612_PHY:
1102 case EPIC_AC101_PHY:
1103 /* We have to powerup fiber tranceivers. */
1104 if (IFM_SUBTYPE(media) == IFM_100_FX)
1105 sc->miicfg |= MIICFG_694_ENABLE;
1107 sc->miicfg &= ~MIICFG_694_ENABLE;
1108 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1111 case EPIC_LXT970_PHY:
1112 /* We have to powerup fiber tranceivers. */
1113 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1114 if (IFM_SUBTYPE(media) == IFM_100_FX)
1115 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1117 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1118 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1122 /* Select serial PHY (10base2/BNC usually). */
1123 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1124 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1126 /* There is no driver to fill this. */
1127 mii->mii_media_active = media;
1128 mii->mii_media_status = 0;
1131 * We need to call this manually as it wasn't called
1132 * in mii_mediachg().
1134 epic_miibus_statchg(sc->dev);
1137 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1145 * Report current media status.
1148 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1151 struct mii_data *mii;
1154 mii = device_get_softc(sc->miibus);
1157 /* Nothing should be selected if interface is down. */
1158 if ((ifp->if_flags & IFF_UP) == 0) {
1159 ifmr->ifm_active = IFM_NONE;
1160 ifmr->ifm_status = 0;
1165 /* Call underlying pollstat, if not serial PHY. */
1166 if (sc->phyid != EPIC_SERIAL)
1169 /* Simply copy media info. */
1170 ifmr->ifm_active = mii->mii_media_active;
1171 ifmr->ifm_status = mii->mii_media_status;
1176 * Callback routine, called on media change.
1179 epic_miibus_statchg(device_t dev)
1182 struct mii_data *mii;
1185 sc = device_get_softc(dev);
1186 mii = device_get_softc(sc->miibus);
1187 media = mii->mii_media_active;
1189 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1192 * If we are in full-duplex mode or loopback operation,
1193 * we need to decouple receiver and transmitter.
1195 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1196 sc->txcon |= TXCON_FULL_DUPLEX;
1198 /* On some cards we need manualy set fullduplex led. */
1199 if (sc->cardid == SMC9432FTX ||
1200 sc->cardid == SMC9432FTX_SC) {
1201 if (IFM_OPTIONS(media) & IFM_FDX)
1202 sc->miicfg |= MIICFG_694_ENABLE;
1204 sc->miicfg &= ~MIICFG_694_ENABLE;
1206 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1209 epic_stop_activity(sc);
1210 epic_set_tx_mode(sc);
1211 epic_start_activity(sc);
1215 epic_miibus_mediainit(device_t dev)
1218 struct mii_data *mii;
1219 struct ifmedia *ifm;
1222 sc = device_get_softc(dev);
1223 mii = device_get_softc(sc->miibus);
1224 ifm = &mii->mii_media;
1227 * Add Serial Media Interface if present, this applies to
1230 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1231 /* Store its instance. */
1232 sc->serinst = mii->mii_instance++;
1234 /* Add as 10base2/BNC media. */
1235 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1236 ifmedia_add(ifm, media, 0, NULL);
1238 /* Report to user. */
1239 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1244 * Reset chip and update media.
1247 epic_init(void *xsc)
1249 epic_softc_t *sc = xsc;
1252 epic_init_locked(sc);
1257 epic_init_locked(epic_softc_t *sc)
1259 struct ifnet *ifp = sc->ifp;
1262 /* If interface is already running, then we need not do anything. */
1263 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1267 /* Soft reset the chip (we have to power up card before). */
1268 CSR_WRITE_4(sc, GENCTL, 0);
1269 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1272 * Reset takes 15 pci ticks which depends on PCI bus speed.
1273 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1278 CSR_WRITE_4(sc, GENCTL, 0);
1280 /* Workaround for Application Note 7-15 */
1281 for (i = 0; i < 16; i++)
1282 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1284 /* Give rings to EPIC */
1285 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1286 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1288 /* Put node address to EPIC. */
1289 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IF_LLADDR(sc->ifp))[0]);
1290 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IF_LLADDR(sc->ifp))[1]);
1291 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IF_LLADDR(sc->ifp))[2]);
1293 /* Set tx mode, includeing transmit threshold. */
1294 epic_set_tx_mode(sc);
1296 /* Compute and set RXCON. */
1297 epic_set_rx_mode(sc);
1299 /* Set multicast table. */
1300 epic_set_mc_table(sc);
1302 /* Enable interrupts by setting the interrupt mask. */
1303 CSR_WRITE_4(sc, INTMASK,
1304 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1305 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1308 /* Acknowledge all pending interrupts. */
1309 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1311 /* Enable interrupts, set for PCI read multiple and etc */
1312 CSR_WRITE_4(sc, GENCTL,
1313 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1314 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1316 /* Mark interface running ... */
1317 if (ifp->if_flags & IFF_UP)
1318 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1320 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1323 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1325 /* Start Rx process */
1326 epic_start_activity(sc);
1328 /* Set appropriate media */
1329 epic_ifmedia_upd_locked(ifp);
1331 callout_reset(&sc->timer, hz, epic_timer, sc);
1335 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1339 epic_set_rx_mode(epic_softc_t *sc)
1344 flags = sc->ifp->if_flags;
1345 rxcon = RXCON_DEFAULT;
1347 #ifdef EPIC_EARLY_RX
1348 rxcon |= RXCON_EARLY_RX;
1351 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1353 CSR_WRITE_4(sc, RXCON, rxcon);
1357 * Synopsis: Set transmit control register. Chip must be in idle state to
1361 epic_set_tx_mode(epic_softc_t *sc)
1364 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1365 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1367 CSR_WRITE_4(sc, TXCON, sc->txcon);
1371 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1372 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch
1373 * individual frames, multicast filter must be manually programmed).
1375 * Note: EPIC must be in idle state.
1378 epic_set_mc_table(epic_softc_t *sc)
1381 struct ifmultiaddr *ifma;
1382 u_int16_t filter[4];
1386 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1387 CSR_WRITE_4(sc, MC0, 0xFFFF);
1388 CSR_WRITE_4(sc, MC1, 0xFFFF);
1389 CSR_WRITE_4(sc, MC2, 0xFFFF);
1390 CSR_WRITE_4(sc, MC3, 0xFFFF);
1399 if_maddr_rlock(ifp);
1400 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1401 if (ifma->ifma_addr->sa_family != AF_LINK)
1403 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1404 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1405 filter[h >> 4] |= 1 << (h & 0xF);
1407 if_maddr_runlock(ifp);
1409 CSR_WRITE_4(sc, MC0, filter[0]);
1410 CSR_WRITE_4(sc, MC1, filter[1]);
1411 CSR_WRITE_4(sc, MC2, filter[2]);
1412 CSR_WRITE_4(sc, MC3, filter[3]);
1417 * Synopsis: Start receive process and transmit one, if they need.
1420 epic_start_activity(epic_softc_t *sc)
1423 /* Start rx process. */
1424 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1425 (sc->pending_txs ? COMMAND_TXQUEUED : 0));
1429 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1430 * packet needs to be queued to stop Tx DMA.
1433 epic_stop_activity(epic_softc_t *sc)
1437 /* Stop Tx and Rx DMA. */
1438 CSR_WRITE_4(sc, COMMAND,
1439 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1441 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */
1442 for (i = 0; i < 0x1000; i++) {
1443 status = CSR_READ_4(sc, INTSTAT) &
1444 (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1445 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1450 /* Catch all finished packets. */
1454 status = CSR_READ_4(sc, INTSTAT);
1456 if ((status & INTSTAT_RXIDLE) == 0)
1457 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1459 if ((status & INTSTAT_TXIDLE) == 0)
1460 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1463 * May need to queue one more packet if TQE, this is rare
1464 * but existing case.
1466 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1467 (void)epic_queue_last_packet(sc);
1471 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1472 * a packet from current descriptor will be copied to internal RAM. We
1473 * compose a dummy packet here and queue it for transmission.
1475 * XXX the packet will then be actually sent over network...
1478 epic_queue_last_packet(epic_softc_t *sc)
1480 struct epic_tx_desc *desc;
1481 struct epic_frag_list *flist;
1482 struct epic_tx_buffer *buf;
1486 device_printf(sc->dev, "queue last packet\n");
1488 desc = sc->tx_desc + sc->cur_tx;
1489 flist = sc->tx_flist + sc->cur_tx;
1490 buf = sc->tx_buffer + sc->cur_tx;
1492 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1495 MGETHDR(m0, M_NOWAIT, MT_DATA);
1500 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN);
1501 m0->m_pkthdr.len = m0->m_len;
1502 m0->m_pkthdr.rcvif = sc->ifp;
1503 bzero(mtod(m0, caddr_t), m0->m_len);
1505 /* Fill fragments list. */
1506 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
1507 epic_dma_map_txbuf, flist, 0);
1512 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
1514 /* Fill in descriptor. */
1517 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1518 desc->control = 0x01;
1519 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
1520 desc->status = 0x8000;
1521 bus_dmamap_sync(sc->ttag, sc->tmap,
1522 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1523 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1525 /* Launch transmission. */
1526 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1528 /* Wait Tx DMA to stop (for how long??? XXX) */
1529 for (i = 0; i < 1000; i++) {
1530 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1535 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1536 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1544 * Synopsis: Shut down board and deallocates rings.
1547 epic_stop(epic_softc_t *sc)
1550 EPIC_ASSERT_LOCKED(sc);
1553 callout_stop(&sc->timer);
1555 /* Disable interrupts */
1556 CSR_WRITE_4(sc, INTMASK, 0);
1557 CSR_WRITE_4(sc, GENCTL, 0);
1559 /* Try to stop Rx and TX processes */
1560 epic_stop_activity(sc);
1563 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1566 /* Make chip go to bed */
1567 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1569 /* Mark as stopped */
1570 sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1574 * Synopsis: This function should free all memory allocated for rings.
1577 epic_free_rings(epic_softc_t *sc)
1581 for (i = 0; i < RX_RING_SIZE; i++) {
1582 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1583 struct epic_rx_desc *desc = sc->rx_desc + i;
1586 desc->buflength = 0;
1590 bus_dmamap_unload(sc->mtag, buf->map);
1591 bus_dmamap_destroy(sc->mtag, buf->map);
1597 if (sc->sparemap != NULL)
1598 bus_dmamap_destroy(sc->mtag, sc->sparemap);
1600 for (i = 0; i < TX_RING_SIZE; i++) {
1601 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1602 struct epic_tx_desc *desc = sc->tx_desc + i;
1605 desc->buflength = 0;
1609 bus_dmamap_unload(sc->mtag, buf->map);
1610 bus_dmamap_destroy(sc->mtag, buf->map);
1618 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1619 * Point Tx descs to fragment lists. Check that all descs and fraglists
1620 * are bounded and aligned properly.
1623 epic_init_rings(epic_softc_t *sc)
1627 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1629 /* Initialize the RX descriptor ring. */
1630 for (i = 0; i < RX_RING_SIZE; i++) {
1631 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1632 struct epic_rx_desc *desc = sc->rx_desc + i;
1634 desc->status = 0; /* Owned by driver */
1635 desc->next = sc->rx_addr +
1636 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc);
1638 if ((desc->next & 3) ||
1639 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1640 epic_free_rings(sc);
1644 buf->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1645 if (buf->mbuf == NULL) {
1646 epic_free_rings(sc);
1649 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1650 m_adj(buf->mbuf, ETHER_ALIGN);
1652 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1654 epic_free_rings(sc);
1657 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1658 epic_dma_map_rxbuf, desc, 0);
1660 epic_free_rings(sc);
1663 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1665 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */
1666 desc->status = 0x8000; /* Set owner bit to NIC */
1668 bus_dmamap_sync(sc->rtag, sc->rmap,
1669 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1671 /* Create the spare DMA map. */
1672 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap);
1674 epic_free_rings(sc);
1678 /* Initialize the TX descriptor ring. */
1679 for (i = 0; i < TX_RING_SIZE; i++) {
1680 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1681 struct epic_tx_desc *desc = sc->tx_desc + i;
1684 desc->next = sc->tx_addr +
1685 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc);
1687 if ((desc->next & 3) ||
1688 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1689 epic_free_rings(sc);
1694 desc->bufaddr = sc->frag_addr +
1695 i * sizeof(struct epic_frag_list);
1697 if ((desc->bufaddr & 3) ||
1698 ((desc->bufaddr & PAGE_MASK) +
1699 sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1700 epic_free_rings(sc);
1704 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1706 epic_free_rings(sc);
1710 bus_dmamap_sync(sc->ttag, sc->tmap,
1711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1712 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1718 * EEPROM operation functions
1721 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1725 CSR_WRITE_1(sc, EECTL, val);
1727 for (i = 0; i < 0xFF; i++) {
1728 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0)
1734 epic_read_eepromreg(epic_softc_t *sc)
1737 return (CSR_READ_1(sc, EECTL));
1741 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1744 epic_write_eepromreg(sc, val);
1745 epic_write_eepromreg(sc, (val | 0x4));
1746 epic_write_eepromreg(sc, val);
1748 return (epic_read_eepromreg(sc));
1752 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1756 for (i = 0xF; i >= 0; i--) {
1758 epic_eeprom_clock(sc, 0x0B);
1760 epic_eeprom_clock(sc, 0x03);
1765 epic_input_eepromw(epic_softc_t *sc)
1767 u_int16_t retval = 0;
1770 for (i = 0xF; i >= 0; i--) {
1771 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1779 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1784 epic_write_eepromreg(sc, 3);
1786 if (epic_read_eepromreg(sc) & 0x40)
1787 read_cmd = (loc & 0x3F) | 0x180;
1789 read_cmd = (loc & 0xFF) | 0x600;
1791 epic_output_eepromw(sc, read_cmd);
1793 dataval = epic_input_eepromw(sc);
1795 epic_write_eepromreg(sc, 1);
1801 * Here goes MII read/write routines.
1804 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1808 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1810 for (i = 0; i < 0x100; i++) {
1811 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1816 return (CSR_READ_4(sc, MIIDATA));
1820 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1824 CSR_WRITE_4(sc, MIIDATA, val);
1825 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1827 for(i = 0; i < 0x100; i++) {
1828 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0)
1835 epic_miibus_readreg(device_t dev, int phy, int reg)
1839 sc = device_get_softc(dev);
1841 return (PHY_READ_2(sc, phy, reg));
1845 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1849 sc = device_get_softc(dev);
1851 PHY_WRITE_2(sc, phy, reg, data);