2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
59 #include <net/if_vlan_var.h>
61 #include <machine/bus.h>
62 #include <machine/resource.h>
63 #include <machine/clock.h> /* for DELAY */
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
70 #include <dev/mii/mii.h>
71 #include <dev/mii/miivar.h>
74 #include <dev/mii/lxtphyreg.h>
76 #include "miibus_if.h"
78 #include <dev/tx/if_txreg.h>
79 #include <dev/tx/if_txvar.h>
81 MODULE_DEPEND(tx, pci, 1, 1, 1);
82 MODULE_DEPEND(tx, ether, 1, 1, 1);
83 MODULE_DEPEND(tx, miibus, 1, 1, 1);
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static void epic_ifstart(struct ifnet *);
89 static void epic_ifwatchdog(struct ifnet *);
90 static void epic_stats_update(epic_softc_t *);
91 static void epic_init(void *);
92 static void epic_stop(epic_softc_t *);
93 static void epic_rx_done(epic_softc_t *);
94 static void epic_tx_done(epic_softc_t *);
95 static int epic_init_rings(epic_softc_t *);
96 static void epic_free_rings(epic_softc_t *);
97 static void epic_stop_activity(epic_softc_t *);
98 static int epic_queue_last_packet(epic_softc_t *);
99 static void epic_start_activity(epic_softc_t *);
100 static void epic_set_rx_mode(epic_softc_t *);
101 static void epic_set_tx_mode(epic_softc_t *);
102 static void epic_set_mc_table(epic_softc_t *);
103 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
104 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
105 static u_int16_t epic_input_eepromw(epic_softc_t *);
106 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
107 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
108 static u_int8_t epic_read_eepromreg(epic_softc_t *);
110 static int epic_read_phy_reg(epic_softc_t *, int, int);
111 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
113 static int epic_miibus_readreg(device_t, int, int);
114 static int epic_miibus_writereg(device_t, int, int, int);
115 static void epic_miibus_statchg(device_t);
116 static void epic_miibus_mediainit(device_t);
118 static int epic_ifmedia_upd(struct ifnet *);
119 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
121 static int epic_probe(device_t);
122 static int epic_attach(device_t);
123 static void epic_shutdown(device_t);
124 static int epic_detach(device_t);
125 static void epic_release(epic_softc_t *);
126 static struct epic_type *epic_devtype(device_t);
128 static device_method_t epic_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, epic_probe),
131 DEVMETHOD(device_attach, epic_attach),
132 DEVMETHOD(device_detach, epic_detach),
133 DEVMETHOD(device_shutdown, epic_shutdown),
136 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
137 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
138 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
139 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
144 static driver_t epic_driver = {
150 static devclass_t epic_devclass;
152 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0);
153 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
155 static struct epic_type epic_devs[] = {
156 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" },
166 t = epic_devtype(dev);
169 device_set_desc(dev, t->name);
170 return (BUS_PROBE_DEFAULT);
176 static struct epic_type *
184 while (t->name != NULL) {
185 if ((pci_get_vendor(dev) == t->ven_id) &&
186 (pci_get_device(dev) == t->dev_id)) {
194 #ifdef EPIC_USEIOSPACE
195 #define EPIC_RES SYS_RES_IOPORT
196 #define EPIC_RID PCIR_BASEIO
198 #define EPIC_RES SYS_RES_MEMORY
199 #define EPIC_RID PCIR_BASEMEM
203 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
210 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
212 *addr = segs->ds_addr;
216 * Attach routine: map registers, allocate softc, rings and descriptors.
217 * Reset to known state.
230 sc = device_get_softc(dev);
231 unit = device_get_unit(dev);
233 /* Preinitialize softc structure. */
237 /* Fill ifnet structure. */
239 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
241 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST|IFF_NEEDSGIANT;
242 ifp->if_ioctl = epic_ifioctl;
243 ifp->if_start = epic_ifstart;
244 ifp->if_watchdog = epic_ifwatchdog;
245 ifp->if_init = epic_init;
247 ifp->if_baudrate = 10000000;
248 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
250 /* Enable busmastering. */
251 pci_enable_busmaster(dev);
254 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
255 if (sc->res == NULL) {
256 device_printf(dev, "couldn't map ports/memory\n");
261 sc->sc_st = rman_get_bustag(sc->res);
262 sc->sc_sh = rman_get_bushandle(sc->res);
264 /* Allocate interrupt. */
266 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
267 RF_SHAREABLE | RF_ACTIVE);
268 if (sc->irq == NULL) {
269 device_printf(dev, "couldn't map interrupt\n");
274 /* Allocate DMA tags. */
275 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
276 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * EPIC_MAX_FRAGS,
277 EPIC_MAX_FRAGS, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->mtag);
279 device_printf(dev, "couldn't allocate dma tag\n");
283 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
284 BUS_SPACE_MAXADDR, NULL, NULL,
285 sizeof(struct epic_rx_desc) * RX_RING_SIZE,
286 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, busdma_lock_mutex,
289 device_printf(dev, "couldn't allocate dma tag\n");
293 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
294 BUS_SPACE_MAXADDR, NULL, NULL,
295 sizeof(struct epic_tx_desc) * TX_RING_SIZE,
296 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0,
297 busdma_lock_mutex, &Giant, &sc->ttag);
299 device_printf(dev, "couldn't allocate dma tag\n");
303 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
304 BUS_SPACE_MAXADDR, NULL, NULL,
305 sizeof(struct epic_frag_list) * TX_RING_SIZE,
306 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0,
307 busdma_lock_mutex, &Giant, &sc->ftag);
309 device_printf(dev, "couldn't allocate dma tag\n");
313 /* Allocate DMA safe memory and get the DMA addresses. */
314 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist,
315 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap);
317 device_printf(dev, "couldn't allocate dma memory\n");
320 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist,
321 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr,
324 device_printf(dev, "couldn't map dma memory\n");
327 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
328 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap);
330 device_printf(dev, "couldn't allocate dma memory\n");
333 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
334 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr,
337 device_printf(dev, "couldn't map dma memory\n");
340 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
341 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap);
343 device_printf(dev, "couldn't allocate dma memory\n");
346 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
347 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr,
350 device_printf(dev, "couldn't map dma memory\n");
354 /* Bring the chip out of low-power mode. */
355 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
358 /* Workaround for Application Note 7-15. */
359 for (i = 0; i < 16; i++)
360 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
362 /* Read MAC address from EEPROM. */
363 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
364 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
366 /* Set Non-Volatile Control Register from EEPROM. */
367 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
370 sc->tx_threshold = TRANSMIT_THRESHOLD;
371 sc->txcon = TXCON_DEFAULT;
372 sc->miicfg = MIICFG_SMI_ENABLE;
373 sc->phyid = EPIC_UNKN_PHY;
377 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2);
378 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2);
380 if (sc->cardvend != SMC_VENDORID)
381 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend);
383 /* Do ifmedia setup. */
384 if (mii_phy_probe(dev, &sc->miibus,
385 epic_ifmedia_upd, epic_ifmedia_sts)) {
386 device_printf(dev, "ERROR! MII without any PHY!?\n");
391 /* board type and ... */
393 for(i = 0x2c; i < 0x32; i++) {
394 tmp = epic_read_eeprom(sc, i);
395 if (' ' == (u_int8_t)tmp)
397 printf("%c", (u_int8_t)tmp);
399 if (' ' == (u_int8_t)tmp)
401 printf("%c", (u_int8_t)tmp);
405 /* Initialize rings. */
406 if (epic_init_rings(sc)) {
407 device_printf(dev, "failed to init rings\n");
412 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
413 ifp->if_capabilities |= IFCAP_VLAN_MTU;
414 ifp->if_capenable |= IFCAP_VLAN_MTU;
415 callout_handle_init(&sc->stat_ch);
417 /* Activate our interrupt handler. */
418 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
419 epic_intr, sc, &sc->sc_ih);
421 device_printf(dev, "couldn't set up irq\n");
425 /* Attach to OS's managers. */
426 ether_ifattach(ifp, sc->sc_macaddr);
437 * Free any resources allocated by the driver.
440 epic_release(epic_softc_t *sc)
444 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
446 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res);
449 bus_dmamap_unload(sc->ftag, sc->fmap);
450 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap);
451 bus_dmamap_destroy(sc->ftag, sc->fmap);
454 bus_dmamap_unload(sc->ttag, sc->tmap);
455 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap);
456 bus_dmamap_destroy(sc->ttag, sc->tmap);
459 bus_dmamap_unload(sc->rtag, sc->rmap);
460 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
461 bus_dmamap_destroy(sc->rtag, sc->rmap);
464 bus_dma_tag_destroy(sc->mtag);
466 bus_dma_tag_destroy(sc->ftag);
468 bus_dma_tag_destroy(sc->ttag);
470 bus_dma_tag_destroy(sc->rtag);
474 * Detach driver and free resources.
486 sc = device_get_softc(dev);
487 ifp = &sc->arpcom.ac_if;
493 bus_generic_detach(dev);
494 device_delete_child(dev, sc->miibus);
496 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
506 * Stop all chip I/O so that the kernel's probe routines don't
507 * get confused by errant DMAs when rebooting.
515 sc = device_get_softc(dev);
521 * This is if_ioctl handler.
524 epic_ifioctl(ifp, command, data)
529 epic_softc_t *sc = ifp->if_softc;
530 struct mii_data *mii;
531 struct ifreq *ifr = (struct ifreq *) data;
538 if (ifp->if_mtu == ifr->ifr_mtu)
541 /* XXX Though the datasheet doesn't imply any
542 * limitations on RX and TX sizes beside max 64Kb
543 * DMA transfer, seems we can't send more then 1600
544 * data bytes per ethernet packet (transmitter hangs
545 * up if more data is sent).
547 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
548 ifp->if_mtu = ifr->ifr_mtu;
557 * If the interface is marked up and stopped, then start it.
558 * If it is marked down and running, then stop it.
560 if (ifp->if_flags & IFF_UP) {
561 if ((ifp->if_flags & IFF_RUNNING) == 0) {
566 if (ifp->if_flags & IFF_RUNNING) {
572 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
573 epic_stop_activity(sc);
574 epic_set_mc_table(sc);
575 epic_set_rx_mode(sc);
576 epic_start_activity(sc);
581 epic_set_mc_table(sc);
587 mii = device_get_softc(sc->miibus);
588 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
592 error = ether_ioctl(ifp, command, data);
600 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
601 bus_size_t mapsize, int error)
603 struct epic_frag_list *flist;
609 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments"));
611 /* Fill fragments list. */
612 for (i = 0; i < nseg; i++) {
613 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
614 flist->frag[i].fraglen = segs[i].ds_len;
615 flist->frag[i].fragaddr = segs[i].ds_addr;
617 flist->numfrags = nseg;
621 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
622 bus_size_t mapsize, int error)
624 struct epic_rx_desc *desc;
629 KASSERT(nseg == 1, ("too many DMA segments"));
631 desc->bufaddr = segs->ds_addr;
635 * This is if_start handler. It takes mbufs from if_snd queue
636 * and queue them for transmit, one by one, until TX ring become full
637 * or queue become empty.
643 epic_softc_t *sc = ifp->if_softc;
644 struct epic_tx_buffer *buf;
645 struct epic_tx_desc *desc;
646 struct epic_frag_list *flist;
650 while (sc->pending_txs < TX_RING_SIZE) {
651 buf = sc->tx_buffer + sc->cur_tx;
652 desc = sc->tx_desc + sc->cur_tx;
653 flist = sc->tx_flist + sc->cur_tx;
655 /* Get next packet to send. */
656 IF_DEQUEUE(&ifp->if_snd, m0);
658 /* If nothing to send, return. */
662 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
663 epic_dma_map_txbuf, flist, 0);
665 if (error && error != EFBIG) {
672 * If packet was more than EPIC_MAX_FRAGS parts,
673 * recopy packet to a newly allocated mbuf cluster.
676 m = m_defrag(m0, M_DONTWAIT);
685 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
686 epic_dma_map_txbuf, flist, 0);
693 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
697 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
698 desc->control = 0x01;
700 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
701 desc->status = 0x8000;
702 bus_dmamap_sync(sc->ttag, sc->tmap,
703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
704 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
705 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
707 /* Set watchdog timer. */
713 ifp->if_flags |= IFF_OACTIVE;
717 * Synopsis: Finish all received frames.
723 struct ifnet *ifp = &sc->sc_if;
725 struct epic_rx_buffer *buf;
726 struct epic_rx_desc *desc;
731 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD);
732 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
733 buf = sc->rx_buffer + sc->cur_rx;
734 desc = sc->rx_desc + sc->cur_rx;
736 /* Switch to next descriptor. */
737 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK;
740 * Check for RX errors. This should only happen if
741 * SAVE_ERRORED_PACKETS is set. RX errors generate
742 * RXE interrupt usually.
744 if ((desc->status & 1) == 0) {
746 desc->status = 0x8000;
750 /* Save packet length and mbuf contained packet. */
751 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
752 len = desc->rxlength - ETHER_CRC_LEN;
755 /* Try to get an mbuf cluster. */
756 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
757 if (buf->mbuf == NULL) {
759 desc->status = 0x8000;
763 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
764 m_adj(buf->mbuf, ETHER_ALIGN);
766 /* Point to new mbuf, and give descriptor to chip. */
767 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf,
768 epic_dma_map_rxbuf, desc, 0);
771 desc->status = 0x8000;
776 desc->status = 0x8000;
777 bus_dmamap_unload(sc->mtag, buf->map);
779 buf->map = sc->sparemap;
781 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
783 /* First mbuf in packet holds the ethernet and packet headers */
784 m->m_pkthdr.rcvif = ifp;
785 m->m_pkthdr.len = m->m_len = len;
787 /* Give mbuf to OS. */
788 (*ifp->if_input)(ifp, m);
790 /* Successfuly received frame */
793 bus_dmamap_sync(sc->rtag, sc->rmap,
794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
798 * Synopsis: Do last phase of transmission. I.e. if desc is
799 * transmitted, decrease pending_txs counter, free mbuf contained
800 * packet, switch to next descriptor and repeat until no packets
801 * are pending or descriptor is not transmitted yet.
807 struct epic_tx_buffer *buf;
808 struct epic_tx_desc *desc;
811 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD);
812 while (sc->pending_txs > 0) {
813 buf = sc->tx_buffer + sc->dirty_tx;
814 desc = sc->tx_desc + sc->dirty_tx;
815 status = desc->status;
818 * If packet is not transmitted, thou followed
819 * packets are not transmitted too.
824 /* Packet is transmitted. Switch to next and free mbuf. */
826 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
827 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
828 bus_dmamap_unload(sc->mtag, buf->map);
832 /* Check for errors and collisions. */
834 sc->sc_if.if_opackets++;
836 sc->sc_if.if_oerrors++;
837 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
839 if ((status & 0x1001) == 0x1001)
840 device_printf(sc->dev,
841 "Tx ERROR: excessive coll. number\n");
845 if (sc->pending_txs < TX_RING_SIZE)
846 sc->sc_if.if_flags &= ~IFF_OACTIVE;
847 bus_dmamap_sync(sc->ttag, sc->tmap,
848 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
863 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
864 CSR_WRITE_4(sc, INTSTAT, status);
866 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
868 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
870 if (status & INTSTAT_OVW)
871 device_printf(sc->dev, "RX buffer overflow\n");
872 if (status & INTSTAT_RQE)
873 device_printf(sc->dev, "RX FIFO overflow\n");
875 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
876 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
877 sc->sc_if.if_ierrors++;
881 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
883 if (sc->sc_if.if_snd.ifq_head != NULL)
884 epic_ifstart(&sc->sc_if);
887 /* Check for rare errors */
888 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
889 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
890 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
891 INTSTAT_APE|INTSTAT_DPE)) {
892 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
893 (status & INTSTAT_PMA) ? "PMA " : "",
894 (status & INTSTAT_PTA) ? "PTA " : "",
895 (status & INTSTAT_APE) ? "APE " : "",
896 (status & INTSTAT_DPE) ? "DPE" : "");
903 if (status & INTSTAT_RXE) {
905 device_printf(sc->dev, "CRC/Alignment error\n");
907 sc->sc_if.if_ierrors++;
910 if (status & INTSTAT_TXU) {
911 epic_tx_underrun(sc);
912 sc->sc_if.if_oerrors++;
917 /* If no packets are pending, then no timeouts. */
918 if (sc->pending_txs == 0)
919 sc->sc_if.if_timer = 0;
923 * Handle the TX underrun error: increase the TX threshold
924 * and restart the transmitter.
930 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
931 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
933 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
936 sc->tx_threshold += 0x40;
938 device_printf(sc->dev,
939 "Tx UNDERRUN: TX threshold increased to %d\n",
944 /* We must set TXUGO to reset the stuck transmitter. */
945 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
947 /* Update the TX threshold */
948 epic_stop_activity(sc);
949 epic_set_tx_mode(sc);
950 epic_start_activity(sc);
954 * Synopsis: This one is called if packets wasn't transmitted
955 * during timeout. Try to deallocate transmitted packets, and
956 * if success continue to work.
968 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
970 /* Try to finish queued packets. */
973 /* If not successful. */
974 if (sc->pending_txs > 0) {
975 ifp->if_oerrors += sc->pending_txs;
977 /* Reinitialize board. */
978 device_printf(sc->dev, "reinitialization\n");
982 device_printf(sc->dev, "seems we can continue normaly\n");
985 if (ifp->if_snd.ifq_head)
992 * Despite the name of this function, it doesn't update statistics, it only
993 * helps in autonegotiation process.
996 epic_stats_update(epic_softc_t * sc)
998 struct mii_data * mii;
1003 mii = device_get_softc(sc->miibus);
1006 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1012 * Set media options.
1015 epic_ifmedia_upd(ifp)
1019 struct mii_data *mii;
1020 struct ifmedia *ifm;
1021 struct mii_softc *miisc;
1025 mii = device_get_softc(sc->miibus);
1026 ifm = &mii->mii_media;
1027 media = ifm->ifm_cur->ifm_media;
1029 /* Do not do anything if interface is not up. */
1030 if ((ifp->if_flags & IFF_UP) == 0)
1034 * Lookup current selected PHY.
1036 if (IFM_INST(media) == sc->serinst) {
1037 sc->phyid = EPIC_SERIAL;
1040 /* If we're not selecting serial interface, select MII mode. */
1041 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1042 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1044 /* Default to unknown PHY. */
1045 sc->phyid = EPIC_UNKN_PHY;
1047 /* Lookup selected PHY. */
1048 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1049 miisc = LIST_NEXT(miisc, mii_list)) {
1050 if (IFM_INST(media) == miisc->mii_inst) {
1056 /* Identify selected PHY. */
1058 int id1, id2, model, oui;
1060 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1061 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1063 oui = MII_OUI(id1, id2);
1064 model = MII_MODEL(id2);
1066 case MII_OUI_QUALSEMI:
1067 if (model == MII_MODEL_QUALSEMI_QS6612)
1068 sc->phyid = EPIC_QS6612_PHY;
1070 case MII_OUI_xxALTIMA:
1071 if (model == MII_MODEL_xxALTIMA_AC101)
1072 sc->phyid = EPIC_AC101_PHY;
1074 case MII_OUI_xxLEVEL1:
1075 if (model == MII_MODEL_xxLEVEL1_LXT970)
1076 sc->phyid = EPIC_LXT970_PHY;
1083 * Do PHY specific card setup.
1087 * Call this, to isolate all not selected PHYs and
1092 /* Do our own setup. */
1093 switch (sc->phyid) {
1094 case EPIC_QS6612_PHY:
1096 case EPIC_AC101_PHY:
1097 /* We have to powerup fiber tranceivers. */
1098 if (IFM_SUBTYPE(media) == IFM_100_FX)
1099 sc->miicfg |= MIICFG_694_ENABLE;
1101 sc->miicfg &= ~MIICFG_694_ENABLE;
1102 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1105 case EPIC_LXT970_PHY:
1106 /* We have to powerup fiber tranceivers. */
1107 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1108 if (IFM_SUBTYPE(media) == IFM_100_FX)
1109 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1111 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1112 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1116 /* Select serial PHY (10base2/BNC usually). */
1117 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1118 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1120 /* There is no driver to fill this. */
1121 mii->mii_media_active = media;
1122 mii->mii_media_status = 0;
1125 * We need to call this manually as it wasn't called
1126 * in mii_mediachg().
1128 epic_miibus_statchg(sc->dev);
1131 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1139 * Report current media status.
1142 epic_ifmedia_sts(ifp, ifmr)
1144 struct ifmediareq *ifmr;
1147 struct mii_data *mii;
1148 struct ifmedia *ifm;
1151 mii = device_get_softc(sc->miibus);
1152 ifm = &mii->mii_media;
1154 /* Nothing should be selected if interface is down. */
1155 if ((ifp->if_flags & IFF_UP) == 0) {
1156 ifmr->ifm_active = IFM_NONE;
1157 ifmr->ifm_status = 0;
1161 /* Call underlying pollstat, if not serial PHY. */
1162 if (sc->phyid != EPIC_SERIAL)
1165 /* Simply copy media info. */
1166 ifmr->ifm_active = mii->mii_media_active;
1167 ifmr->ifm_status = mii->mii_media_status;
1171 * Callback routine, called on media change.
1174 epic_miibus_statchg(dev)
1178 struct mii_data *mii;
1181 sc = device_get_softc(dev);
1182 mii = device_get_softc(sc->miibus);
1183 media = mii->mii_media_active;
1185 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1188 * If we are in full-duplex mode or loopback operation,
1189 * we need to decouple receiver and transmitter.
1191 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1192 sc->txcon |= TXCON_FULL_DUPLEX;
1194 /* On some cards we need manualy set fullduplex led. */
1195 if (sc->cardid == SMC9432FTX ||
1196 sc->cardid == SMC9432FTX_SC) {
1197 if (IFM_OPTIONS(media) & IFM_FDX)
1198 sc->miicfg |= MIICFG_694_ENABLE;
1200 sc->miicfg &= ~MIICFG_694_ENABLE;
1202 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1205 /* Update baudrate. */
1206 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1207 IFM_SUBTYPE(media) == IFM_100_FX)
1208 sc->sc_if.if_baudrate = 100000000;
1210 sc->sc_if.if_baudrate = 10000000;
1212 epic_stop_activity(sc);
1213 epic_set_tx_mode(sc);
1214 epic_start_activity(sc);
1218 epic_miibus_mediainit(dev)
1222 struct mii_data *mii;
1223 struct ifmedia *ifm;
1226 sc = device_get_softc(dev);
1227 mii = device_get_softc(sc->miibus);
1228 ifm = &mii->mii_media;
1231 * Add Serial Media Interface if present, this applies to
1234 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1235 /* Store its instance. */
1236 sc->serinst = mii->mii_instance++;
1238 /* Add as 10base2/BNC media. */
1239 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1240 ifmedia_add(ifm, media, 0, NULL);
1242 /* Report to user. */
1243 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1248 * Reset chip and update media.
1254 epic_softc_t *sc = xsc;
1255 struct ifnet *ifp = &sc->sc_if;
1260 /* If interface is already running, then we need not do anything. */
1261 if (ifp->if_flags & IFF_RUNNING) {
1266 /* Soft reset the chip (we have to power up card before). */
1267 CSR_WRITE_4(sc, GENCTL, 0);
1268 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1271 * Reset takes 15 pci ticks which depends on PCI bus speed.
1272 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1277 CSR_WRITE_4(sc, GENCTL, 0);
1279 /* Workaround for Application Note 7-15 */
1280 for (i = 0; i < 16; i++)
1281 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1283 /* Give rings to EPIC */
1284 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1285 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1287 /* Put node address to EPIC. */
1288 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1289 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1290 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1292 /* Set tx mode, includeing transmit threshold. */
1293 epic_set_tx_mode(sc);
1295 /* Compute and set RXCON. */
1296 epic_set_rx_mode(sc);
1298 /* Set multicast table. */
1299 epic_set_mc_table(sc);
1301 /* Enable interrupts by setting the interrupt mask. */
1302 CSR_WRITE_4(sc, INTMASK,
1303 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1304 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1307 /* Acknowledge all pending interrupts. */
1308 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1310 /* Enable interrupts, set for PCI read multiple and etc */
1311 CSR_WRITE_4(sc, GENCTL,
1312 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1313 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1315 /* Mark interface running ... */
1316 if (ifp->if_flags & IFF_UP)
1317 ifp->if_flags |= IFF_RUNNING;
1319 ifp->if_flags &= ~IFF_RUNNING;
1322 ifp->if_flags &= ~IFF_OACTIVE;
1324 /* Start Rx process */
1325 epic_start_activity(sc);
1327 /* Set appropriate media */
1328 epic_ifmedia_upd(ifp);
1330 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1336 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1340 epic_set_rx_mode(sc)
1346 flags = sc->sc_if.if_flags;
1347 rxcon = RXCON_DEFAULT;
1349 #ifdef EPIC_EARLY_RX
1350 rxcon |= RXCON_EARLY_RX;
1353 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1355 CSR_WRITE_4(sc, RXCON, rxcon);
1359 * Synopsis: Set transmit control register. Chip must be in idle state to
1363 epic_set_tx_mode(sc)
1367 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1368 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1370 CSR_WRITE_4(sc, TXCON, sc->txcon);
1374 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1375 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch
1376 * individual frames, multicast filter must be manually programmed).
1378 * Note: EPIC must be in idle state.
1381 epic_set_mc_table(sc)
1385 struct ifmultiaddr *ifma;
1386 u_int16_t filter[4];
1390 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1391 CSR_WRITE_4(sc, MC0, 0xFFFF);
1392 CSR_WRITE_4(sc, MC1, 0xFFFF);
1393 CSR_WRITE_4(sc, MC2, 0xFFFF);
1394 CSR_WRITE_4(sc, MC3, 0xFFFF);
1403 #if __FreeBSD_version < 500000
1404 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1406 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1408 if (ifma->ifma_addr->sa_family != AF_LINK)
1410 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1411 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1412 filter[h >> 4] |= 1 << (h & 0xF);
1415 CSR_WRITE_4(sc, MC0, filter[0]);
1416 CSR_WRITE_4(sc, MC1, filter[1]);
1417 CSR_WRITE_4(sc, MC2, filter[2]);
1418 CSR_WRITE_4(sc, MC3, filter[3]);
1423 * Synopsis: Start receive process and transmit one, if they need.
1426 epic_start_activity(sc)
1430 /* Start rx process. */
1431 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1432 (sc->pending_txs ? COMMAND_TXQUEUED : 0));
1436 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1437 * packet needs to be queued to stop Tx DMA.
1440 epic_stop_activity(sc)
1445 /* Stop Tx and Rx DMA. */
1446 CSR_WRITE_4(sc, COMMAND,
1447 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1449 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */
1450 for (i = 0; i < 0x1000; i++) {
1451 status = CSR_READ_4(sc, INTSTAT) &
1452 (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1453 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1458 /* Catch all finished packets. */
1462 status = CSR_READ_4(sc, INTSTAT);
1464 if ((status & INTSTAT_RXIDLE) == 0)
1465 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1467 if ((status & INTSTAT_TXIDLE) == 0)
1468 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1471 * May need to queue one more packet if TQE, this is rare
1472 * but existing case.
1474 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1475 (void)epic_queue_last_packet(sc);
1479 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1480 * a packet from current descriptor will be copied to internal RAM. We
1481 * compose a dummy packet here and queue it for transmission.
1483 * XXX the packet will then be actually sent over network...
1486 epic_queue_last_packet(sc)
1489 struct epic_tx_desc *desc;
1490 struct epic_frag_list *flist;
1491 struct epic_tx_buffer *buf;
1495 device_printf(sc->dev, "queue last packet\n");
1497 desc = sc->tx_desc + sc->cur_tx;
1498 flist = sc->tx_flist + sc->cur_tx;
1499 buf = sc->tx_buffer + sc->cur_tx;
1501 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1504 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1509 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN);
1510 m0->m_pkthdr.len = m0->m_len;
1511 m0->m_pkthdr.rcvif = &sc->sc_if;
1512 bzero(mtod(m0, caddr_t), m0->m_len);
1514 /* Fill fragments list. */
1515 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
1516 epic_dma_map_txbuf, flist, 0);
1521 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
1523 /* Fill in descriptor. */
1526 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1527 desc->control = 0x01;
1528 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
1529 desc->status = 0x8000;
1530 bus_dmamap_sync(sc->ttag, sc->tmap,
1531 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1532 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1534 /* Launch transmission. */
1535 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1537 /* Wait Tx DMA to stop (for how long??? XXX) */
1538 for (i = 0; i < 1000; i++) {
1539 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1544 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1545 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1553 * Synopsis: Shut down board and deallocates rings.
1563 sc->sc_if.if_timer = 0;
1565 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch);
1567 /* Disable interrupts */
1568 CSR_WRITE_4(sc, INTMASK, 0);
1569 CSR_WRITE_4(sc, GENCTL, 0);
1571 /* Try to stop Rx and TX processes */
1572 epic_stop_activity(sc);
1575 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1578 /* Make chip go to bed */
1579 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1581 /* Mark as stoped */
1582 sc->sc_if.if_flags &= ~IFF_RUNNING;
1588 * Synopsis: This function should free all memory allocated for rings.
1596 for (i = 0; i < RX_RING_SIZE; i++) {
1597 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1598 struct epic_rx_desc *desc = sc->rx_desc + i;
1601 desc->buflength = 0;
1605 bus_dmamap_unload(sc->mtag, buf->map);
1606 bus_dmamap_destroy(sc->mtag, buf->map);
1612 if (sc->sparemap != NULL)
1613 bus_dmamap_destroy(sc->mtag, sc->sparemap);
1615 for (i = 0; i < TX_RING_SIZE; i++) {
1616 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1617 struct epic_tx_desc *desc = sc->tx_desc + i;
1620 desc->buflength = 0;
1624 bus_dmamap_unload(sc->mtag, buf->map);
1625 bus_dmamap_destroy(sc->mtag, buf->map);
1633 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1634 * Point Tx descs to fragment lists. Check that all descs and fraglists
1635 * are bounded and aligned properly.
1643 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1645 /* Initialize the RX descriptor ring. */
1646 for (i = 0; i < RX_RING_SIZE; i++) {
1647 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1648 struct epic_rx_desc *desc = sc->rx_desc + i;
1650 desc->status = 0; /* Owned by driver */
1651 desc->next = sc->rx_addr +
1652 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc);
1654 if ((desc->next & 3) ||
1655 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1656 epic_free_rings(sc);
1660 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1661 if (buf->mbuf == NULL) {
1662 epic_free_rings(sc);
1665 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1666 m_adj(buf->mbuf, ETHER_ALIGN);
1668 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1670 epic_free_rings(sc);
1673 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1674 epic_dma_map_rxbuf, desc, 0);
1676 epic_free_rings(sc);
1679 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1681 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */
1682 desc->status = 0x8000; /* Set owner bit to NIC */
1684 bus_dmamap_sync(sc->rtag, sc->rmap,
1685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1687 /* Create the spare DMA map. */
1688 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap);
1690 epic_free_rings(sc);
1694 /* Initialize the TX descriptor ring. */
1695 for (i = 0; i < TX_RING_SIZE; i++) {
1696 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1697 struct epic_tx_desc *desc = sc->tx_desc + i;
1700 desc->next = sc->tx_addr +
1701 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc);
1703 if ((desc->next & 3) ||
1704 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1705 epic_free_rings(sc);
1710 desc->bufaddr = sc->frag_addr +
1711 i * sizeof(struct epic_frag_list);
1713 if ((desc->bufaddr & 3) ||
1714 ((desc->bufaddr & PAGE_MASK) +
1715 sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1716 epic_free_rings(sc);
1720 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1722 epic_free_rings(sc);
1726 bus_dmamap_sync(sc->ttag, sc->tmap,
1727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1728 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1734 * EEPROM operation functions
1737 epic_write_eepromreg(sc, val)
1743 CSR_WRITE_1(sc, EECTL, val);
1745 for (i = 0; i < 0xFF; i++) {
1746 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0)
1752 epic_read_eepromreg(sc)
1756 return (CSR_READ_1(sc, EECTL));
1760 epic_eeprom_clock(sc, val)
1765 epic_write_eepromreg(sc, val);
1766 epic_write_eepromreg(sc, (val | 0x4));
1767 epic_write_eepromreg(sc, val);
1769 return (epic_read_eepromreg(sc));
1773 epic_output_eepromw(sc, val)
1779 for (i = 0xF; i >= 0; i--) {
1781 epic_eeprom_clock(sc, 0x0B);
1783 epic_eeprom_clock(sc, 0x03);
1788 epic_input_eepromw(sc)
1791 u_int16_t retval = 0;
1794 for (i = 0xF; i >= 0; i--) {
1795 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1803 epic_read_eeprom(sc, loc)
1810 epic_write_eepromreg(sc, 3);
1812 if (epic_read_eepromreg(sc) & 0x40)
1813 read_cmd = (loc & 0x3F) | 0x180;
1815 read_cmd = (loc & 0xFF) | 0x600;
1817 epic_output_eepromw(sc, read_cmd);
1819 dataval = epic_input_eepromw(sc);
1821 epic_write_eepromreg(sc, 1);
1827 * Here goes MII read/write routines.
1830 epic_read_phy_reg(sc, phy, reg)
1836 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1838 for (i = 0; i < 0x100; i++) {
1839 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1844 return (CSR_READ_4(sc, MIIDATA));
1848 epic_write_phy_reg(sc, phy, reg, val)
1854 CSR_WRITE_4(sc, MIIDATA, val);
1855 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1857 for(i = 0; i < 0x100; i++) {
1858 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0)
1865 epic_miibus_readreg(dev, phy, reg)
1871 sc = device_get_softc(dev);
1873 return (PHY_READ_2(sc, phy, reg));
1877 epic_miibus_writereg(dev, phy, reg, data)
1883 sc = device_get_softc(dev);
1885 PHY_WRITE_2(sc, phy, reg, data);