2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
60 #include <net/if_vlan_var.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
64 #include <machine/clock.h> /* for DELAY */
68 #include <dev/pci/pcireg.h>
69 #include <dev/pci/pcivar.h>
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
75 #include <dev/mii/lxtphyreg.h>
77 #include "miibus_if.h"
79 #include <dev/tx/if_txreg.h>
80 #include <dev/tx/if_txvar.h>
82 MODULE_DEPEND(tx, pci, 1, 1, 1);
83 MODULE_DEPEND(tx, ether, 1, 1, 1);
84 MODULE_DEPEND(tx, miibus, 1, 1, 1);
86 static int epic_ifioctl(struct ifnet *, u_long, caddr_t);
87 static void epic_intr(void *);
88 static void epic_tx_underrun(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifwatchdog(struct ifnet *);
91 static void epic_stats_update(epic_softc_t *);
92 static void epic_init(void *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
105 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
106 static u_int16_t epic_input_eepromw(epic_softc_t *);
107 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
108 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
109 static u_int8_t epic_read_eepromreg(epic_softc_t *);
111 static int epic_read_phy_reg(epic_softc_t *, int, int);
112 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
114 static int epic_miibus_readreg(device_t, int, int);
115 static int epic_miibus_writereg(device_t, int, int, int);
116 static void epic_miibus_statchg(device_t);
117 static void epic_miibus_mediainit(device_t);
119 static int epic_ifmedia_upd(struct ifnet *);
120 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
122 static int epic_probe(device_t);
123 static int epic_attach(device_t);
124 static void epic_shutdown(device_t);
125 static int epic_detach(device_t);
126 static void epic_release(epic_softc_t *);
127 static struct epic_type *epic_devtype(device_t);
129 static device_method_t epic_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, epic_probe),
132 DEVMETHOD(device_attach, epic_attach),
133 DEVMETHOD(device_detach, epic_detach),
134 DEVMETHOD(device_shutdown, epic_shutdown),
137 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
138 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
139 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
140 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
145 static driver_t epic_driver = {
151 static devclass_t epic_devclass;
153 DRIVER_MODULE(tx, pci, epic_driver, epic_devclass, 0, 0);
154 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
156 static struct epic_type epic_devs[] = {
157 { SMC_VENDORID, SMC_DEVICEID_83C170, "SMC EtherPower II 10/100" },
167 t = epic_devtype(dev);
170 device_set_desc(dev, t->name);
171 return (BUS_PROBE_DEFAULT);
177 static struct epic_type *
185 while (t->name != NULL) {
186 if ((pci_get_vendor(dev) == t->ven_id) &&
187 (pci_get_device(dev) == t->dev_id)) {
195 #ifdef EPIC_USEIOSPACE
196 #define EPIC_RES SYS_RES_IOPORT
197 #define EPIC_RID PCIR_BASEIO
199 #define EPIC_RES SYS_RES_MEMORY
200 #define EPIC_RID PCIR_BASEMEM
204 epic_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
211 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
213 *addr = segs->ds_addr;
217 * Attach routine: map registers, allocate softc, rings and descriptors.
218 * Reset to known state.
232 sc = device_get_softc(dev);
233 unit = device_get_unit(dev);
235 /* Preinitialize softc structure. */
239 /* Fill ifnet structure. */
240 ifp = sc->ifp = if_alloc(IFT_ETHER);
242 device_printf(dev, "can not if_alloc()\n");
246 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
248 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST|IFF_NEEDSGIANT;
249 ifp->if_ioctl = epic_ifioctl;
250 ifp->if_start = epic_ifstart;
251 ifp->if_watchdog = epic_ifwatchdog;
252 ifp->if_init = epic_init;
254 ifp->if_baudrate = 10000000;
255 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
257 /* Enable busmastering. */
258 pci_enable_busmaster(dev);
261 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
262 if (sc->res == NULL) {
263 device_printf(dev, "couldn't map ports/memory\n");
268 sc->sc_st = rman_get_bustag(sc->res);
269 sc->sc_sh = rman_get_bushandle(sc->res);
271 /* Allocate interrupt. */
273 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
274 RF_SHAREABLE | RF_ACTIVE);
275 if (sc->irq == NULL) {
276 device_printf(dev, "couldn't map interrupt\n");
281 /* Allocate DMA tags. */
282 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
283 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * EPIC_MAX_FRAGS,
284 EPIC_MAX_FRAGS, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->mtag);
286 device_printf(dev, "couldn't allocate dma tag\n");
290 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
291 BUS_SPACE_MAXADDR, NULL, NULL,
292 sizeof(struct epic_rx_desc) * RX_RING_SIZE,
293 1, sizeof(struct epic_rx_desc) * RX_RING_SIZE, 0, busdma_lock_mutex,
296 device_printf(dev, "couldn't allocate dma tag\n");
300 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
301 BUS_SPACE_MAXADDR, NULL, NULL,
302 sizeof(struct epic_tx_desc) * TX_RING_SIZE,
303 1, sizeof(struct epic_tx_desc) * TX_RING_SIZE, 0,
304 busdma_lock_mutex, &Giant, &sc->ttag);
306 device_printf(dev, "couldn't allocate dma tag\n");
310 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
311 BUS_SPACE_MAXADDR, NULL, NULL,
312 sizeof(struct epic_frag_list) * TX_RING_SIZE,
313 1, sizeof(struct epic_frag_list) * TX_RING_SIZE, 0,
314 busdma_lock_mutex, &Giant, &sc->ftag);
316 device_printf(dev, "couldn't allocate dma tag\n");
320 /* Allocate DMA safe memory and get the DMA addresses. */
321 error = bus_dmamem_alloc(sc->ftag, (void **)&sc->tx_flist,
322 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fmap);
324 device_printf(dev, "couldn't allocate dma memory\n");
327 error = bus_dmamap_load(sc->ftag, sc->fmap, sc->tx_flist,
328 sizeof(struct epic_frag_list) * TX_RING_SIZE, epic_dma_map_addr,
331 device_printf(dev, "couldn't map dma memory\n");
334 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
335 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tmap);
337 device_printf(dev, "couldn't allocate dma memory\n");
340 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
341 sizeof(struct epic_tx_desc) * TX_RING_SIZE, epic_dma_map_addr,
344 device_printf(dev, "couldn't map dma memory\n");
347 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
348 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rmap);
350 device_printf(dev, "couldn't allocate dma memory\n");
353 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
354 sizeof(struct epic_rx_desc) * RX_RING_SIZE, epic_dma_map_addr,
357 device_printf(dev, "couldn't map dma memory\n");
361 /* Bring the chip out of low-power mode. */
362 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
365 /* Workaround for Application Note 7-15. */
366 for (i = 0; i < 16; i++)
367 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
369 /* Read MAC address from EEPROM. */
370 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
371 ((u_int16_t *)eaddr)[i] = epic_read_eeprom(sc,i);
373 /* Set Non-Volatile Control Register from EEPROM. */
374 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
377 sc->tx_threshold = TRANSMIT_THRESHOLD;
378 sc->txcon = TXCON_DEFAULT;
379 sc->miicfg = MIICFG_SMI_ENABLE;
380 sc->phyid = EPIC_UNKN_PHY;
384 sc->cardvend = pci_read_config(dev, PCIR_SUBVEND_0, 2);
385 sc->cardid = pci_read_config(dev, PCIR_SUBDEV_0, 2);
387 if (sc->cardvend != SMC_VENDORID)
388 device_printf(dev, "unknown card vendor %04xh\n", sc->cardvend);
390 /* Do ifmedia setup. */
391 if (mii_phy_probe(dev, &sc->miibus,
392 epic_ifmedia_upd, epic_ifmedia_sts)) {
393 device_printf(dev, "ERROR! MII without any PHY!?\n");
398 /* board type and ... */
400 for(i = 0x2c; i < 0x32; i++) {
401 tmp = epic_read_eeprom(sc, i);
402 if (' ' == (u_int8_t)tmp)
404 printf("%c", (u_int8_t)tmp);
406 if (' ' == (u_int8_t)tmp)
408 printf("%c", (u_int8_t)tmp);
412 /* Initialize rings. */
413 if (epic_init_rings(sc)) {
414 device_printf(dev, "failed to init rings\n");
419 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
420 ifp->if_capabilities |= IFCAP_VLAN_MTU;
421 ifp->if_capenable |= IFCAP_VLAN_MTU;
422 callout_handle_init(&sc->stat_ch);
424 /* Activate our interrupt handler. */
425 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
426 epic_intr, sc, &sc->sc_ih);
428 device_printf(dev, "couldn't set up irq\n");
432 /* Attach to OS's managers. */
433 ether_ifattach(ifp, eaddr);
444 * Free any resources allocated by the driver.
447 epic_release(epic_softc_t *sc)
453 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
455 bus_release_resource(sc->dev, EPIC_RES, EPIC_RID, sc->res);
458 bus_dmamap_unload(sc->ftag, sc->fmap);
459 bus_dmamem_free(sc->ftag, sc->tx_flist, sc->fmap);
460 bus_dmamap_destroy(sc->ftag, sc->fmap);
463 bus_dmamap_unload(sc->ttag, sc->tmap);
464 bus_dmamem_free(sc->ttag, sc->tx_desc, sc->tmap);
465 bus_dmamap_destroy(sc->ttag, sc->tmap);
468 bus_dmamap_unload(sc->rtag, sc->rmap);
469 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
470 bus_dmamap_destroy(sc->rtag, sc->rmap);
473 bus_dma_tag_destroy(sc->mtag);
475 bus_dma_tag_destroy(sc->ftag);
477 bus_dma_tag_destroy(sc->ttag);
479 bus_dma_tag_destroy(sc->rtag);
483 * Detach driver and free resources.
495 sc = device_get_softc(dev);
502 bus_generic_detach(dev);
503 device_delete_child(dev, sc->miibus);
505 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
515 * Stop all chip I/O so that the kernel's probe routines don't
516 * get confused by errant DMAs when rebooting.
524 sc = device_get_softc(dev);
530 * This is if_ioctl handler.
533 epic_ifioctl(ifp, command, data)
538 epic_softc_t *sc = ifp->if_softc;
539 struct mii_data *mii;
540 struct ifreq *ifr = (struct ifreq *) data;
547 if (ifp->if_mtu == ifr->ifr_mtu)
550 /* XXX Though the datasheet doesn't imply any
551 * limitations on RX and TX sizes beside max 64Kb
552 * DMA transfer, seems we can't send more then 1600
553 * data bytes per ethernet packet (transmitter hangs
554 * up if more data is sent).
556 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
557 ifp->if_mtu = ifr->ifr_mtu;
566 * If the interface is marked up and stopped, then start it.
567 * If it is marked down and running, then stop it.
569 if (ifp->if_flags & IFF_UP) {
570 if ((ifp->if_flags & IFF_RUNNING) == 0) {
575 if (ifp->if_flags & IFF_RUNNING) {
581 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
582 epic_stop_activity(sc);
583 epic_set_mc_table(sc);
584 epic_set_rx_mode(sc);
585 epic_start_activity(sc);
590 epic_set_mc_table(sc);
596 mii = device_get_softc(sc->miibus);
597 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
601 error = ether_ioctl(ifp, command, data);
609 epic_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
610 bus_size_t mapsize, int error)
612 struct epic_frag_list *flist;
618 KASSERT(nseg <= EPIC_MAX_FRAGS, ("too many DMA segments"));
620 /* Fill fragments list. */
621 for (i = 0; i < nseg; i++) {
622 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
623 flist->frag[i].fraglen = segs[i].ds_len;
624 flist->frag[i].fragaddr = segs[i].ds_addr;
626 flist->numfrags = nseg;
630 epic_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
631 bus_size_t mapsize, int error)
633 struct epic_rx_desc *desc;
638 KASSERT(nseg == 1, ("too many DMA segments"));
640 desc->bufaddr = segs->ds_addr;
644 * This is if_start handler. It takes mbufs from if_snd queue
645 * and queue them for transmit, one by one, until TX ring become full
646 * or queue become empty.
652 epic_softc_t *sc = ifp->if_softc;
653 struct epic_tx_buffer *buf;
654 struct epic_tx_desc *desc;
655 struct epic_frag_list *flist;
659 while (sc->pending_txs < TX_RING_SIZE) {
660 buf = sc->tx_buffer + sc->cur_tx;
661 desc = sc->tx_desc + sc->cur_tx;
662 flist = sc->tx_flist + sc->cur_tx;
664 /* Get next packet to send. */
665 IF_DEQUEUE(&ifp->if_snd, m0);
667 /* If nothing to send, return. */
671 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
672 epic_dma_map_txbuf, flist, 0);
674 if (error && error != EFBIG) {
681 * If packet was more than EPIC_MAX_FRAGS parts,
682 * recopy packet to a newly allocated mbuf cluster.
685 m = m_defrag(m0, M_DONTWAIT);
694 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
695 epic_dma_map_txbuf, flist, 0);
702 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
706 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
707 desc->control = 0x01;
709 max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
710 desc->status = 0x8000;
711 bus_dmamap_sync(sc->ttag, sc->tmap,
712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
713 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
714 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
716 /* Set watchdog timer. */
722 ifp->if_flags |= IFF_OACTIVE;
726 * Synopsis: Finish all received frames.
732 struct ifnet *ifp = sc->ifp;
734 struct epic_rx_buffer *buf;
735 struct epic_rx_desc *desc;
740 bus_dmamap_sync(sc->rtag, sc->rmap, BUS_DMASYNC_POSTREAD);
741 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
742 buf = sc->rx_buffer + sc->cur_rx;
743 desc = sc->rx_desc + sc->cur_rx;
745 /* Switch to next descriptor. */
746 sc->cur_rx = (sc->cur_rx + 1) & RX_RING_MASK;
749 * Check for RX errors. This should only happen if
750 * SAVE_ERRORED_PACKETS is set. RX errors generate
751 * RXE interrupt usually.
753 if ((desc->status & 1) == 0) {
755 desc->status = 0x8000;
759 /* Save packet length and mbuf contained packet. */
760 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
761 len = desc->rxlength - ETHER_CRC_LEN;
764 /* Try to get an mbuf cluster. */
765 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
766 if (buf->mbuf == NULL) {
768 desc->status = 0x8000;
772 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
773 m_adj(buf->mbuf, ETHER_ALIGN);
775 /* Point to new mbuf, and give descriptor to chip. */
776 error = bus_dmamap_load_mbuf(sc->mtag, sc->sparemap, buf->mbuf,
777 epic_dma_map_rxbuf, desc, 0);
780 desc->status = 0x8000;
785 desc->status = 0x8000;
786 bus_dmamap_unload(sc->mtag, buf->map);
788 buf->map = sc->sparemap;
790 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
792 /* First mbuf in packet holds the ethernet and packet headers */
793 m->m_pkthdr.rcvif = ifp;
794 m->m_pkthdr.len = m->m_len = len;
796 /* Give mbuf to OS. */
797 (*ifp->if_input)(ifp, m);
799 /* Successfuly received frame */
802 bus_dmamap_sync(sc->rtag, sc->rmap,
803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
807 * Synopsis: Do last phase of transmission. I.e. if desc is
808 * transmitted, decrease pending_txs counter, free mbuf contained
809 * packet, switch to next descriptor and repeat until no packets
810 * are pending or descriptor is not transmitted yet.
816 struct epic_tx_buffer *buf;
817 struct epic_tx_desc *desc;
820 bus_dmamap_sync(sc->ttag, sc->tmap, BUS_DMASYNC_POSTREAD);
821 while (sc->pending_txs > 0) {
822 buf = sc->tx_buffer + sc->dirty_tx;
823 desc = sc->tx_desc + sc->dirty_tx;
824 status = desc->status;
827 * If packet is not transmitted, thou followed
828 * packets are not transmitted too.
833 /* Packet is transmitted. Switch to next and free mbuf. */
835 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
836 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
837 bus_dmamap_unload(sc->mtag, buf->map);
841 /* Check for errors and collisions. */
843 sc->ifp->if_opackets++;
845 sc->ifp->if_oerrors++;
846 sc->ifp->if_collisions += (status >> 8) & 0x1F;
848 if ((status & 0x1001) == 0x1001)
849 device_printf(sc->dev,
850 "Tx ERROR: excessive coll. number\n");
854 if (sc->pending_txs < TX_RING_SIZE)
855 sc->ifp->if_flags &= ~IFF_OACTIVE;
856 bus_dmamap_sync(sc->ttag, sc->tmap,
857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
872 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
873 CSR_WRITE_4(sc, INTSTAT, status);
875 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
877 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
879 if (status & INTSTAT_OVW)
880 device_printf(sc->dev, "RX buffer overflow\n");
881 if (status & INTSTAT_RQE)
882 device_printf(sc->dev, "RX FIFO overflow\n");
884 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
885 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
886 sc->ifp->if_ierrors++;
890 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
892 if (sc->ifp->if_snd.ifq_head != NULL)
893 epic_ifstart(sc->ifp);
896 /* Check for rare errors */
897 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
898 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
899 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
900 INTSTAT_APE|INTSTAT_DPE)) {
901 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
902 (status & INTSTAT_PMA) ? "PMA " : "",
903 (status & INTSTAT_PTA) ? "PTA " : "",
904 (status & INTSTAT_APE) ? "APE " : "",
905 (status & INTSTAT_DPE) ? "DPE" : "");
912 if (status & INTSTAT_RXE) {
914 device_printf(sc->dev, "CRC/Alignment error\n");
916 sc->ifp->if_ierrors++;
919 if (status & INTSTAT_TXU) {
920 epic_tx_underrun(sc);
921 sc->ifp->if_oerrors++;
926 /* If no packets are pending, then no timeouts. */
927 if (sc->pending_txs == 0)
928 sc->ifp->if_timer = 0;
932 * Handle the TX underrun error: increase the TX threshold
933 * and restart the transmitter.
939 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
940 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
942 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
945 sc->tx_threshold += 0x40;
947 device_printf(sc->dev,
948 "Tx UNDERRUN: TX threshold increased to %d\n",
953 /* We must set TXUGO to reset the stuck transmitter. */
954 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
956 /* Update the TX threshold */
957 epic_stop_activity(sc);
958 epic_set_tx_mode(sc);
959 epic_start_activity(sc);
963 * Synopsis: This one is called if packets wasn't transmitted
964 * during timeout. Try to deallocate transmitted packets, and
965 * if success continue to work.
977 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
979 /* Try to finish queued packets. */
982 /* If not successful. */
983 if (sc->pending_txs > 0) {
984 ifp->if_oerrors += sc->pending_txs;
986 /* Reinitialize board. */
987 device_printf(sc->dev, "reinitialization\n");
991 device_printf(sc->dev, "seems we can continue normaly\n");
994 if (ifp->if_snd.ifq_head)
1001 * Despite the name of this function, it doesn't update statistics, it only
1002 * helps in autonegotiation process.
1005 epic_stats_update(epic_softc_t * sc)
1007 struct mii_data * mii;
1012 mii = device_get_softc(sc->miibus);
1015 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1021 * Set media options.
1024 epic_ifmedia_upd(ifp)
1028 struct mii_data *mii;
1029 struct ifmedia *ifm;
1030 struct mii_softc *miisc;
1034 mii = device_get_softc(sc->miibus);
1035 ifm = &mii->mii_media;
1036 media = ifm->ifm_cur->ifm_media;
1038 /* Do not do anything if interface is not up. */
1039 if ((ifp->if_flags & IFF_UP) == 0)
1043 * Lookup current selected PHY.
1045 if (IFM_INST(media) == sc->serinst) {
1046 sc->phyid = EPIC_SERIAL;
1049 /* If we're not selecting serial interface, select MII mode. */
1050 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1051 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1053 /* Default to unknown PHY. */
1054 sc->phyid = EPIC_UNKN_PHY;
1056 /* Lookup selected PHY. */
1057 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1058 miisc = LIST_NEXT(miisc, mii_list)) {
1059 if (IFM_INST(media) == miisc->mii_inst) {
1065 /* Identify selected PHY. */
1067 int id1, id2, model, oui;
1069 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1070 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1072 oui = MII_OUI(id1, id2);
1073 model = MII_MODEL(id2);
1075 case MII_OUI_QUALSEMI:
1076 if (model == MII_MODEL_QUALSEMI_QS6612)
1077 sc->phyid = EPIC_QS6612_PHY;
1079 case MII_OUI_xxALTIMA:
1080 if (model == MII_MODEL_xxALTIMA_AC101)
1081 sc->phyid = EPIC_AC101_PHY;
1083 case MII_OUI_xxLEVEL1:
1084 if (model == MII_MODEL_xxLEVEL1_LXT970)
1085 sc->phyid = EPIC_LXT970_PHY;
1092 * Do PHY specific card setup.
1096 * Call this, to isolate all not selected PHYs and
1101 /* Do our own setup. */
1102 switch (sc->phyid) {
1103 case EPIC_QS6612_PHY:
1105 case EPIC_AC101_PHY:
1106 /* We have to powerup fiber tranceivers. */
1107 if (IFM_SUBTYPE(media) == IFM_100_FX)
1108 sc->miicfg |= MIICFG_694_ENABLE;
1110 sc->miicfg &= ~MIICFG_694_ENABLE;
1111 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1114 case EPIC_LXT970_PHY:
1115 /* We have to powerup fiber tranceivers. */
1116 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1117 if (IFM_SUBTYPE(media) == IFM_100_FX)
1118 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1120 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1121 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1125 /* Select serial PHY (10base2/BNC usually). */
1126 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1127 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1129 /* There is no driver to fill this. */
1130 mii->mii_media_active = media;
1131 mii->mii_media_status = 0;
1134 * We need to call this manually as it wasn't called
1135 * in mii_mediachg().
1137 epic_miibus_statchg(sc->dev);
1140 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1148 * Report current media status.
1151 epic_ifmedia_sts(ifp, ifmr)
1153 struct ifmediareq *ifmr;
1156 struct mii_data *mii;
1157 struct ifmedia *ifm;
1160 mii = device_get_softc(sc->miibus);
1161 ifm = &mii->mii_media;
1163 /* Nothing should be selected if interface is down. */
1164 if ((ifp->if_flags & IFF_UP) == 0) {
1165 ifmr->ifm_active = IFM_NONE;
1166 ifmr->ifm_status = 0;
1170 /* Call underlying pollstat, if not serial PHY. */
1171 if (sc->phyid != EPIC_SERIAL)
1174 /* Simply copy media info. */
1175 ifmr->ifm_active = mii->mii_media_active;
1176 ifmr->ifm_status = mii->mii_media_status;
1180 * Callback routine, called on media change.
1183 epic_miibus_statchg(dev)
1187 struct mii_data *mii;
1190 sc = device_get_softc(dev);
1191 mii = device_get_softc(sc->miibus);
1192 media = mii->mii_media_active;
1194 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1197 * If we are in full-duplex mode or loopback operation,
1198 * we need to decouple receiver and transmitter.
1200 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1201 sc->txcon |= TXCON_FULL_DUPLEX;
1203 /* On some cards we need manualy set fullduplex led. */
1204 if (sc->cardid == SMC9432FTX ||
1205 sc->cardid == SMC9432FTX_SC) {
1206 if (IFM_OPTIONS(media) & IFM_FDX)
1207 sc->miicfg |= MIICFG_694_ENABLE;
1209 sc->miicfg &= ~MIICFG_694_ENABLE;
1211 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1214 /* Update baudrate. */
1215 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1216 IFM_SUBTYPE(media) == IFM_100_FX)
1217 sc->ifp->if_baudrate = 100000000;
1219 sc->ifp->if_baudrate = 10000000;
1221 epic_stop_activity(sc);
1222 epic_set_tx_mode(sc);
1223 epic_start_activity(sc);
1227 epic_miibus_mediainit(dev)
1231 struct mii_data *mii;
1232 struct ifmedia *ifm;
1235 sc = device_get_softc(dev);
1236 mii = device_get_softc(sc->miibus);
1237 ifm = &mii->mii_media;
1240 * Add Serial Media Interface if present, this applies to
1243 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1244 /* Store its instance. */
1245 sc->serinst = mii->mii_instance++;
1247 /* Add as 10base2/BNC media. */
1248 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1249 ifmedia_add(ifm, media, 0, NULL);
1251 /* Report to user. */
1252 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1257 * Reset chip and update media.
1263 epic_softc_t *sc = xsc;
1264 struct ifnet *ifp = sc->ifp;
1269 /* If interface is already running, then we need not do anything. */
1270 if (ifp->if_flags & IFF_RUNNING) {
1275 /* Soft reset the chip (we have to power up card before). */
1276 CSR_WRITE_4(sc, GENCTL, 0);
1277 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1280 * Reset takes 15 pci ticks which depends on PCI bus speed.
1281 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1286 CSR_WRITE_4(sc, GENCTL, 0);
1288 /* Workaround for Application Note 7-15 */
1289 for (i = 0; i < 16; i++)
1290 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1292 /* Give rings to EPIC */
1293 CSR_WRITE_4(sc, PRCDAR, sc->rx_addr);
1294 CSR_WRITE_4(sc, PTCDAR, sc->tx_addr);
1296 /* Put node address to EPIC. */
1297 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)IFP2ENADDR(sc->ifp))[0]);
1298 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)IFP2ENADDR(sc->ifp))[1]);
1299 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)IFP2ENADDR(sc->ifp))[2]);
1301 /* Set tx mode, includeing transmit threshold. */
1302 epic_set_tx_mode(sc);
1304 /* Compute and set RXCON. */
1305 epic_set_rx_mode(sc);
1307 /* Set multicast table. */
1308 epic_set_mc_table(sc);
1310 /* Enable interrupts by setting the interrupt mask. */
1311 CSR_WRITE_4(sc, INTMASK,
1312 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1313 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1316 /* Acknowledge all pending interrupts. */
1317 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1319 /* Enable interrupts, set for PCI read multiple and etc */
1320 CSR_WRITE_4(sc, GENCTL,
1321 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1322 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1324 /* Mark interface running ... */
1325 if (ifp->if_flags & IFF_UP)
1326 ifp->if_flags |= IFF_RUNNING;
1328 ifp->if_flags &= ~IFF_RUNNING;
1331 ifp->if_flags &= ~IFF_OACTIVE;
1333 /* Start Rx process */
1334 epic_start_activity(sc);
1336 /* Set appropriate media */
1337 epic_ifmedia_upd(ifp);
1339 sc->stat_ch = timeout((timeout_t *)epic_stats_update, sc, hz);
1345 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1349 epic_set_rx_mode(sc)
1355 flags = sc->ifp->if_flags;
1356 rxcon = RXCON_DEFAULT;
1358 #ifdef EPIC_EARLY_RX
1359 rxcon |= RXCON_EARLY_RX;
1362 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1364 CSR_WRITE_4(sc, RXCON, rxcon);
1368 * Synopsis: Set transmit control register. Chip must be in idle state to
1372 epic_set_tx_mode(sc)
1376 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1377 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1379 CSR_WRITE_4(sc, TXCON, sc->txcon);
1383 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1384 * flags (note that setting PROMISC bit in EPIC's RXCON will only touch
1385 * individual frames, multicast filter must be manually programmed).
1387 * Note: EPIC must be in idle state.
1390 epic_set_mc_table(sc)
1394 struct ifmultiaddr *ifma;
1395 u_int16_t filter[4];
1399 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1400 CSR_WRITE_4(sc, MC0, 0xFFFF);
1401 CSR_WRITE_4(sc, MC1, 0xFFFF);
1402 CSR_WRITE_4(sc, MC2, 0xFFFF);
1403 CSR_WRITE_4(sc, MC3, 0xFFFF);
1412 #if __FreeBSD_version < 500000
1413 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1415 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1417 if (ifma->ifma_addr->sa_family != AF_LINK)
1419 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1420 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1421 filter[h >> 4] |= 1 << (h & 0xF);
1424 CSR_WRITE_4(sc, MC0, filter[0]);
1425 CSR_WRITE_4(sc, MC1, filter[1]);
1426 CSR_WRITE_4(sc, MC2, filter[2]);
1427 CSR_WRITE_4(sc, MC3, filter[3]);
1432 * Synopsis: Start receive process and transmit one, if they need.
1435 epic_start_activity(sc)
1439 /* Start rx process. */
1440 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED | COMMAND_START_RX |
1441 (sc->pending_txs ? COMMAND_TXQUEUED : 0));
1445 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1446 * packet needs to be queued to stop Tx DMA.
1449 epic_stop_activity(sc)
1454 /* Stop Tx and Rx DMA. */
1455 CSR_WRITE_4(sc, COMMAND,
1456 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1458 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX). */
1459 for (i = 0; i < 0x1000; i++) {
1460 status = CSR_READ_4(sc, INTSTAT) &
1461 (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1462 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1467 /* Catch all finished packets. */
1471 status = CSR_READ_4(sc, INTSTAT);
1473 if ((status & INTSTAT_RXIDLE) == 0)
1474 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1476 if ((status & INTSTAT_TXIDLE) == 0)
1477 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1480 * May need to queue one more packet if TQE, this is rare
1481 * but existing case.
1483 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1484 (void)epic_queue_last_packet(sc);
1488 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1489 * a packet from current descriptor will be copied to internal RAM. We
1490 * compose a dummy packet here and queue it for transmission.
1492 * XXX the packet will then be actually sent over network...
1495 epic_queue_last_packet(sc)
1498 struct epic_tx_desc *desc;
1499 struct epic_frag_list *flist;
1500 struct epic_tx_buffer *buf;
1504 device_printf(sc->dev, "queue last packet\n");
1506 desc = sc->tx_desc + sc->cur_tx;
1507 flist = sc->tx_flist + sc->cur_tx;
1508 buf = sc->tx_buffer + sc->cur_tx;
1510 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1513 MGETHDR(m0, M_DONTWAIT, MT_DATA);
1518 m0->m_len = min(MHLEN, ETHER_MIN_LEN - ETHER_CRC_LEN);
1519 m0->m_pkthdr.len = m0->m_len;
1520 m0->m_pkthdr.rcvif = sc->ifp;
1521 bzero(mtod(m0, caddr_t), m0->m_len);
1523 /* Fill fragments list. */
1524 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
1525 epic_dma_map_txbuf, flist, 0);
1530 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
1532 /* Fill in descriptor. */
1535 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1536 desc->control = 0x01;
1537 desc->txlength = max(m0->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
1538 desc->status = 0x8000;
1539 bus_dmamap_sync(sc->ttag, sc->tmap,
1540 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1541 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1543 /* Launch transmission. */
1544 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1546 /* Wait Tx DMA to stop (for how long??? XXX) */
1547 for (i = 0; i < 1000; i++) {
1548 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1553 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1554 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1562 * Synopsis: Shut down board and deallocates rings.
1572 sc->ifp->if_timer = 0;
1574 untimeout((timeout_t *)epic_stats_update, sc, sc->stat_ch);
1576 /* Disable interrupts */
1577 CSR_WRITE_4(sc, INTMASK, 0);
1578 CSR_WRITE_4(sc, GENCTL, 0);
1580 /* Try to stop Rx and TX processes */
1581 epic_stop_activity(sc);
1584 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1587 /* Make chip go to bed */
1588 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1590 /* Mark as stoped */
1591 sc->ifp->if_flags &= ~IFF_RUNNING;
1597 * Synopsis: This function should free all memory allocated for rings.
1605 for (i = 0; i < RX_RING_SIZE; i++) {
1606 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1607 struct epic_rx_desc *desc = sc->rx_desc + i;
1610 desc->buflength = 0;
1614 bus_dmamap_unload(sc->mtag, buf->map);
1615 bus_dmamap_destroy(sc->mtag, buf->map);
1621 if (sc->sparemap != NULL)
1622 bus_dmamap_destroy(sc->mtag, sc->sparemap);
1624 for (i = 0; i < TX_RING_SIZE; i++) {
1625 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1626 struct epic_tx_desc *desc = sc->tx_desc + i;
1629 desc->buflength = 0;
1633 bus_dmamap_unload(sc->mtag, buf->map);
1634 bus_dmamap_destroy(sc->mtag, buf->map);
1642 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1643 * Point Tx descs to fragment lists. Check that all descs and fraglists
1644 * are bounded and aligned properly.
1652 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1654 /* Initialize the RX descriptor ring. */
1655 for (i = 0; i < RX_RING_SIZE; i++) {
1656 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1657 struct epic_rx_desc *desc = sc->rx_desc + i;
1659 desc->status = 0; /* Owned by driver */
1660 desc->next = sc->rx_addr +
1661 ((i + 1) & RX_RING_MASK) * sizeof(struct epic_rx_desc);
1663 if ((desc->next & 3) ||
1664 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1665 epic_free_rings(sc);
1669 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1670 if (buf->mbuf == NULL) {
1671 epic_free_rings(sc);
1674 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1675 m_adj(buf->mbuf, ETHER_ALIGN);
1677 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1679 epic_free_rings(sc);
1682 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1683 epic_dma_map_rxbuf, desc, 0);
1685 epic_free_rings(sc);
1688 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1690 desc->buflength = buf->mbuf->m_len; /* Max RX buffer length */
1691 desc->status = 0x8000; /* Set owner bit to NIC */
1693 bus_dmamap_sync(sc->rtag, sc->rmap,
1694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1696 /* Create the spare DMA map. */
1697 error = bus_dmamap_create(sc->mtag, 0, &sc->sparemap);
1699 epic_free_rings(sc);
1703 /* Initialize the TX descriptor ring. */
1704 for (i = 0; i < TX_RING_SIZE; i++) {
1705 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1706 struct epic_tx_desc *desc = sc->tx_desc + i;
1709 desc->next = sc->tx_addr +
1710 ((i + 1) & TX_RING_MASK) * sizeof(struct epic_tx_desc);
1712 if ((desc->next & 3) ||
1713 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1714 epic_free_rings(sc);
1719 desc->bufaddr = sc->frag_addr +
1720 i * sizeof(struct epic_frag_list);
1722 if ((desc->bufaddr & 3) ||
1723 ((desc->bufaddr & PAGE_MASK) +
1724 sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1725 epic_free_rings(sc);
1729 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
1731 epic_free_rings(sc);
1735 bus_dmamap_sync(sc->ttag, sc->tmap,
1736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1737 bus_dmamap_sync(sc->ftag, sc->fmap, BUS_DMASYNC_PREWRITE);
1743 * EEPROM operation functions
1746 epic_write_eepromreg(sc, val)
1752 CSR_WRITE_1(sc, EECTL, val);
1754 for (i = 0; i < 0xFF; i++) {
1755 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0)
1761 epic_read_eepromreg(sc)
1765 return (CSR_READ_1(sc, EECTL));
1769 epic_eeprom_clock(sc, val)
1774 epic_write_eepromreg(sc, val);
1775 epic_write_eepromreg(sc, (val | 0x4));
1776 epic_write_eepromreg(sc, val);
1778 return (epic_read_eepromreg(sc));
1782 epic_output_eepromw(sc, val)
1788 for (i = 0xF; i >= 0; i--) {
1790 epic_eeprom_clock(sc, 0x0B);
1792 epic_eeprom_clock(sc, 0x03);
1797 epic_input_eepromw(sc)
1800 u_int16_t retval = 0;
1803 for (i = 0xF; i >= 0; i--) {
1804 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1812 epic_read_eeprom(sc, loc)
1819 epic_write_eepromreg(sc, 3);
1821 if (epic_read_eepromreg(sc) & 0x40)
1822 read_cmd = (loc & 0x3F) | 0x180;
1824 read_cmd = (loc & 0xFF) | 0x600;
1826 epic_output_eepromw(sc, read_cmd);
1828 dataval = epic_input_eepromw(sc);
1830 epic_write_eepromreg(sc, 1);
1836 * Here goes MII read/write routines.
1839 epic_read_phy_reg(sc, phy, reg)
1845 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1847 for (i = 0; i < 0x100; i++) {
1848 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1853 return (CSR_READ_4(sc, MIIDATA));
1857 epic_write_phy_reg(sc, phy, reg, val)
1863 CSR_WRITE_4(sc, MIIDATA, val);
1864 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1866 for(i = 0; i < 0x100; i++) {
1867 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0)
1874 epic_miibus_readreg(dev, phy, reg)
1880 sc = device_get_softc(dev);
1882 return (PHY_READ_2(sc, phy, reg));
1886 epic_miibus_writereg(dev, phy, reg, data)
1892 sc = device_get_softc(dev);
1894 PHY_WRITE_2(sc, phy, reg, data);