2 * Copyright (c) 1997 Semen Ustimenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /*#define EPIC_DIAG 1*/
33 /*#define EPIC_USEIOSPACE 1*/
34 /*#define EPIC_EARLY_RX 1*/
37 #define ETHER_MAX_LEN 1518
40 #define ETHER_MIN_LEN 64
43 #define ETHER_CRC_LEN 4
45 #define TX_RING_SIZE 16 /* Leave this a power of 2 */
46 #define RX_RING_SIZE 16 /* And this too, to do not */
47 /* confuse RX(TX)_RING_MASK */
48 #define TX_RING_MASK (TX_RING_SIZE - 1)
49 #define RX_RING_MASK (RX_RING_SIZE - 1)
50 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
53 /* This is driver's structure to define EPIC descriptors */
54 struct epic_rx_buffer {
55 struct mbuf *mbuf; /* mbuf receiving packet */
56 bus_dmamap_t map; /* DMA map */
59 struct epic_tx_buffer {
60 struct mbuf *mbuf; /* mbuf contained packet */
61 bus_dmamap_t map; /* DMA map */
64 /* PHY, known by tx driver */
65 #define EPIC_UNKN_PHY 0x0000
66 #define EPIC_QS6612_PHY 0x0001
67 #define EPIC_AC101_PHY 0x0002
68 #define EPIC_LXT970_PHY 0x0003
69 #define EPIC_SERIAL 0x0004
71 /* Driver status structure */
91 bus_dmamap_t sparemap;
93 struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
94 struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
96 /* Each element of array MUST be aligned on dword */
97 /* and bounded on PAGE_SIZE */
98 struct epic_rx_desc *rx_desc;
99 struct epic_tx_desc *tx_desc;
100 struct epic_frag_list *tx_flist;
105 u_int32_t tx_threshold;
111 u_int32_t pending_txs;
114 struct mii_softc *physc;
120 #define EPIC_LOCK(sc) mtx_lock(&(sc)->lock)
121 #define EPIC_UNLOCK(sc) mtx_unlock(&(sc)->lock)
122 #define EPIC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
130 #define CSR_WRITE_4(sc, reg, val) \
131 bus_write_4((sc)->res, (reg), (val))
132 #define CSR_WRITE_2(sc, reg, val) \
133 bus_write_2((sc)->res, (reg), (val))
134 #define CSR_WRITE_1(sc, reg, val) \
135 bus_write_1((sc)->res, (reg), (val))
136 #define CSR_READ_4(sc, reg) \
137 bus_read_4((sc)->res, (reg))
138 #define CSR_READ_2(sc, reg) \
139 bus_read_2((sc)->res, (reg))
140 #define CSR_READ_1(sc, reg) \
141 bus_read_1((sc)->res, (reg))
143 #define PHY_READ_2(sc, phy, reg) \
144 epic_read_phy_reg((sc), (phy), (reg))
145 #define PHY_WRITE_2(sc, phy, reg, val) \
146 epic_write_phy_reg((sc), (phy), (reg), (val))