2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997 Semen Ustimenko
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 /*#define EPIC_DIAG 1*/
35 /*#define EPIC_USEIOSPACE 1*/
36 /*#define EPIC_EARLY_RX 1*/
39 #define ETHER_MAX_LEN 1518
42 #define ETHER_MIN_LEN 64
45 #define ETHER_CRC_LEN 4
47 #define TX_RING_SIZE 16 /* Leave this a power of 2 */
48 #define RX_RING_SIZE 16 /* And this too, to do not */
49 /* confuse RX(TX)_RING_MASK */
50 #define TX_RING_MASK (TX_RING_SIZE - 1)
51 #define RX_RING_MASK (RX_RING_SIZE - 1)
52 #define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
55 /* This is driver's structure to define EPIC descriptors */
56 struct epic_rx_buffer {
57 struct mbuf *mbuf; /* mbuf receiving packet */
58 bus_dmamap_t map; /* DMA map */
61 struct epic_tx_buffer {
62 struct mbuf *mbuf; /* mbuf contained packet */
63 bus_dmamap_t map; /* DMA map */
66 /* PHY, known by tx driver */
67 #define EPIC_UNKN_PHY 0x0000
68 #define EPIC_QS6612_PHY 0x0001
69 #define EPIC_AC101_PHY 0x0002
70 #define EPIC_LXT970_PHY 0x0003
71 #define EPIC_SERIAL 0x0004
73 /* Driver status structure */
93 bus_dmamap_t sparemap;
95 struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
96 struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
98 /* Each element of array MUST be aligned on dword */
99 /* and bounded on PAGE_SIZE */
100 struct epic_rx_desc *rx_desc;
101 struct epic_tx_desc *tx_desc;
102 struct epic_frag_list *tx_flist;
107 u_int32_t tx_threshold;
113 u_int32_t pending_txs;
116 struct mii_softc *physc;
122 #define EPIC_LOCK(sc) mtx_lock(&(sc)->lock)
123 #define EPIC_UNLOCK(sc) mtx_unlock(&(sc)->lock)
124 #define EPIC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
132 #define CSR_WRITE_4(sc, reg, val) \
133 bus_write_4((sc)->res, (reg), (val))
134 #define CSR_WRITE_2(sc, reg, val) \
135 bus_write_2((sc)->res, (reg), (val))
136 #define CSR_WRITE_1(sc, reg, val) \
137 bus_write_1((sc)->res, (reg), (val))
138 #define CSR_READ_4(sc, reg) \
139 bus_read_4((sc)->res, (reg))
140 #define CSR_READ_2(sc, reg) \
141 bus_read_2((sc)->res, (reg))
142 #define CSR_READ_1(sc, reg) \
143 bus_read_1((sc)->res, (reg))
145 #define PHY_READ_2(sc, phy, reg) \
146 epic_read_phy_reg((sc), (phy), (reg))
147 #define PHY_WRITE_2(sc, phy, reg, val) \
148 epic_write_phy_reg((sc), (phy), (reg), (val))