1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
6 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Jason L. Wright,
19 * Theo de Raadt and Aaron Campbell.
20 * 4. Neither the name of the author nor the names of any co-contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * Driver for 3c990 (Typhoon) Ethernet ASIC
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/sockio.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/socket.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_types.h>
61 #include <net/if_vlan_var.h>
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #include <netinet/if_ether.h>
68 #include <machine/in_cksum.h>
70 #include <net/if_media.h>
74 #include <vm/vm.h> /* for vtophys */
75 #include <vm/pmap.h> /* for vtophys */
76 #include <machine/clock.h> /* for DELAY */
77 #include <machine/bus.h>
78 #include <machine/resource.h>
82 #include <dev/mii/mii.h>
83 #include <dev/mii/miivar.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
87 #define TXP_USEIOSPACE
88 #define __STRICT_ALIGNMENT
90 #include <dev/txp/if_txpreg.h>
91 #include <dev/txp/3c990img.h>
94 static const char rcsid[] =
99 * Various supported device vendors/types and their names.
101 static struct txp_type txp_devs[] = {
102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95,
103 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97,
105 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM,
107 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95,
109 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
110 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97,
111 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
112 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV,
113 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
117 static int txp_probe(device_t);
118 static int txp_attach(device_t);
119 static int txp_detach(device_t);
120 static void txp_intr(void *);
121 static void txp_tick(void *);
122 static int txp_shutdown(device_t);
123 static int txp_ioctl(struct ifnet *, u_long, caddr_t);
124 static void txp_start(struct ifnet *);
125 static void txp_start_locked(struct ifnet *);
126 static void txp_stop(struct txp_softc *);
127 static void txp_init(void *);
128 static void txp_init_locked(struct txp_softc *);
129 static void txp_watchdog(struct ifnet *);
131 static void txp_release_resources(struct txp_softc *);
132 static int txp_chip_init(struct txp_softc *);
133 static int txp_reset_adapter(struct txp_softc *);
134 static int txp_download_fw(struct txp_softc *);
135 static int txp_download_fw_wait(struct txp_softc *);
136 static int txp_download_fw_section(struct txp_softc *,
137 struct txp_fw_section_header *, int);
138 static int txp_alloc_rings(struct txp_softc *);
139 static int txp_rxring_fill(struct txp_softc *);
140 static void txp_rxring_empty(struct txp_softc *);
141 static void txp_set_filter(struct txp_softc *);
143 static int txp_cmd_desc_numfree(struct txp_softc *);
144 static int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
145 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
146 static int txp_command2(struct txp_softc *, u_int16_t, u_int16_t,
147 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
148 struct txp_rsp_desc **, int);
149 static int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
150 struct txp_rsp_desc **);
151 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *,
152 struct txp_rsp_desc *);
153 static void txp_capabilities(struct txp_softc *);
155 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *);
156 static int txp_ifmedia_upd(struct ifnet *);
158 static void txp_show_descriptor(void *);
160 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *);
161 static void txp_rxbuf_reclaim(struct txp_softc *);
162 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *);
164 #ifdef TXP_USEIOSPACE
165 #define TXP_RES SYS_RES_IOPORT
166 #define TXP_RID TXP_PCI_LOIO
168 #define TXP_RES SYS_RES_MEMORY
169 #define TXP_RID TXP_PCI_LOMEM
172 static device_method_t txp_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, txp_probe),
175 DEVMETHOD(device_attach, txp_attach),
176 DEVMETHOD(device_detach, txp_detach),
177 DEVMETHOD(device_shutdown, txp_shutdown),
181 static driver_t txp_driver = {
184 sizeof(struct txp_softc)
187 static devclass_t txp_devclass;
189 DRIVER_MODULE(txp, pci, txp_driver, txp_devclass, 0, 0);
190 MODULE_DEPEND(txp, pci, 1, 1, 1);
191 MODULE_DEPEND(txp, ether, 1, 1, 1);
201 while(t->txp_name != NULL) {
202 if ((pci_get_vendor(dev) == t->txp_vid) &&
203 (pci_get_device(dev) == t->txp_did)) {
204 device_set_desc(dev, t->txp_name);
205 return(BUS_PROBE_DEFAULT);
217 struct txp_softc *sc;
224 sc = device_get_softc(dev);
228 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
230 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0);
233 * Map control/status registers.
235 pci_enable_busmaster(dev);
238 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid,
241 if (sc->sc_res == NULL) {
242 device_printf(dev, "couldn't map ports/memory\n");
247 sc->sc_bt = rman_get_bustag(sc->sc_res);
248 sc->sc_bh = rman_get_bushandle(sc->sc_res);
250 /* Allocate interrupt */
252 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
253 RF_SHAREABLE | RF_ACTIVE);
255 if (sc->sc_irq == NULL) {
256 device_printf(dev, "couldn't map interrupt\n");
261 if (txp_chip_init(sc)) {
266 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
267 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
268 error = txp_download_fw(sc);
269 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
275 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
276 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
277 bzero(sc->sc_ldata, sizeof(struct txp_ldata));
279 if (txp_alloc_rings(sc)) {
284 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
285 NULL, NULL, NULL, 1)) {
290 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
291 &p1, &p2, NULL, 1)) {
296 eaddr[0] = ((u_int8_t *)&p1)[1];
297 eaddr[1] = ((u_int8_t *)&p1)[0];
298 eaddr[2] = ((u_int8_t *)&p2)[3];
299 eaddr[3] = ((u_int8_t *)&p2)[2];
300 eaddr[4] = ((u_int8_t *)&p2)[1];
301 eaddr[5] = ((u_int8_t *)&p2)[0];
305 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
314 sc->sc_xcvr = TXP_XCVR_AUTO;
315 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
316 NULL, NULL, NULL, 0);
317 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
319 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
321 device_printf(dev, "can not if_alloc()\n");
326 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
327 ifp->if_mtu = ETHERMTU;
328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
329 ifp->if_ioctl = txp_ioctl;
330 ifp->if_start = txp_start;
331 ifp->if_watchdog = txp_watchdog;
332 ifp->if_init = txp_init;
333 ifp->if_baudrate = 100000000;
334 ifp->if_snd.ifq_maxlen = TX_ENTRIES;
335 ifp->if_hwassist = 0;
336 txp_capabilities(sc);
339 * Attach us everywhere
341 ether_ifattach(ifp, eaddr);
343 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
344 txp_intr, sc, &sc->sc_intrhand);
348 device_printf(dev, "couldn't set up irq\n");
355 txp_release_resources(sc);
356 mtx_destroy(&sc->sc_mtx);
364 struct txp_softc *sc;
368 sc = device_get_softc(dev);
375 callout_drain(&sc->sc_tick);
377 ifmedia_removeall(&sc->sc_ifmedia);
380 for (i = 0; i < RXBUF_ENTRIES; i++)
381 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
383 txp_release_resources(sc);
385 mtx_destroy(&sc->sc_mtx);
390 txp_release_resources(sc)
391 struct txp_softc *sc;
397 if (sc->sc_intrhand != NULL)
398 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
400 if (sc->sc_irq != NULL)
401 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
403 if (sc->sc_res != NULL)
404 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
406 if (sc->sc_ldata != NULL)
407 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
417 struct txp_softc *sc;
419 /* disable interrupts */
420 WRITE_REG(sc, TXP_IER, 0);
421 WRITE_REG(sc, TXP_IMR,
422 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
423 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
426 /* ack all interrupts */
427 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
428 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
429 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
430 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
431 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
433 if (txp_reset_adapter(sc))
436 /* disable interrupts */
437 WRITE_REG(sc, TXP_IER, 0);
438 WRITE_REG(sc, TXP_IMR,
439 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
440 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
443 /* ack all interrupts */
444 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
445 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
446 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
447 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
448 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
454 txp_reset_adapter(sc)
455 struct txp_softc *sc;
461 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
463 WRITE_REG(sc, TXP_SRR, 0);
465 /* Should wait max 6 seconds */
466 for (i = 0; i < 6000; i++) {
467 r = READ_REG(sc, TXP_A2H_0);
468 if (r == STAT_WAITING_FOR_HOST_REQUEST)
473 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
474 device_printf(sc->sc_dev, "reset hung\n");
483 struct txp_softc *sc;
485 struct txp_fw_file_header *fileheader;
486 struct txp_fw_section_header *secthead;
488 u_int32_t r, i, ier, imr;
491 ier = READ_REG(sc, TXP_IER);
492 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
494 imr = READ_REG(sc, TXP_IMR);
495 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
497 for (i = 0; i < 10000; i++) {
498 r = READ_REG(sc, TXP_A2H_0);
499 if (r == STAT_WAITING_FOR_HOST_REQUEST)
503 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
504 device_printf(sc->sc_dev, "not waiting for host request\n");
509 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
511 fileheader = (struct txp_fw_file_header *)tc990image;
512 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
513 device_printf(sc->sc_dev, "fw invalid magic\n");
517 /* Tell boot firmware to get ready for image */
518 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
519 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
521 if (txp_download_fw_wait(sc)) {
522 device_printf(sc->sc_dev, "fw wait failed, initial\n");
526 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
527 sizeof(struct txp_fw_file_header));
529 for (sect = 0; sect < fileheader->nsections; sect++) {
530 if (txp_download_fw_section(sc, secthead, sect))
532 secthead = (struct txp_fw_section_header *)
533 (((u_int8_t *)secthead) + secthead->nbytes +
537 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
539 for (i = 0; i < 10000; i++) {
540 r = READ_REG(sc, TXP_A2H_0);
541 if (r == STAT_WAITING_FOR_BOOT)
545 if (r != STAT_WAITING_FOR_BOOT) {
546 device_printf(sc->sc_dev, "not waiting for boot\n");
550 WRITE_REG(sc, TXP_IER, ier);
551 WRITE_REG(sc, TXP_IMR, imr);
557 txp_download_fw_wait(sc)
558 struct txp_softc *sc;
563 for (i = 0; i < 10000; i++) {
564 r = READ_REG(sc, TXP_ISR);
565 if (r & TXP_INT_A2H_0)
570 if (!(r & TXP_INT_A2H_0)) {
571 device_printf(sc->sc_dev, "fw wait failed comm0\n");
575 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
577 r = READ_REG(sc, TXP_A2H_0);
578 if (r != STAT_WAITING_FOR_SEGMENT) {
579 device_printf(sc->sc_dev, "fw not waiting for segment\n");
586 txp_download_fw_section(sc, sect, sectnum)
587 struct txp_softc *sc;
588 struct txp_fw_section_header *sect;
596 /* Skip zero length sections */
597 if (sect->nbytes == 0)
600 /* Make sure we aren't past the end of the image */
601 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
602 if (rseg >= sizeof(tc990image)) {
603 device_printf(sc->sc_dev, "fw invalid section address, "
604 "section %d\n", sectnum);
608 /* Make sure this section doesn't go past the end */
609 rseg += sect->nbytes;
610 if (rseg >= sizeof(tc990image)) {
611 device_printf(sc->sc_dev, "fw truncated section %d\n",
616 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
617 dma = vtophys(sc->sc_fwbuf);
620 * dummy up mbuf and verify section checksum
623 m.m_next = m.m_nextpkt = NULL;
624 m.m_len = sect->nbytes;
625 m.m_data = sc->sc_fwbuf;
627 csum = in_cksum(&m, sect->nbytes);
628 if (csum != sect->cksum) {
629 device_printf(sc->sc_dev, "fw section %d, bad "
630 "cksum (expected 0x%x got 0x%x)\n",
631 sectnum, sect->cksum, csum);
636 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
637 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
638 WRITE_REG(sc, TXP_H2A_3, sect->addr);
639 WRITE_REG(sc, TXP_H2A_4, 0);
640 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
641 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
643 if (txp_download_fw_wait(sc)) {
644 device_printf(sc->sc_dev, "fw wait failed, "
645 "section %d\n", sectnum);
657 struct txp_softc *sc = vsc;
658 struct txp_hostvar *hv = sc->sc_hostvar;
661 /* mask all interrupts */
663 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
664 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
665 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
666 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
667 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
669 isr = READ_REG(sc, TXP_ISR);
671 WRITE_REG(sc, TXP_ISR, isr);
673 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
674 txp_rx_reclaim(sc, &sc->sc_rxhir);
675 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
676 txp_rx_reclaim(sc, &sc->sc_rxlor);
678 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
679 txp_rxbuf_reclaim(sc);
681 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
682 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
683 txp_tx_reclaim(sc, &sc->sc_txhir);
685 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
686 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
687 txp_tx_reclaim(sc, &sc->sc_txlor);
689 isr = READ_REG(sc, TXP_ISR);
692 /* unmask all interrupts */
693 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
695 txp_start_locked(sc->sc_ifp);
702 txp_rx_reclaim(sc, r)
703 struct txp_softc *sc;
704 struct txp_rx_ring *r;
706 struct ifnet *ifp = sc->sc_ifp;
707 struct txp_rx_desc *rxd;
709 struct txp_swdesc *sd = NULL;
710 u_int32_t roff, woff;
715 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
717 while (roff != woff) {
719 if (rxd->rx_flags & RX_FLAGS_ERROR) {
720 device_printf(sc->sc_dev, "error 0x%x\n",
726 /* retrieve stashed pointer */
732 m->m_pkthdr.len = m->m_len = rxd->rx_len;
734 #ifdef __STRICT_ALIGNMENT
737 * XXX Nice chip, except it won't accept "off by 2"
738 * buffers, so we're force to copy. Supposedly
739 * this will be fixed in a newer firmware rev
740 * and this will be temporary.
744 mnew = m_devget(mtod(m, caddr_t), rxd->rx_len,
745 ETHER_ALIGN, ifp, NULL);
755 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
756 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
757 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
758 m->m_pkthdr.csum_flags |=
759 CSUM_IP_CHECKED|CSUM_IP_VALID;
761 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
762 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
763 m->m_pkthdr.csum_flags |=
764 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
765 m->m_pkthdr.csum_data = 0xffff;
768 if (rxd->rx_stat & RX_STAT_VLAN) {
769 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16));
775 (*ifp->if_input)(ifp, m);
780 roff += sizeof(struct txp_rx_desc);
781 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
795 txp_rxbuf_reclaim(sc)
796 struct txp_softc *sc;
798 struct ifnet *ifp = sc->sc_ifp;
799 struct txp_hostvar *hv = sc->sc_hostvar;
800 struct txp_rxbuf_desc *rbd;
801 struct txp_swdesc *sd;
805 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
808 i = sc->sc_rxbufprod;
809 rbd = sc->sc_rxbufs + i;
813 if (sd->sd_mbuf != NULL)
816 sd->sd_mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
817 if (sd->sd_mbuf == NULL)
819 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
820 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
822 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
826 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
828 if (++i == RXBUF_ENTRIES) {
835 sc->sc_rxbufprod = i;
841 * Reclaim mbufs and entries from a transmit ring.
844 txp_tx_reclaim(sc, r)
845 struct txp_softc *sc;
846 struct txp_tx_ring *r;
848 struct ifnet *ifp = sc->sc_ifp;
849 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
850 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
851 struct txp_tx_desc *txd = r->r_desc + cons;
852 struct txp_swdesc *sd = sc->sc_txd + cons;
856 while (cons != idx) {
860 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
861 TX_FLAGS_TYPE_DATA) {
870 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
872 if (++cons == TX_ENTRIES) {
894 struct txp_softc *sc;
896 sc = device_get_softc(dev);
900 /* mask all interrupts */
901 WRITE_REG(sc, TXP_IMR,
902 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
903 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
906 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
907 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
908 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
916 struct txp_softc *sc;
918 struct txp_boot_record *boot;
919 struct txp_ldata *ld;
925 boot = &ld->txp_boot;
931 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
932 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
933 boot->br_hostvar_hi = 0;
934 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
936 /* hi priority tx ring */
937 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);;
938 boot->br_txhipri_hi = 0;
939 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
940 sc->sc_txhir.r_reg = TXP_H2A_1;
941 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
942 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
943 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
945 /* lo priority tx ring */
946 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
947 boot->br_txlopri_hi = 0;
948 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
949 sc->sc_txlor.r_reg = TXP_H2A_3;
950 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
951 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
952 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
954 /* high priority rx ring */
955 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
956 boot->br_rxhipri_hi = 0;
957 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
958 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
959 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
960 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
962 /* low priority rx ring */
963 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
964 boot->br_rxlopri_hi = 0;
965 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
966 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
967 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
968 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
971 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
972 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
974 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
975 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
976 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
977 sc->sc_cmdring.lastwrite = 0;
980 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
981 boot->br_resp_lo = vtophys(&ld->txp_rspring);
982 boot->br_resp_hi = 0;
983 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
984 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
985 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
986 sc->sc_rspring.lastwrite = 0;
988 /* receive buffer ring */
989 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
990 boot->br_rxbuf_hi = 0;
991 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
992 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
994 for (i = 0; i < RXBUF_ENTRIES; i++) {
995 struct txp_swdesc *sd;
996 if (sc->sc_rxbufs[i].rb_sd != NULL)
998 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc),
1000 if (sc->sc_rxbufs[i].rb_sd == NULL)
1002 sd = sc->sc_rxbufs[i].rb_sd;
1005 sc->sc_rxbufprod = 0;
1008 bzero(&ld->txp_zero, sizeof(u_int32_t));
1009 boot->br_zero_lo = vtophys(&ld->txp_zero);
1010 boot->br_zero_hi = 0;
1012 /* See if it's waiting for boot, and try to boot it */
1013 for (i = 0; i < 10000; i++) {
1014 r = READ_REG(sc, TXP_A2H_0);
1015 if (r == STAT_WAITING_FOR_BOOT)
1020 if (r != STAT_WAITING_FOR_BOOT) {
1021 device_printf(sc->sc_dev, "not waiting for boot\n");
1025 WRITE_REG(sc, TXP_H2A_2, 0);
1026 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
1027 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
1029 /* See if it booted */
1030 for (i = 0; i < 10000; i++) {
1031 r = READ_REG(sc, TXP_A2H_0);
1032 if (r == STAT_RUNNING)
1036 if (r != STAT_RUNNING) {
1037 device_printf(sc->sc_dev, "fw not running\n");
1041 /* Clear TX and CMD ring write registers */
1042 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
1043 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
1044 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
1045 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1051 txp_ioctl(ifp, command, data)
1056 struct txp_softc *sc = ifp->if_softc;
1057 struct ifreq *ifr = (struct ifreq *)data;
1063 if (ifp->if_flags & IFF_UP) {
1064 txp_init_locked(sc);
1066 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1074 * Multicast list has changed; set the hardware
1075 * filter accordingly.
1084 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1087 error = ether_ioctl(ifp, command, data);
1096 struct txp_softc *sc;
1100 struct txp_swdesc *sd;
1102 TXP_LOCK_ASSERT(sc);
1105 for (i = 0; i < RXBUF_ENTRIES; i++) {
1106 sd = sc->sc_rxbufs[i].rb_sd;
1107 sd->sd_mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1108 if (sd->sd_mbuf == NULL)
1111 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1112 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1114 sc->sc_rxbufs[i].rb_paddrlo =
1115 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1116 sc->sc_rxbufs[i].rb_paddrhi = 0;
1119 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1120 sizeof(struct txp_rxbuf_desc);
1126 txp_rxring_empty(sc)
1127 struct txp_softc *sc;
1130 struct txp_swdesc *sd;
1132 TXP_LOCK_ASSERT(sc);
1133 if (sc->sc_rxbufs == NULL)
1136 for (i = 0; i < RXBUF_ENTRIES; i++) {
1137 if (&sc->sc_rxbufs[i] == NULL)
1139 sd = sc->sc_rxbufs[i].rb_sd;
1142 if (sd->sd_mbuf != NULL) {
1143 m_freem(sd->sd_mbuf);
1155 struct txp_softc *sc;
1159 txp_init_locked(sc);
1165 struct txp_softc *sc;
1171 TXP_LOCK_ASSERT(sc);
1174 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1179 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1180 NULL, NULL, NULL, 1);
1182 /* Set station address. */
1183 ((u_int8_t *)&p1)[1] = IF_LLADDR(sc->sc_ifp)[0];
1184 ((u_int8_t *)&p1)[0] = IF_LLADDR(sc->sc_ifp)[1];
1185 ((u_int8_t *)&p2)[3] = IF_LLADDR(sc->sc_ifp)[2];
1186 ((u_int8_t *)&p2)[2] = IF_LLADDR(sc->sc_ifp)[3];
1187 ((u_int8_t *)&p2)[1] = IF_LLADDR(sc->sc_ifp)[4];
1188 ((u_int8_t *)&p2)[0] = IF_LLADDR(sc->sc_ifp)[5];
1189 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1190 NULL, NULL, NULL, 1);
1194 txp_rxring_fill(sc);
1196 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1197 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1199 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1200 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1201 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1202 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1203 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1204 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1206 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1207 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1210 callout_reset(&sc->sc_tick, hz, txp_tick, sc);
1217 struct txp_softc *sc = vsc;
1218 struct ifnet *ifp = sc->sc_ifp;
1219 struct txp_rsp_desc *rsp = NULL;
1220 struct txp_ext_desc *ext;
1222 TXP_LOCK_ASSERT(sc);
1223 txp_rxbuf_reclaim(sc);
1225 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1228 if (rsp->rsp_numdesc != 6)
1230 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1231 NULL, NULL, NULL, 1))
1233 ext = (struct txp_ext_desc *)(rsp + 1);
1235 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1236 ext[4].ext_1 + ext[4].ext_4;
1237 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1239 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1241 ifp->if_opackets += rsp->rsp_par2;
1242 ifp->if_ipackets += ext[2].ext_3;
1246 free(rsp, M_DEVBUF);
1248 callout_reset(&sc->sc_tick, hz, txp_tick, sc);
1257 struct txp_softc *sc;
1261 txp_start_locked(ifp);
1266 txp_start_locked(ifp)
1269 struct txp_softc *sc = ifp->if_softc;
1270 struct txp_tx_ring *r = &sc->sc_txhir;
1271 struct txp_tx_desc *txd;
1272 struct txp_frag_desc *fxd;
1273 struct mbuf *m, *m0;
1274 struct txp_swdesc *sd;
1275 u_int32_t firstprod, firstcnt, prod, cnt;
1278 TXP_LOCK_ASSERT(sc);
1279 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1287 IF_DEQUEUE(&ifp->if_snd, m);
1294 sd = sc->sc_txd + prod;
1297 if ((TX_ENTRIES - cnt) < 4)
1300 txd = r->r_desc + prod;
1302 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1303 txd->tx_numdesc = 0;
1309 if (++prod == TX_ENTRIES)
1312 if (++cnt >= (TX_ENTRIES - 4))
1315 mtag = VLAN_OUTPUT_TAG(ifp, m);
1317 txd->tx_pflags = TX_PFLAGS_VLAN |
1318 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S);
1321 if (m->m_pkthdr.csum_flags & CSUM_IP)
1322 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1325 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1326 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1327 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1328 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1331 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1332 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1335 if (++cnt >= (TX_ENTRIES - 4))
1340 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1341 fxd->frag_rsvd1 = 0;
1342 fxd->frag_len = m0->m_len;
1343 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1344 fxd->frag_addrhi = 0;
1345 fxd->frag_rsvd2 = 0;
1347 if (++prod == TX_ENTRIES) {
1348 fxd = (struct txp_frag_desc *)r->r_desc;
1358 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1366 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1367 r->r_prod = firstprod;
1368 r->r_cnt = firstcnt;
1369 IF_PREPEND(&ifp->if_snd, m);
1374 * Handle simple commands sent to the typhoon
1377 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait)
1378 struct txp_softc *sc;
1379 u_int16_t id, in1, *out1;
1380 u_int32_t in2, in3, *out2, *out3;
1383 struct txp_rsp_desc *rsp = NULL;
1385 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1392 *out1 = rsp->rsp_par1;
1394 *out2 = rsp->rsp_par2;
1396 *out3 = rsp->rsp_par3;
1397 free(rsp, M_DEVBUF);
1402 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait)
1403 struct txp_softc *sc;
1406 struct txp_ext_desc *in_extp;
1408 struct txp_rsp_desc **rspp;
1411 struct txp_hostvar *hv = sc->sc_hostvar;
1412 struct txp_cmd_desc *cmd;
1413 struct txp_ext_desc *ext;
1417 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1418 device_printf(sc->sc_dev, "no free cmd descriptors\n");
1422 idx = sc->sc_cmdring.lastwrite;
1423 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1424 bzero(cmd, sizeof(*cmd));
1426 cmd->cmd_numdesc = in_extn;
1427 cmd->cmd_seq = seq = sc->sc_seq++;
1429 cmd->cmd_par1 = in1;
1430 cmd->cmd_par2 = in2;
1431 cmd->cmd_par3 = in3;
1432 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1433 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1435 idx += sizeof(struct txp_cmd_desc);
1436 if (idx == sc->sc_cmdring.size)
1439 for (i = 0; i < in_extn; i++) {
1440 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1441 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1443 idx += sizeof(struct txp_cmd_desc);
1444 if (idx == sc->sc_cmdring.size)
1448 sc->sc_cmdring.lastwrite = idx;
1450 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1455 for (i = 0; i < 10000; i++) {
1456 idx = hv->hv_resp_read_idx;
1457 if (idx != hv->hv_resp_write_idx) {
1459 if (txp_response(sc, idx, id, seq, rspp))
1466 if (i == 1000 || (*rspp) == NULL) {
1467 device_printf(sc->sc_dev, "0x%x command failed\n", id);
1475 txp_response(sc, ridx, id, seq, rspp)
1476 struct txp_softc *sc;
1480 struct txp_rsp_desc **rspp;
1482 struct txp_hostvar *hv = sc->sc_hostvar;
1483 struct txp_rsp_desc *rsp;
1485 while (ridx != hv->hv_resp_write_idx) {
1486 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1488 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1489 *rspp = (struct txp_rsp_desc *)malloc(
1490 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1491 M_DEVBUF, M_NOWAIT);
1492 if ((*rspp) == NULL)
1494 txp_rsp_fixup(sc, rsp, *rspp);
1498 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1499 device_printf(sc->sc_dev, "response error!\n");
1500 txp_rsp_fixup(sc, rsp, NULL);
1501 ridx = hv->hv_resp_read_idx;
1505 switch (rsp->rsp_id) {
1506 case TXP_CMD_CYCLE_STATISTICS:
1507 case TXP_CMD_MEDIA_STATUS_READ:
1509 case TXP_CMD_HELLO_RESPONSE:
1510 device_printf(sc->sc_dev, "hello\n");
1513 device_printf(sc->sc_dev, "unknown id(0x%x)\n",
1517 txp_rsp_fixup(sc, rsp, NULL);
1518 ridx = hv->hv_resp_read_idx;
1519 hv->hv_resp_read_idx = ridx;
1526 txp_rsp_fixup(sc, rsp, dst)
1527 struct txp_softc *sc;
1528 struct txp_rsp_desc *rsp, *dst;
1530 struct txp_rsp_desc *src = rsp;
1531 struct txp_hostvar *hv = sc->sc_hostvar;
1534 ridx = hv->hv_resp_read_idx;
1536 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1538 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1539 ridx += sizeof(struct txp_rsp_desc);
1540 if (ridx == sc->sc_rspring.size) {
1541 src = sc->sc_rspring.base;
1545 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1548 hv->hv_resp_read_idx = ridx;
1552 txp_cmd_desc_numfree(sc)
1553 struct txp_softc *sc;
1555 struct txp_hostvar *hv = sc->sc_hostvar;
1556 struct txp_boot_record *br = sc->sc_boot;
1557 u_int32_t widx, ridx, nfree;
1559 widx = sc->sc_cmdring.lastwrite;
1560 ridx = hv->hv_cmd_read_idx;
1563 /* Ring is completely free */
1564 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1567 nfree = br->br_cmd_siz -
1568 (widx - ridx + sizeof(struct txp_cmd_desc));
1570 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1573 return (nfree / sizeof(struct txp_cmd_desc));
1578 struct txp_softc *sc;
1582 TXP_LOCK_ASSERT(sc);
1585 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1587 callout_stop(&sc->sc_tick);
1589 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1590 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1592 txp_rxring_empty(sc);
1605 txp_ifmedia_upd(ifp)
1608 struct txp_softc *sc = ifp->if_softc;
1609 struct ifmedia *ifm = &sc->sc_ifmedia;
1613 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1618 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1619 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1620 new_xcvr = TXP_XCVR_10_FDX;
1622 new_xcvr = TXP_XCVR_10_HDX;
1623 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1624 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1625 new_xcvr = TXP_XCVR_100_FDX;
1627 new_xcvr = TXP_XCVR_100_HDX;
1628 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1629 new_xcvr = TXP_XCVR_AUTO;
1636 if (sc->sc_xcvr == new_xcvr) {
1641 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1642 NULL, NULL, NULL, 0);
1643 sc->sc_xcvr = new_xcvr;
1650 txp_ifmedia_sts(ifp, ifmr)
1652 struct ifmediareq *ifmr;
1654 struct txp_softc *sc = ifp->if_softc;
1655 struct ifmedia *ifm = &sc->sc_ifmedia;
1656 u_int16_t bmsr, bmcr, anlpar;
1658 ifmr->ifm_status = IFM_AVALID;
1659 ifmr->ifm_active = IFM_ETHER;
1662 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1663 &bmsr, NULL, NULL, 1))
1665 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1666 &bmsr, NULL, NULL, 1))
1669 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1670 &bmcr, NULL, NULL, 1))
1673 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1674 &anlpar, NULL, NULL, 1))
1678 if (bmsr & BMSR_LINK)
1679 ifmr->ifm_status |= IFM_ACTIVE;
1681 if (bmcr & BMCR_ISO) {
1682 ifmr->ifm_active |= IFM_NONE;
1683 ifmr->ifm_status = 0;
1687 if (bmcr & BMCR_LOOP)
1688 ifmr->ifm_active |= IFM_LOOP;
1690 if (bmcr & BMCR_AUTOEN) {
1691 if ((bmsr & BMSR_ACOMP) == 0) {
1692 ifmr->ifm_active |= IFM_NONE;
1696 if (anlpar & ANLPAR_T4)
1697 ifmr->ifm_active |= IFM_100_T4;
1698 else if (anlpar & ANLPAR_TX_FD)
1699 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1700 else if (anlpar & ANLPAR_TX)
1701 ifmr->ifm_active |= IFM_100_TX;
1702 else if (anlpar & ANLPAR_10_FD)
1703 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1704 else if (anlpar & ANLPAR_10)
1705 ifmr->ifm_active |= IFM_10_T;
1707 ifmr->ifm_active |= IFM_NONE;
1709 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1714 ifmr->ifm_active |= IFM_NONE;
1715 ifmr->ifm_status &= ~IFM_AVALID;
1720 txp_show_descriptor(d)
1723 struct txp_cmd_desc *cmd = d;
1724 struct txp_rsp_desc *rsp = d;
1725 struct txp_tx_desc *txd = d;
1726 struct txp_frag_desc *frgd = d;
1728 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1729 case CMD_FLAGS_TYPE_CMD:
1730 /* command descriptor */
1731 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1732 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1733 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1735 case CMD_FLAGS_TYPE_RESP:
1736 /* response descriptor */
1737 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1738 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1739 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1741 case CMD_FLAGS_TYPE_DATA:
1742 /* data header (assuming tx for now) */
1743 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1744 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1745 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1747 case CMD_FLAGS_TYPE_FRAG:
1748 /* fragment descriptor */
1749 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1750 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1751 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1754 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1755 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1756 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1757 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1765 struct txp_softc *sc;
1767 struct ifnet *ifp = sc->sc_ifp;
1768 u_int32_t crc, carry, hashbit, hash[2];
1772 struct ifmultiaddr *ifma;
1775 if (ifp->if_flags & IFF_PROMISC) {
1776 filter = TXP_RXFILT_PROMISC;
1780 filter = TXP_RXFILT_DIRECT;
1782 if (ifp->if_flags & IFF_BROADCAST)
1783 filter |= TXP_RXFILT_BROADCAST;
1785 if (ifp->if_flags & IFF_ALLMULTI)
1786 filter |= TXP_RXFILT_ALLMULTI;
1788 hash[0] = hash[1] = 0;
1791 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1792 if (ifma->ifma_addr->sa_family != AF_LINK)
1795 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1799 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1801 for (j = 0; j < 8; j++) {
1802 carry = ((crc & 0x80000000) ? 1 : 0) ^
1807 crc = (crc ^ TXP_POLYNOMIAL) |
1811 hashbit = (u_int16_t)(crc & (64 - 1));
1812 hash[hashbit / 32] |= (1 << hashbit % 32);
1814 IF_ADDR_UNLOCK(ifp);
1817 filter |= TXP_RXFILT_HASHMULTI;
1818 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1819 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1825 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1826 NULL, NULL, NULL, 1);
1832 txp_capabilities(sc)
1833 struct txp_softc *sc;
1835 struct ifnet *ifp = sc->sc_ifp;
1836 struct txp_rsp_desc *rsp = NULL;
1837 struct txp_ext_desc *ext;
1839 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1842 if (rsp->rsp_numdesc != 1)
1844 ext = (struct txp_ext_desc *)(rsp + 1);
1846 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1847 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1848 ifp->if_capabilities = 0;
1850 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1851 sc->sc_tx_capability |= OFFLOAD_VLAN;
1852 sc->sc_rx_capability |= OFFLOAD_VLAN;
1853 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
1858 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1859 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1860 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1861 ifp->if_capabilities |= IFCAP_IPSEC;
1865 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1866 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1867 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1868 ifp->if_capabilities |= IFCAP_HWCSUM;
1869 ifp->if_hwassist |= CSUM_IP;
1872 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1874 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1876 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1877 ifp->if_capabilities |= IFCAP_HWCSUM;
1880 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1882 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1884 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1885 ifp->if_capabilities |= IFCAP_HWCSUM;
1887 ifp->if_capenable = ifp->if_capabilities;
1889 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1890 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1895 free(rsp, M_DEVBUF);