1 /* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */
5 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Aaron Campbell.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #define TXP_PCI_LOMEM 0x14 /* pci conf, memory map BAR */
36 #define TXP_PCI_LOIO 0x10 /* pci conf, IO map BAR */
37 #define TXP_PCI_INTLINE 0x3C
42 #define TXP_SRR 0x00 /* soft reset register */
43 #define TXP_ISR 0x04 /* interrupt status register */
44 #define TXP_IER 0x08 /* interrupt enable register */
45 #define TXP_IMR 0x0c /* interrupt mask register */
46 #define TXP_SIR 0x10 /* self interrupt register */
47 #define TXP_H2A_7 0x14 /* host->arm comm 7 */
48 #define TXP_H2A_6 0x18 /* host->arm comm 6 */
49 #define TXP_H2A_5 0x1c /* host->arm comm 5 */
50 #define TXP_H2A_4 0x20 /* host->arm comm 4 */
51 #define TXP_H2A_3 0x24 /* host->arm comm 3 */
52 #define TXP_H2A_2 0x28 /* host->arm comm 2 */
53 #define TXP_H2A_1 0x2c /* host->arm comm 1 */
54 #define TXP_H2A_0 0x30 /* host->arm comm 0 */
55 #define TXP_A2H_3 0x34 /* arm->host comm 3 */
56 #define TXP_A2H_2 0x38 /* arm->host comm 2 */
57 #define TXP_A2H_1 0x3c /* arm->host comm 1 */
58 #define TXP_A2H_0 0x40 /* arm->host comm 0 */
61 * interrupt bits (IMR, ISR, IER)
63 #define TXP_INT_RESERVED 0xffff0000
64 #define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */
65 #define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */
66 #define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */
67 #define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */
68 #define TXP_INT_SELF 0x00000800 /* self interrupt */
69 #define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */
70 #define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */
71 #define TXP_INT_DMA3 0x00000100 /* dma3 done */
72 #define TXP_INT_DMA2 0x00000080 /* dma2 done */
73 #define TXP_INT_DMA1 0x00000040 /* dma1 done */
74 #define TXP_INT_DMA0 0x00000020 /* dma0 done */
75 #define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */
76 #define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */
77 #define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */
78 #define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */
79 #define TXP_INT_LATCH 0x00000001 /* interrupt latch */
82 * soft reset register (SRR)
84 #define TXP_SRR_ALL 0x0000007f /* full reset */
87 * Typhoon boot commands.
89 #define TXP_BOOTCMD_NULL 0x00
90 #define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb
91 #define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc
92 #define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd
93 #define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff
96 * Typhoon runtime commands.
98 #define TXP_CMD_GLOBAL_RESET 0x00
99 #define TXP_CMD_TX_ENABLE 0x01
100 #define TXP_CMD_TX_DISABLE 0x02
101 #define TXP_CMD_RX_ENABLE 0x03
102 #define TXP_CMD_RX_DISABLE 0x04
103 #define TXP_CMD_RX_FILTER_WRITE 0x05
104 #define TXP_CMD_RX_FILTER_READ 0x06
105 #define TXP_CMD_READ_STATISTICS 0x07
106 #define TXP_CMD_CYCLE_STATISTICS 0x08
107 #define TXP_CMD_CLEAR_STATISTICS 0x09
108 #define TXP_CMD_MEMORY_READ 0x0a
109 #define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b
110 #define TXP_CMD_VARIABLE_SECTION_READ 0x0c
111 #define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d
112 #define TXP_CMD_STATIC_SECTION_READ 0x0e
113 #define TXP_CMD_STATIC_SECTION_WRITE 0x0f
114 #define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10
115 #define TXP_CMD_NVRAM_PAGE_READ 0x11
116 #define TXP_CMD_NVRAM_PAGE_WRITE 0x12
117 #define TXP_CMD_XCVR_SELECT 0x13
118 #define TXP_CMD_TEST_MUX 0x14
119 #define TXP_CMD_PHYLOOPBACK_ENABLE 0x15
120 #define TXP_CMD_PHYLOOPBACK_DISABLE 0x16
121 #define TXP_CMD_MAC_CONTROL_READ 0x17
122 #define TXP_CMD_MAC_CONTROL_WRITE 0x18
123 #define TXP_CMD_MAX_PKT_SIZE_READ 0x19
124 #define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a
125 #define TXP_CMD_MEDIA_STATUS_READ 0x1b
126 #define TXP_CMD_MEDIA_STATUS_WRITE 0x1c
127 #define TXP_CMD_NETWORK_DIAGS_READ 0x1d
128 #define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e
129 #define TXP_CMD_PHY_MGMT_READ 0x1f
130 #define TXP_CMD_PHY_MGMT_WRITE 0x20
131 #define TXP_CMD_VARIABLE_PARAMETER_READ 0x21
132 #define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22
133 #define TXP_CMD_GOTO_SLEEP 0x23
134 #define TXP_CMD_FIREWALL_CONTROL 0x24
135 #define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25
136 #define TXP_CMD_STATION_ADDRESS_WRITE 0x26
137 #define TXP_CMD_STATION_ADDRESS_READ 0x27
138 #define TXP_CMD_STATION_MASK_WRITE 0x28
139 #define TXP_CMD_STATION_MASK_READ 0x29
140 #define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a
141 #define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b
142 #define TXP_CMD_VLAN_MASK_READ 0x2c
143 #define TXP_CMD_VLAN_MASK_WRITE 0x2d
144 #define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e
145 #define TXP_CMD_BCAST_THROTTLE_READ 0x2f
146 #define TXP_CMD_DHCP_PREVENT_WRITE 0x30
147 #define TXP_CMD_DHCP_PREVENT_READ 0x31
148 #define TXP_CMD_RECV_BUFFER_CONTROL 0x32
149 #define TXP_CMD_SOFTWARE_RESET 0x33
150 #define TXP_CMD_CREATE_SA 0x34
151 #define TXP_CMD_DELETE_SA 0x35
152 #define TXP_CMD_ENABLE_RX_IP_OPTION 0x36
153 #define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37
154 #define TXP_CMD_RANDOM_NUMBER_READ 0x38
155 #define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39
156 #define TXP_CMD_MATRIX_DETAIL_READ 0x3a
157 #define TXP_CMD_FILTER_ARRAY_READ 0x3b
158 #define TXP_CMD_FILTER_DETAIL_READ 0x3c
159 #define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d
160 #define TXP_CMD_FILTER_TCL_WRITE 0x3e
161 #define TXP_CMD_FILTER_TBL_READ 0x3f
162 #define TXP_CMD_FILTER_DEFINE 0x45
163 #define TXP_CMD_ADD_WAKEUP_PKT 0x46
164 #define TXP_CMD_ADD_SLEEP_PKT 0x47
165 #define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48
166 #define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49
167 #define TXP_CMD_GET_IP_ADDRESS 0x4a
168 #define TXP_CMD_READ_PCI_REG 0x4c
169 #define TXP_CMD_WRITE_PCI_REG 0x4d
170 #define TXP_CMD_OFFLOAD_READ 0x4e
171 #define TXP_CMD_OFFLOAD_WRITE 0x4f
172 #define TXP_CMD_HELLO_RESPONSE 0x57
173 #define TXP_CMD_ENABLE_RX_FILTER 0x58
174 #define TXP_CMD_RX_FILTER_CAPABILITY 0x59
175 #define TXP_CMD_HALT 0x5d
176 #define TXP_CMD_READ_IPSEC_INFO 0x54
177 #define TXP_CMD_GET_IPSEC_ENABLE 0x67
178 #define TXP_CMD_INVALID 0xffff
180 #define TXP_FRAGMENT 0x0000
181 #define TXP_TXFRAME 0x0001
182 #define TXP_COMMAND 0x0002
183 #define TXP_OPTION 0x0003
184 #define TXP_RECEIVE 0x0004
185 #define TXP_RESPONSE 0x0005
187 #define TXP_TYPE_IPSEC 0x0000
188 #define TXP_TYPE_TCPSEGMENT 0x0001
190 #define TXP_PFLAG_NOCRC 0x0000
191 #define TXP_PFLAG_IPCKSUM 0x0001
192 #define TXP_PFLAG_TCPCKSUM 0x0002
193 #define TXP_PFLAG_TCPSEGMENT 0x0004
194 #define TXP_PFLAG_INSERTVLAN 0x0008
195 #define TXP_PFLAG_IPSEC 0x0010
196 #define TXP_PFLAG_PRIORITY 0x0020
197 #define TXP_PFLAG_UDPCKSUM 0x0040
198 #define TXP_PFLAG_PADFRAME 0x0080
200 #define TXP_MISC_FIRSTDESC 0x0000
201 #define TXP_MISC_LASTDESC 0x0001
203 #define TXP_ERR_INTERNAL 0x0000
204 #define TXP_ERR_FIFOUNDERRUN 0x0001
205 #define TXP_ERR_BADSSD 0x0002
206 #define TXP_ERR_RUNT 0x0003
207 #define TXP_ERR_CRC 0x0004
208 #define TXP_ERR_OVERSIZE 0x0005
209 #define TXP_ERR_ALIGNMENT 0x0006
210 #define TXP_ERR_DRIBBLEBIT 0x0007
212 #define TXP_PROTO_UNKNOWN 0x0000
213 #define TXP_PROTO_IP 0x0001
214 #define TXP_PROTO_IPX 0x0002
215 #define TXP_PROTO_RESERVED 0x0003
217 #define TXP_STAT_PROTO 0x0001
218 #define TXP_STAT_VLAN 0x0002
219 #define TXP_STAT_IPFRAGMENT 0x0004
220 #define TXP_STAT_IPSEC 0x0008
221 #define TXP_STAT_IPCKSUMBAD 0x0010
222 #define TXP_STAT_TCPCKSUMBAD 0x0020
223 #define TXP_STAT_UDPCKSUMBAD 0x0040
224 #define TXP_STAT_IPCKSUMGOOD 0x0080
225 #define TXP_STAT_TCPCKSUMGOOD 0x0100
226 #define TXP_STAT_UDPCKSUMGOOD 0x0200
229 volatile u_int8_t tx_flags; /* type/descriptor flags */
230 volatile u_int8_t tx_numdesc; /* number of descriptors */
231 volatile u_int16_t tx_totlen; /* total packet length */
232 volatile u_int32_t tx_addrlo; /* virt addr low word */
233 volatile u_int32_t tx_addrhi; /* virt addr high word */
234 volatile u_int32_t tx_pflags; /* processing flags */
236 #define TX_FLAGS_TYPE_M 0x07 /* type mask */
237 #define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
238 #define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
239 #define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
240 #define TX_FLAGS_TYPE_OPT 0x03 /* type: options */
241 #define TX_FLAGS_TYPE_RX 0x04 /* type: command */
242 #define TX_FLAGS_TYPE_RESP 0x05 /* type: response */
243 #define TX_FLAGS_RESP 0x40 /* response requested */
244 #define TX_FLAGS_VALID 0x80 /* valid descriptor */
246 #define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */
247 #define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */
248 #define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */
249 #define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */
250 #define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */
251 #define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */
252 #define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */
253 #define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */
254 #define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */
255 #define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */
256 #define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */
257 #define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */
260 volatile u_int8_t rx_flags; /* type/descriptor flags */
261 volatile u_int8_t rx_numdesc; /* number of descriptors */
262 volatile u_int16_t rx_len; /* frame length */
264 volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */
265 volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */
268 struct txp_swdesc *rx_sd;
271 volatile u_int32_t rx_stat; /* status */
272 volatile u_int16_t rx_filter; /* filter status */
273 volatile u_int16_t rx_hash; /* hash status */
274 volatile u_int32_t rx_vlan; /* vlan tag/priority */
277 #define rx_sd txp_rx_u.rx_sd
279 /* txp_rx_desc.rx_flags */
280 #define RX_FLAGS_TYPE_M 0x07 /* type mask */
281 #define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
282 #define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
283 #define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
284 #define RX_FLAGS_TYPE_OPT 0x03 /* type: options */
285 #define RX_FLAGS_TYPE_RX 0x04 /* type: command */
286 #define RX_FLAGS_TYPE_RESP 0x05 /* type: response */
287 #define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */
288 #define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */
289 #define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */
290 #define RX_FLAGS_ERROR 0x40 /* error in packet */
292 /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */
293 #define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */
294 #define RX_ERROR_FIFO 0x00000001 /* fifo underrun */
295 #define RX_ERROR_BADSSD 0x00000002 /* bad ssd */
296 #define RX_ERROR_RUNT 0x00000003 /* runt packet */
297 #define RX_ERROR_CRC 0x00000004 /* bad crc */
298 #define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */
299 #define RX_ERROR_ALIGN 0x00000006 /* alignment error */
300 #define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */
302 /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */
303 #define RX_STAT_PROTO_M 0x00000003 /* protocol mask */
304 #define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */
305 #define RX_STAT_PROTO_IPX 0x00000001 /* IPX */
306 #define RX_STAT_PROTO_IP 0x00000002 /* IP */
307 #define RX_STAT_PROTO_RSV 0x00000003 /* reserved */
308 #define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */
309 #define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */
310 #define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */
311 #define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */
312 #define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */
313 #define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */
314 #define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */
315 #define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */
316 #define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */
319 struct txp_rxbuf_desc {
320 volatile u_int32_t rb_paddrlo;
321 volatile u_int32_t rb_paddrhi;
323 volatile u_int32_t rb_vaddrlo;
324 volatile u_int32_t rb_vaddrhi;
327 struct txp_swdesc *rb_sd;
332 #define rb_sd txp_rb_u.rb_sd
334 /* Extension descriptor */
335 struct txp_ext_desc {
336 volatile u_int32_t ext_1;
337 volatile u_int32_t ext_2;
338 volatile u_int32_t ext_3;
339 volatile u_int32_t ext_4;
342 struct txp_cmd_desc {
343 volatile u_int8_t cmd_flags;
344 volatile u_int8_t cmd_numdesc;
345 volatile u_int16_t cmd_id;
346 volatile u_int16_t cmd_seq;
347 volatile u_int16_t cmd_par1;
348 volatile u_int32_t cmd_par2;
349 volatile u_int32_t cmd_par3;
351 #define CMD_FLAGS_TYPE_M 0x07 /* type mask */
352 #define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
353 #define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */
354 #define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */
355 #define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */
356 #define CMD_FLAGS_TYPE_RX 0x04 /* type: command */
357 #define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */
358 #define CMD_FLAGS_RESP 0x40 /* response requested */
359 #define CMD_FLAGS_VALID 0x80 /* valid descriptor */
361 struct txp_rsp_desc {
362 volatile u_int8_t rsp_flags;
363 volatile u_int8_t rsp_numdesc;
364 volatile u_int16_t rsp_id;
365 volatile u_int16_t rsp_seq;
366 volatile u_int16_t rsp_par1;
367 volatile u_int32_t rsp_par2;
368 volatile u_int32_t rsp_par3;
370 #define RSP_FLAGS_TYPE_M 0x07 /* type mask */
371 #define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
372 #define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */
373 #define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */
374 #define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */
375 #define RSP_FLAGS_TYPE_RX 0x04 /* type: command */
376 #define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */
377 #define RSP_FLAGS_ERROR 0x40 /* response error */
379 struct txp_frag_desc {
380 volatile u_int8_t frag_flags; /* type/descriptor flags */
381 volatile u_int8_t frag_rsvd1;
382 volatile u_int16_t frag_len; /* bytes in this fragment */
383 volatile u_int32_t frag_addrlo; /* phys addr low word */
384 volatile u_int32_t frag_addrhi; /* phys addr high word */
385 volatile u_int32_t frag_rsvd2;
387 #define FRAG_FLAGS_TYPE_M 0x07 /* type mask */
388 #define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
389 #define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */
390 #define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */
391 #define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */
392 #define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */
393 #define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */
395 struct txp_opt_desc {
396 u_int8_t opt_desctype:3,
407 struct txp_ipsec_desc {
408 u_int8_t ipsec_desctpe:3,
413 u_int16_t ipsec_flags;
415 u_int16_t ipsec_esp1;
417 u_int16_t ipsec_esp2;
418 u_int32_t ipsec_rsvd1;
421 struct txp_tcpseg_desc {
422 u_int8_t tcpseg_desctype:3,
428 u_int16_t tcpseg_mss:12,
431 u_int32_t tcpseg_respaddr;
432 u_int32_t tcpseg_txbytes;
433 u_int32_t tcpseg_lss;
439 #define TXP_XCVR_10_HDX 0
440 #define TXP_XCVR_10_FDX 1
441 #define TXP_XCVR_100_HDX 2
442 #define TXP_XCVR_100_FDX 3
443 #define TXP_XCVR_AUTO 4
445 #define TXP_MEDIA_CRC 0x0004 /* crc strip disable */
446 #define TXP_MEDIA_CD 0x0010 /* collision detection */
447 #define TXP_MEDIA_CS 0x0020 /* carrier sense */
448 #define TXP_MEDIA_POL 0x0400 /* polarity reversed */
449 #define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */
452 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE}
454 #define TXP_RXFILT_DIRECT 0x0001 /* directed packets */
455 #define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */
456 #define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */
457 #define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */
458 #define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */
460 /* multicast polynomial */
461 #define TXP_POLYNOMIAL 0x04c11db7
464 * boot record (pointers to rings)
466 struct txp_boot_record {
467 volatile u_int32_t br_hostvar_lo; /* host ring pointer */
468 volatile u_int32_t br_hostvar_hi;
469 volatile u_int32_t br_txlopri_lo; /* tx low pri ring */
470 volatile u_int32_t br_txlopri_hi;
471 volatile u_int32_t br_txlopri_siz;
472 volatile u_int32_t br_txhipri_lo; /* tx high pri ring */
473 volatile u_int32_t br_txhipri_hi;
474 volatile u_int32_t br_txhipri_siz;
475 volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */
476 volatile u_int32_t br_rxlopri_hi;
477 volatile u_int32_t br_rxlopri_siz;
478 volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */
479 volatile u_int32_t br_rxbuf_hi;
480 volatile u_int32_t br_rxbuf_siz;
481 volatile u_int32_t br_cmd_lo; /* command ring */
482 volatile u_int32_t br_cmd_hi;
483 volatile u_int32_t br_cmd_siz;
484 volatile u_int32_t br_resp_lo; /* response ring */
485 volatile u_int32_t br_resp_hi;
486 volatile u_int32_t br_resp_siz;
487 volatile u_int32_t br_zero_lo; /* zero word */
488 volatile u_int32_t br_zero_hi;
489 volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */
490 volatile u_int32_t br_rxhipri_hi;
491 volatile u_int32_t br_rxhipri_siz;
495 * hostvar structure (shared with typhoon)
498 volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */
499 volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */
500 volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */
501 volatile u_int32_t hv_resp_read_idx; /* host->arm */
502 volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */
503 volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */
504 volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */
505 volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */
506 volatile u_int32_t hv_cmd_read_idx; /* arm->host */
507 volatile u_int32_t hv_resp_write_idx; /* arm->host */
508 volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */
512 * TYPHOON status register state (in TXP_A2H_0)
514 #define STAT_ROM_CODE 0x00000001
515 #define STAT_ROM_EEPROM_LOAD 0x00000002
516 #define STAT_WAITING_FOR_BOOT 0x00000007
517 #define STAT_RUNNING 0x00000009
518 #define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d
519 #define STAT_WAITING_FOR_SEGMENT 0x00000010
520 #define STAT_SLEEPING 0x00000011
521 #define STAT_HALTED 0x00000014
523 #define TX_ENTRIES 256
524 #define RX_ENTRIES 128
525 #define RXBUF_ENTRIES 256
526 #define CMD_ENTRIES 32
527 #define RSP_ENTRIES 32
529 #define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */
530 #define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */
531 #define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */
532 #define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */
533 #define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */
534 #define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */
535 #define OFFLOAD_VLAN 0x00000080 /* vlan enable */
536 #define OFFLOAD_FILTER 0x00000100 /* filter enable */
537 #define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */
538 #define OFFLOAD_MASK 0xfffffffe /* mask off low bit */
541 * Macros for converting array indices to offsets within the descriptor
542 * arrays. The chip operates on offsets, but it's much easier for us
543 * to operate on indices. Assumes descriptor entries are 16 bytes.
545 #define TXP_IDX2OFFSET(idx) ((idx) << 4)
546 #define TXP_OFFSET2IDX(off) ((off) >> 4)
548 struct txp_cmd_ring {
549 struct txp_cmd_desc *base;
554 struct txp_rsp_ring {
555 struct txp_rsp_desc *base;
561 struct txp_tx_desc *r_desc; /* base address of descs */
562 u_int32_t r_reg; /* register to activate */
563 u_int32_t r_prod; /* producer */
564 u_int32_t r_cons; /* consumer */
565 u_int32_t r_cnt; /* # descs in use */
566 volatile u_int32_t *r_off; /* hostvar index pointer */
570 struct mbuf * sd_mbuf;
575 struct txp_rx_desc *r_desc; /* base address of descs */
576 volatile u_int32_t *r_roff; /* hv read offset ptr */
577 volatile u_int32_t *r_woff; /* hv write offset ptr */
581 struct txp_boot_record txp_boot;
582 struct txp_hostvar txp_hostvar;
583 struct txp_tx_desc txp_txhiring[TX_ENTRIES];
584 struct txp_tx_desc txp_txloring[TX_ENTRIES];
585 struct txp_rxbuf_desc txp_rxbufs[RXBUF_ENTRIES];
586 struct txp_rx_desc txp_rxhiring[RX_ENTRIES];
587 struct txp_rx_desc txp_rxloring[RX_ENTRIES];
588 struct txp_cmd_desc txp_cmdring[CMD_ENTRIES];
589 struct txp_rsp_desc txp_rspring[RSP_ENTRIES];
594 struct arpcom sc_arpcom; /* ethernet common */
596 struct txp_hostvar *sc_hostvar;
597 struct txp_boot_record *sc_boot;
598 bus_space_handle_t sc_bh; /* bus handle (regs) */
599 bus_space_tag_t sc_bt; /* bus tag (regs) */
600 struct resource *sc_res;
601 struct resource *sc_irq;
604 struct txp_ldata *sc_ldata;
607 struct txp_cmd_ring sc_cmdring;
608 struct txp_rsp_ring sc_rspring;
609 struct txp_swdesc sc_txd[TX_ENTRIES];
610 struct callout_handle sc_tick;
611 struct ifmedia sc_ifmedia;
612 struct txp_tx_ring sc_txhir, sc_txlor;
613 struct txp_rxbuf_desc *sc_rxbufs;
614 struct txp_rx_ring sc_rxhir, sc_rxlor;
618 u_int32_t sc_rx_capability, sc_tx_capability;
621 #define TXP_DEVNAME(sc) ((sc)->sc_cold ? "" : (sc)->sc_dev.dv_xname)
623 struct txp_fw_file_header {
624 u_int8_t magicid[8]; /* TYPHOON\0 */
630 struct txp_fw_section_header {
637 #define TXP_MAX_SEGLEN 0xffff
638 #define TXP_MAX_PKTLEN 0x0800
640 #define WRITE_REG(sc,reg,val) \
641 bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
642 #define READ_REG(sc,reg) \
643 bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
646 * 3Com PCI vendor ID.
648 #define TXP_VENDORID_3COM 0x10B7
653 #define TXP_DEVICEID_3CR990_TX_95 0x9902
654 #define TXP_DEVICEID_3CR990_TX_97 0x9903
655 #define TXP_DEVICEID_3CR990B_TXM 0x9904
656 #define TXP_DEVICEID_3CR990_SRV_95 0x9908
657 #define TXP_DEVICEID_3CR990_SRV_97 0x9909
658 #define TXP_DEVICEID_3CR990B_SRV 0x990A