2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef _DEV_UART_BUS_H_
30 #define _DEV_UART_BUS_H_
36 #include <sys/serial.h>
37 #include <sys/timepps.h>
39 /* Drain and flush targets. */
40 #define UART_DRAIN_RECEIVER 0x0001
41 #define UART_DRAIN_TRANSMITTER 0x0002
42 #define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
43 #define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
45 /* Received character status bits. */
46 #define UART_STAT_BREAK 0x0100
47 #define UART_STAT_FRAMERR 0x0200
48 #define UART_STAT_OVERRUN 0x0400
49 #define UART_STAT_PARERR 0x0800
51 /* UART_IOCTL() requests */
52 #define UART_IOCTL_BREAK 1
53 #define UART_IOCTL_IFLOW 2
54 #define UART_IOCTL_OFLOW 3
55 #define UART_IOCTL_BAUD 4
58 #define UART_F_BUSY_DETECT 0x1
61 * UART class & instance (=softc)
65 struct uart_ops *uc_ops; /* Low-level console operations. */
66 u_int uc_range; /* Bus space address range. */
67 u_int uc_rclk; /* Default rclk for this device. */
68 u_int uc_rshift; /* Default regshift for this device. */
69 u_int uc_riowidth; /* Default reg io width for this device. */
74 struct uart_class *sc_class;
75 struct uart_bas sc_bas;
78 struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */
81 struct resource *sc_rres; /* Register resource. */
83 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
84 struct resource *sc_ires; /* Interrupt resource. */
87 struct callout sc_timer;
89 int sc_callout:1; /* This UART is opened for callout. */
90 int sc_fastintr:1; /* This UART uses fast interrupts. */
91 int sc_hwiflow:1; /* This UART has HW input flow ctl. */
92 int sc_hwoflow:1; /* This UART has HW output flow ctl. */
93 int sc_leaving:1; /* This UART is going away. */
94 int sc_opened:1; /* This UART is open for business. */
95 int sc_polled:1; /* This UART has no interrupts. */
96 int sc_txbusy:1; /* This UART is transmitting. */
97 int sc_isquelch:1; /* This UART has input squelched. */
98 int sc_testintr:1; /* This UART is under int. testing. */
100 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
102 int sc_altbrk; /* State for alt break sequence. */
103 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
110 int sc_rxfifosz; /* Size of RX FIFO. */
112 /* Transmitter data. */
115 int sc_txfifosz; /* Size of TX FIFO and buffer. */
117 /* Pulse capturing support (PPS). */
118 struct pps_state sc_pps;
120 sbintime_t sc_pps_captime;
122 /* Upper layer data. */
126 /* TTY specific data. */
130 /* Keyboard specific data. */
136 extern devclass_t uart_devclass;
137 extern const char uart_driver_name[];
139 int uart_bus_attach(device_t dev);
140 int uart_bus_detach(device_t dev);
141 int uart_bus_resume(device_t dev);
142 serdev_intr_t *uart_bus_ihand(device_t dev, int ipend);
143 int uart_bus_ipend(device_t dev);
144 int uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan, int quirks);
145 int uart_bus_sysdev(device_t dev);
147 void uart_sched_softih(struct uart_softc *, uint32_t);
149 int uart_tty_attach(struct uart_softc *);
150 int uart_tty_detach(struct uart_softc *);
151 struct mtx *uart_tty_getlock(struct uart_softc *);
152 void uart_tty_intr(void *arg);
155 * Receive buffer operations.
158 uart_rx_empty(struct uart_softc *sc)
161 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
165 uart_rx_full(struct uart_softc *sc)
168 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) ?
169 (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
173 uart_rx_get(struct uart_softc *sc)
178 if (ptr == sc->sc_rxput)
180 xc = sc->sc_rxbuf[ptr++];
181 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
186 uart_rx_next(struct uart_softc *sc)
191 if (ptr == sc->sc_rxput)
194 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
199 uart_rx_peek(struct uart_softc *sc)
204 return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]);
208 uart_rx_put(struct uart_softc *sc, int xc)
212 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
213 if (ptr == sc->sc_rxget)
215 sc->sc_rxbuf[sc->sc_rxput] = xc;
220 #endif /* _DEV_UART_BUS_H_ */