2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef _DEV_UART_BUS_H_
30 #define _DEV_UART_BUS_H_
36 #include <sys/serial.h>
37 #include <sys/timepps.h>
39 /* Drain and flush targets. */
40 #define UART_DRAIN_RECEIVER 0x0001
41 #define UART_DRAIN_TRANSMITTER 0x0002
42 #define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
43 #define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
46 * Interrupt sources (in priority order). See also uart_core.c
47 * Note that the low order 16 bits are used to pass modem signals
48 * from the hardware interrupt handler to the software interrupt
51 #define UART_IPEND_OVERRUN 0x010000
52 #define UART_IPEND_BREAK 0x020000
53 #define UART_IPEND_RXREADY 0x040000
54 #define UART_IPEND_SIGCHG 0x080000
55 #define UART_IPEND_TXIDLE 0x100000
57 #define UART_IPEND_MASK 0x1f0000
58 #define UART_IPEND_SIGMASK 0x00ffff
60 /* Received character status bits. */
61 #define UART_STAT_BREAK 0x0100
62 #define UART_STAT_FRAMERR 0x0200
63 #define UART_STAT_OVERRUN 0x0400
64 #define UART_STAT_PARERR 0x0800
66 #define UART_SIGMASK_DTE (SER_DTR | SER_RTS)
67 #define UART_SIGMASK_DCE (SER_DSR | SER_CTS | SER_DCD | SER_RI)
68 #define UART_SIGMASK_STATE (UART_SIGMASK_DTE | UART_SIGMASK_DCE)
69 #define UART_SIGMASK_DELTA (UART_SIGMASK_STATE << 8)
71 #ifdef UART_PPS_ON_CTS
72 #define UART_SIG_DPPS SER_DCTS
73 #define UART_SIG_PPS SER_CTS
75 #define UART_SIG_DPPS SER_DDCD
76 #define UART_SIG_PPS SER_DCD
79 /* UART_IOCTL() requests */
80 #define UART_IOCTL_BREAK 1
81 #define UART_IOCTL_IFLOW 2
82 #define UART_IOCTL_OFLOW 3
83 #define UART_IOCTL_BAUD 4
86 * UART class & instance (=softc)
90 u_int uc_range; /* Bus space address range. */
91 u_int uc_rclk; /* Default rclk for this device. */
94 extern struct uart_class uart_ns8250_class;
95 extern struct uart_class uart_sab82532_class;
96 extern struct uart_class uart_z8530_class;
100 struct uart_class *sc_class;
101 struct uart_bas sc_bas;
104 struct mtx sc_hwmtx; /* Spinlock protecting hardware. */
106 struct resource *sc_rres; /* Register resource. */
108 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
109 struct resource *sc_ires; /* Interrupt resource. */
113 int sc_callout:1; /* This UART is opened for callout. */
114 int sc_fastintr:1; /* This UART uses fast interrupts. */
115 int sc_hasfifo:1; /* This UART has FIFOs. */
116 int sc_hwiflow:1; /* This UART has HW input flow ctl. */
117 int sc_hwoflow:1; /* This UART has HW output flow ctl. */
118 int sc_leaving:1; /* This UART is going away. */
119 int sc_opened:1; /* This UART is open for business. */
120 int sc_polled:1; /* This UART has no interrupts. */
121 int sc_txbusy:1; /* This UART is transmitting. */
123 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
125 int sc_altbrk; /* State for alt break sequence. */
126 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
133 int sc_rxfifosz; /* Size of RX FIFO. */
135 /* Transmitter data. */
138 int sc_txfifosz; /* Size of TX FIFO and buffer. */
140 /* Pulse capturing support (PPS). */
141 struct pps_state sc_pps;
143 /* Upper layer data. */
147 /* TTY specific data. */
151 /* Keyboard specific data. */
157 extern devclass_t uart_devclass;
158 extern char uart_driver_name[];
160 int uart_bus_attach(device_t dev);
161 int uart_bus_detach(device_t dev);
162 int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
164 int uart_tty_attach(struct uart_softc *);
165 int uart_tty_detach(struct uart_softc *);
166 void uart_tty_intr(void *arg);
169 * Receive buffer operations.
172 uart_rx_empty(struct uart_softc *sc)
174 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
178 uart_rx_full(struct uart_softc *sc)
180 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz)
181 ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
185 uart_rx_get(struct uart_softc *sc)
190 if (ptr == sc->sc_rxput)
192 xc = sc->sc_rxbuf[ptr++];
193 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
198 uart_rx_put(struct uart_softc *sc, int xc)
202 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
203 if (ptr == sc->sc_rxget)
205 sc->sc_rxbuf[sc->sc_rxput] = xc;
210 #endif /* _DEV_UART_BUS_H_ */