2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Marcel Moolenaar All rights reserved.
5 * Copyright (c) 2001 M. Warner Losh <imp@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <machine/bus.h>
39 #include <machine/resource.h>
41 #include <dev/pci/pcivar.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_bus.h>
45 #include <dev/uart/uart_cpu.h>
47 #define DEFAULT_RCLK 1843200
49 static int uart_pci_probe(device_t dev);
50 static int uart_pci_attach(device_t dev);
51 static int uart_pci_detach(device_t dev);
53 static device_method_t uart_pci_methods[] = {
54 /* Device interface */
55 DEVMETHOD(device_probe, uart_pci_probe),
56 DEVMETHOD(device_attach, uart_pci_attach),
57 DEVMETHOD(device_detach, uart_pci_detach),
58 DEVMETHOD(device_resume, uart_bus_resume),
62 static driver_t uart_pci_driver = {
65 sizeof(struct uart_softc),
79 struct pci_unique_id {
84 static const struct pci_id pci_ns8250_ids[] = {
85 { 0x1028, 0x0008, 0xffff, 0, "Dell Remote Access Card III", 0x14,
87 { 0x1028, 0x0012, 0xffff, 0, "Dell RAC 4 Daughter Card Virtual UART", 0x14,
89 { 0x1033, 0x0074, 0x1033, 0x8014, "NEC RCV56ACF 56k Voice Modem", 0x10 },
90 { 0x1033, 0x007d, 0x1033, 0x8012, "NEC RS232C", 0x10 },
91 { 0x103c, 0x1048, 0x103c, 0x1227, "HP Diva Serial [GSP] UART - Powerbar SP2",
93 { 0x103c, 0x1048, 0x103c, 0x1301, "HP Diva RMP3", 0x14 },
94 { 0x103c, 0x1290, 0xffff, 0, "HP Auxiliary Diva Serial Port", 0x18 },
95 { 0x103c, 0x3301, 0xffff, 0, "HP iLO serial port", 0x10 },
96 { 0x11c1, 0x0480, 0xffff, 0, "Agere Systems Venus Modem (V90, 56KFlex)", 0x14 },
97 { 0x115d, 0x0103, 0xffff, 0, "Xircom Cardbus Ethernet + 56k Modem", 0x10 },
98 { 0x125b, 0x9100, 0xa000, 0x1000,
99 "ASIX AX99100 PCIe 1/2/3/4-port RS-232/422/485", 0x10 },
100 { 0x1282, 0x6585, 0xffff, 0, "Davicom 56PDV PCI Modem", 0x10 },
101 { 0x12b9, 0x1008, 0xffff, 0, "3Com 56K FaxModem Model 5610", 0x10 },
102 { 0x131f, 0x1000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x18 },
103 { 0x131f, 0x1001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x18 },
104 { 0x131f, 0x1002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x18 },
105 { 0x131f, 0x2000, 0xffff, 0, "Siig CyberSerial (1-port) 16550", 0x10 },
106 { 0x131f, 0x2001, 0xffff, 0, "Siig CyberSerial (1-port) 16650", 0x10 },
107 { 0x131f, 0x2002, 0xffff, 0, "Siig CyberSerial (1-port) 16850", 0x10 },
108 { 0x135c, 0x0190, 0xffff, 0, "Quatech SSCLP-100", 0x18 },
109 { 0x135c, 0x01c0, 0xffff, 0, "Quatech SSCLP-200/300", 0x18 },
110 { 0x135e, 0x7101, 0xffff, 0, "Sealevel Systems Single Port RS-232/422/485/530",
112 { 0x1407, 0x0110, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port A", 0x10 },
113 { 0x1407, 0x0111, 0xffff, 0, "Lava Computer mfg DSerial-PCI Port B", 0x10 },
114 { 0x1407, 0x0510, 0xffff, 0, "Lava SP Serial 550 PCI", 0x10 },
115 { 0x1409, 0x7168, 0x1409, 0x4025, "Timedia Technology Serial Port", 0x10,
117 { 0x1409, 0x7168, 0x1409, 0x4027, "Timedia Technology Serial Port", 0x10,
119 { 0x1409, 0x7168, 0x1409, 0x4028, "Timedia Technology Serial Port", 0x10,
121 { 0x1409, 0x7168, 0x1409, 0x5025, "Timedia Technology Serial Port", 0x10,
123 { 0x1409, 0x7168, 0x1409, 0x5027, "Timedia Technology Serial Port", 0x10,
125 { 0x1415, 0x950b, 0xffff, 0, "Oxford Semiconductor OXCB950 Cardbus 16950 UART",
127 { 0x1415, 0xc120, 0xffff, 0, "Oxford Semiconductor OXPCIe952 PCIe 16950 UART",
129 { 0x14e4, 0x160a, 0xffff, 0, "Broadcom TruManage UART", 0x10,
130 128 * DEFAULT_RCLK, 2},
131 { 0x14e4, 0x4344, 0xffff, 0, "Sony Ericsson GC89 PC Card", 0x10},
132 { 0x151f, 0x0000, 0xffff, 0, "TOPIC Semiconductor TP560 56k modem", 0x10 },
133 { 0x1d0f, 0x8250, 0x0000, 0, "Amazon PCI serial device", 0x10 },
134 { 0x1d0f, 0x8250, 0x1d0f, 0, "Amazon PCI serial device", 0x10 },
135 { 0x1fd4, 0x1999, 0x1fd4, 0x0001, "Sunix SER5xxxx Serial Port", 0x10,
137 { 0x8086, 0x0f0a, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#1", 0x10,
138 24 * DEFAULT_RCLK, 2 },
139 { 0x8086, 0x0f0c, 0xffff, 0, "Intel ValleyView LPIO1 HSUART#2", 0x10,
140 24 * DEFAULT_RCLK, 2 },
141 { 0x8086, 0x108f, 0xffff, 0, "Intel AMT - SOL", 0x10 },
142 { 0x8086, 0x19d8, 0xffff, 0, "Intel Denverton UART", 0x10 },
143 { 0x8086, 0x1c3d, 0xffff, 0, "Intel AMT - KT Controller", 0x10 },
144 { 0x8086, 0x1d3d, 0xffff, 0, "Intel C600/X79 Series Chipset KT Controller",
146 { 0x8086, 0x1e3d, 0xffff, 0, "Intel Panther Point KT Controller", 0x10 },
147 { 0x8086, 0x228a, 0xffff, 0, "Intel Cherryview SIO HSUART#1", 0x10,
148 24 * DEFAULT_RCLK, 2 },
149 { 0x8086, 0x228c, 0xffff, 0, "Intel Cherryview SIO HSUART#2", 0x10,
150 24 * DEFAULT_RCLK, 2 },
151 { 0x8086, 0x2a07, 0xffff, 0, "Intel AMT - PM965/GM965 KT Controller", 0x10 },
152 { 0x8086, 0x2a47, 0xffff, 0, "Mobile 4 Series Chipset KT Controller", 0x10 },
153 { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 },
154 { 0x8086, 0x31bc, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 0", 0x10,
155 24 * DEFAULT_RCLK, 2 },
156 { 0x8086, 0x31be, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 1", 0x10,
157 24 * DEFAULT_RCLK, 2 },
158 { 0x8086, 0x31c0, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 2", 0x10,
159 24 * DEFAULT_RCLK, 2 },
160 { 0x8086, 0x31ee, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 3", 0x10,
161 24 * DEFAULT_RCLK, 2 },
162 { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller",
164 { 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10,
165 24 * DEFAULT_RCLK, 2 },
166 { 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10,
167 24 * DEFAULT_RCLK, 2 },
168 { 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10,
169 24 * DEFAULT_RCLK, 2 },
170 { 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10,
171 24 * DEFAULT_RCLK, 2 },
172 { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
173 { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
174 { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },
175 { 0x8086, 0x8814, 0xffff, 0, "Intel EG20T Serial Port 3", 0x10 },
176 { 0x8086, 0x8c3d, 0xffff, 0, "Intel Lynx Point KT Controller", 0x10 },
177 { 0x8086, 0x8cbd, 0xffff, 0, "Intel Wildcat Point KT Controller", 0x10 },
178 { 0x8086, 0x8d3d, 0xffff, 0,
179 "Intel Corporation C610/X99 series chipset KT Controller", 0x10 },
180 { 0x8086, 0x9c3d, 0xffff, 0, "Intel Lynx Point-LP HECI KT", 0x10 },
181 { 0x8086, 0xa13d, 0xffff, 0,
182 "100 Series/C230 Series Chipset Family KT Redirection", 0x10 },
183 { 0x9710, 0x9820, 0x1000, 1, "NetMos NM9820 Serial Port", 0x10 },
184 { 0x9710, 0x9835, 0x1000, 1, "NetMos NM9835 Serial Port", 0x10 },
185 { 0x9710, 0x9865, 0xa000, 0x1000, "NetMos NM9865 Serial Port", 0x10 },
186 { 0x9710, 0x9900, 0xa000, 0x1000,
187 "MosChip MCS9900 PCIe to Peripheral Controller", 0x10 },
188 { 0x9710, 0x9901, 0xa000, 0x1000,
189 "MosChip MCS9901 PCIe to Peripheral Controller", 0x10 },
190 { 0x9710, 0x9904, 0xa000, 0x1000,
191 "MosChip MCS9904 PCIe to Peripheral Controller", 0x10 },
192 { 0x9710, 0x9922, 0xa000, 0x1000,
193 "MosChip MCS9922 PCIe to Peripheral Controller", 0x10 },
194 { 0xdeaf, 0x9051, 0xffff, 0, "Middle Digital PC Weasel Serial Port", 0x10 },
195 { 0xffff, 0, 0xffff, 0, NULL, 0, 0}
198 const static struct pci_id *
199 uart_pci_match(device_t dev, const struct pci_id *id)
201 uint16_t device, subdev, subven, vendor;
203 vendor = pci_get_vendor(dev);
204 device = pci_get_device(dev);
205 while (id->vendor != 0xffff &&
206 (id->vendor != vendor || id->device != device))
208 if (id->vendor == 0xffff)
210 if (id->subven == 0xffff)
212 subven = pci_get_subvendor(dev);
213 subdev = pci_get_subdevice(dev);
214 while (id->vendor == vendor && id->device == device &&
215 (id->subven != subven || id->subdev != subdev))
217 return ((id->vendor == vendor && id->device == device) ? id : NULL);
220 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
222 /* PCI vendor/device pairs of devices guaranteed to be unique on a system. */
223 static const struct pci_unique_id pci_unique_devices[] = {
224 { 0x1d0f, 0x8250 } /* Amazon PCI serial device */
227 /* Match a UART to a console if it's a PCI device known to be unique. */
229 uart_pci_unique_console_match(device_t dev)
231 struct uart_softc *sc;
232 struct uart_devinfo * sysdev;
233 const struct pci_unique_id * id;
234 uint16_t vendor, device;
236 sc = device_get_softc(dev);
237 vendor = pci_get_vendor(dev);
238 device = pci_get_device(dev);
240 /* Is this a device known to exist only once in a system? */
241 for (id = pci_unique_devices; ; id++) {
242 if (id == &pci_unique_devices[nitems(pci_unique_devices)])
244 if (id->vendor == vendor && id->device == device)
248 /* If it matches a console, it must be the same device. */
249 SLIST_FOREACH(sysdev, &uart_sysdevs, next) {
250 if (sysdev->pci_info.vendor == vendor &&
251 sysdev->pci_info.device == device) {
252 sc->sc_sysdev = sysdev;
253 sysdev->bas.rclk = sc->sc_bas.rclk;
259 uart_pci_probe(device_t dev)
261 struct uart_softc *sc;
262 const struct pci_id *id;
265 sc = device_get_softc(dev);
267 id = uart_pci_match(dev, pci_ns8250_ids);
269 sc->sc_class = &uart_ns8250_class;
272 /* Add checks for non-ns8250 IDs here. */
276 result = uart_bus_probe(dev, id->regshft, 0, id->rclk, id->rid, 0, 0);
277 /* Bail out on error. */
281 * If we haven't already matched this to a console, check if it's a
282 * PCI device which is known to only exist once in any given system
283 * and we can match it that way.
285 if (sc->sc_sysdev == NULL)
286 uart_pci_unique_console_match(dev);
287 /* Set/override the device description. */
289 device_set_desc(dev, id->desc);
294 uart_pci_attach(device_t dev)
296 struct uart_softc *sc;
299 sc = device_get_softc(dev);
302 * Use MSI in preference to legacy IRQ if available. However, experience
303 * suggests this is only reliable when one MSI vector is advertised.
305 if (pci_msi_count(dev) == 1) {
307 if (pci_alloc_msi(dev, &count) == 0) {
309 device_printf(dev, "Using %d MSI message\n", count);
313 return (uart_bus_attach(dev));
317 uart_pci_detach(device_t dev)
319 struct uart_softc *sc;
321 sc = device_get_softc(dev);
323 if (sc->sc_irid != 0)
324 pci_release_msi(dev);
326 return (uart_bus_detach(dev));
329 DRIVER_MODULE(uart, pci, uart_pci_driver, uart_devclass, NULL, NULL);