2 * Copyright (c) 2012 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
40 #include <machine/bus.h>
41 #include <machine/fdt.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_cpu.h>
45 #include <dev/uart/uart_bus.h>
47 #include <dev/uart/uart_dev_imx5xx.h>
51 * Low-level UART interface.
53 static int imx_uart_probe(struct uart_bas *bas);
54 static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
55 static void imx_uart_term(struct uart_bas *bas);
56 static void imx_uart_putc(struct uart_bas *bas, int);
57 static int imx_uart_rxready(struct uart_bas *bas);
58 static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
60 static struct uart_ops uart_imx_uart_ops = {
61 .probe = imx_uart_probe,
62 .init = imx_uart_init,
63 .term = imx_uart_term,
64 .putc = imx_uart_putc,
65 .rxready = imx_uart_rxready,
66 .getc = imx_uart_getc,
70 imx_uart_probe(struct uart_bas *bas)
77 imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
78 int stopbits, int parity)
84 imx_uart_term(struct uart_bas *bas)
90 imx_uart_putc(struct uart_bas *bas, int c)
93 while (!(IS(bas, USR2, TXFE)))
95 SETREG(bas, REG(UTXD), c);
99 imx_uart_rxready(struct uart_bas *bas)
102 return ((IS(bas, USR2, RDR)) ? 1 : 0);
106 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
111 while (!(IS(bas, USR2, RDR)))
114 c = GETREG(bas, REG(URXD));
117 if (c & FLD(URXD, BRK)) {
126 * High-level UART interface.
128 struct imx_uart_softc {
129 struct uart_softc base;
132 static int imx_uart_bus_attach(struct uart_softc *);
133 static int imx_uart_bus_detach(struct uart_softc *);
134 static int imx_uart_bus_flush(struct uart_softc *, int);
135 static int imx_uart_bus_getsig(struct uart_softc *);
136 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
137 static int imx_uart_bus_ipend(struct uart_softc *);
138 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
139 static int imx_uart_bus_probe(struct uart_softc *);
140 static int imx_uart_bus_receive(struct uart_softc *);
141 static int imx_uart_bus_setsig(struct uart_softc *, int);
142 static int imx_uart_bus_transmit(struct uart_softc *);
144 static kobj_method_t imx_uart_methods[] = {
145 KOBJMETHOD(uart_attach, imx_uart_bus_attach),
146 KOBJMETHOD(uart_detach, imx_uart_bus_detach),
147 KOBJMETHOD(uart_flush, imx_uart_bus_flush),
148 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
149 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
150 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
151 KOBJMETHOD(uart_param, imx_uart_bus_param),
152 KOBJMETHOD(uart_probe, imx_uart_bus_probe),
153 KOBJMETHOD(uart_receive, imx_uart_bus_receive),
154 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
155 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
159 struct uart_class uart_imx_class = {
162 sizeof(struct imx_uart_softc),
163 .uc_ops = &uart_imx_uart_ops,
165 .uc_rclk = 24000000 /* TODO: get value from CCM */
168 #define SIGCHG(c, i, s, d) \
170 i |= (i & s) ? s : s | d; \
172 i = (i & s) ? (i & ~s) | d : i; \
176 imx_uart_bus_attach(struct uart_softc *sc)
178 struct uart_bas *bas;
179 struct uart_devinfo *di;
182 if (sc->sc_sysdev != NULL) {
184 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
187 imx_uart_init(bas, 115200, 8, 1, 0);
190 (void)imx_uart_bus_getsig(sc);
192 /* XXX workaround to have working console on manut prompt */
193 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE){
194 DIS(bas, UCR4, DREN);
196 ENA(bas, UCR4, DREN);
198 DIS(bas, UCR1, RRDYEN);
199 DIS(bas, UCR1, IDEN);
200 DIS(bas, UCR3, RXDSEN);
201 DIS(bas, UCR2, ATEN);
202 DIS(bas, UCR1, TXMPTYEN);
203 DIS(bas, UCR1, TRDYEN);
204 DIS(bas, UCR4, TCEN);
205 DIS(bas, UCR4, OREN);
206 ENA(bas, UCR4, BKEN);
207 DIS(bas, UCR4, WKEN);
208 DIS(bas, UCR1, ADEN);
209 DIS(bas, UCR3, ACIEN);
210 DIS(bas, UCR2, ESCI);
211 DIS(bas, UCR4, ENIRI);
212 DIS(bas, UCR3, AIRINTEN);
213 DIS(bas, UCR3, AWAKEN);
214 DIS(bas, UCR3, FRAERREN);
215 DIS(bas, UCR3, PARERREN);
216 DIS(bas, UCR1, RTSDEN);
217 DIS(bas, UCR2, RTSEN);
218 DIS(bas, UCR3, DTREN);
221 DIS(bas, UCR3, DTRDEN);
223 /* ACK all interrupts */
224 SETREG(bas, REG(USR1), 0xffff);
225 SETREG(bas, REG(USR2), 0xffff);
230 imx_uart_bus_detach(struct uart_softc *sc)
233 SETREG(&sc->sc_bas, REG(UCR4), 0);
239 imx_uart_bus_flush(struct uart_softc *sc, int what)
247 imx_uart_bus_getsig(struct uart_softc *sc)
249 uint32_t new, old, sig;
255 uart_lock(sc->sc_hwmtx);
256 bes = GETREG(&sc->sc_bas, REG(USR2));
257 uart_unlock(sc->sc_hwmtx);
258 /* XXX: chip can show delta */
259 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
260 new = sig & ~SER_MASK_DELTA;
261 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
267 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
269 struct uart_bas *bas;
274 uart_lock(sc->sc_hwmtx);
276 case UART_IOCTL_BREAK:
279 case UART_IOCTL_BAUD:
281 *(int*)data = 115200;
287 uart_unlock(sc->sc_hwmtx);
293 imx_uart_bus_ipend(struct uart_softc *sc)
295 struct uart_bas *bas;
303 uart_lock(sc->sc_hwmtx);
305 /* Read pending interrupts */
306 usr1 = GETREG(bas, REG(USR1));
307 usr2 = GETREG(bas, REG(USR2));
309 SETREG(bas, REG(USR1), usr1);
310 SETREG(bas, REG(USR2), usr2);
312 ucr1 = GETREG(bas, REG(UCR1));
313 ucr4 = GETREG(bas, REG(UCR4));
315 if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) {
316 DIS(bas, UCR1, TXMPTYEN);
318 ipend |= SER_INT_TXIDLE;
320 if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) {
321 DIS(bas, UCR4, DREN);
322 /* Wow, new char on input */
323 ipend |= SER_INT_RXREADY;
325 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
326 ipend |= SER_INT_BREAK;
328 uart_unlock(sc->sc_hwmtx);
334 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
335 int stopbits, int parity)
338 uart_lock(sc->sc_hwmtx);
339 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
340 uart_unlock(sc->sc_hwmtx);
345 imx_uart_bus_probe(struct uart_softc *sc)
349 error = imx_uart_probe(&sc->sc_bas);
356 device_set_desc(sc->sc_dev, "imx_uart");
361 imx_uart_bus_receive(struct uart_softc *sc)
363 struct uart_bas *bas;
367 uart_lock(sc->sc_hwmtx);
369 /* Read while we have anything in FIFO */
370 while (IS(bas, USR2, RDR)) {
371 if (uart_rx_full(sc)) {
372 /* No space left in input buffer */
373 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
377 xc = GETREG(bas, REG(URXD));
379 /* We have valid char */
380 if (xc & FLD(URXD, CHARRDY))
381 out = xc & 0x000000ff;
383 if (xc & FLD(URXD, FRMERR))
384 out |= UART_STAT_FRAMERR;
385 if (xc & FLD(URXD, PRERR))
386 out |= UART_STAT_PARERR;
387 if (xc & FLD(URXD, OVRRUN))
388 out |= UART_STAT_OVERRUN;
389 if (xc & FLD(URXD, BRK))
390 out |= UART_STAT_BREAK;
392 uart_rx_put(sc, out);
394 /* Reenable Data Ready interrupt */
395 ENA(bas, UCR4, DREN);
397 uart_unlock(sc->sc_hwmtx);
402 imx_uart_bus_setsig(struct uart_softc *sc, int sig)
405 /* TODO: implement (?) */
407 /* XXX workaround to have working console on mount prompt */
408 /* Enable RX interrupt */
409 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
410 if (!IS(&sc->sc_bas, UCR4, DREN))
411 ENA(&sc->sc_bas, UCR4, DREN);
416 imx_uart_bus_transmit(struct uart_softc *sc)
418 struct uart_bas *bas = &sc->sc_bas;
422 uart_lock(sc->sc_hwmtx);
425 for (i = 0; i < sc->sc_txdatasz; i++) {
426 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
430 /* Call me when ready */
431 ENA(bas, UCR1, TXMPTYEN);
433 uart_unlock(sc->sc_hwmtx);