2 * Copyright (c) 2012 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
40 #include <machine/bus.h>
41 #include <machine/fdt.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_cpu.h>
45 #include <dev/uart/uart_bus.h>
47 #include <dev/uart/uart_dev_imx5xx.h>
51 * Low-level UART interface.
53 static int imx_uart_probe(struct uart_bas *bas);
54 static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
55 static void imx_uart_term(struct uart_bas *bas);
56 static void imx_uart_putc(struct uart_bas *bas, int);
57 static int imx_uart_rxready(struct uart_bas *bas);
58 static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
60 static struct uart_ops uart_imx_uart_ops = {
61 .probe = imx_uart_probe,
62 .init = imx_uart_init,
63 .term = imx_uart_term,
64 .putc = imx_uart_putc,
65 .rxready = imx_uart_rxready,
66 .getc = imx_uart_getc,
70 imx_uart_probe(struct uart_bas *bas)
77 imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
78 int stopbits, int parity)
84 imx_uart_term(struct uart_bas *bas)
90 imx_uart_putc(struct uart_bas *bas, int c)
93 while (!(IS(bas, USR2, TXFE)))
95 SETREG(bas, REG(UTXD), c);
99 imx_uart_rxready(struct uart_bas *bas)
102 return ((IS(bas, USR2, RDR)) ? 1 : 0);
106 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
111 while (!(IS(bas, USR2, RDR)))
114 c = GETREG(bas, REG(URXD));
117 if (c & FLD(URXD, BRK)) {
126 * High-level UART interface.
128 struct imx_uart_softc {
129 struct uart_softc base;
132 static int imx_uart_bus_attach(struct uart_softc *);
133 static int imx_uart_bus_detach(struct uart_softc *);
134 static int imx_uart_bus_flush(struct uart_softc *, int);
135 static int imx_uart_bus_getsig(struct uart_softc *);
136 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
137 static int imx_uart_bus_ipend(struct uart_softc *);
138 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
139 static int imx_uart_bus_probe(struct uart_softc *);
140 static int imx_uart_bus_receive(struct uart_softc *);
141 static int imx_uart_bus_setsig(struct uart_softc *, int);
142 static int imx_uart_bus_transmit(struct uart_softc *);
143 static void imx_uart_bus_grab(struct uart_softc *);
144 static void imx_uart_bus_ungrab(struct uart_softc *);
146 static kobj_method_t imx_uart_methods[] = {
147 KOBJMETHOD(uart_attach, imx_uart_bus_attach),
148 KOBJMETHOD(uart_detach, imx_uart_bus_detach),
149 KOBJMETHOD(uart_flush, imx_uart_bus_flush),
150 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
151 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
152 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
153 KOBJMETHOD(uart_param, imx_uart_bus_param),
154 KOBJMETHOD(uart_probe, imx_uart_bus_probe),
155 KOBJMETHOD(uart_receive, imx_uart_bus_receive),
156 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
157 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
158 KOBJMETHOD(uart_grab, imx_uart_bus_grab),
159 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab),
163 struct uart_class uart_imx_class = {
166 sizeof(struct imx_uart_softc),
167 .uc_ops = &uart_imx_uart_ops,
169 .uc_rclk = 24000000 /* TODO: get value from CCM */
172 #define SIGCHG(c, i, s, d) \
174 i |= (i & s) ? s : s | d; \
176 i = (i & s) ? (i & ~s) | d : i; \
180 imx_uart_bus_attach(struct uart_softc *sc)
182 struct uart_bas *bas;
183 struct uart_devinfo *di;
186 if (sc->sc_sysdev != NULL) {
188 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
191 imx_uart_init(bas, 115200, 8, 1, 0);
194 (void)imx_uart_bus_getsig(sc);
196 ENA(bas, UCR4, DREN);
197 DIS(bas, UCR1, RRDYEN);
198 DIS(bas, UCR1, IDEN);
199 DIS(bas, UCR3, RXDSEN);
200 DIS(bas, UCR2, ATEN);
201 DIS(bas, UCR1, TXMPTYEN);
202 DIS(bas, UCR1, TRDYEN);
203 DIS(bas, UCR4, TCEN);
204 DIS(bas, UCR4, OREN);
205 ENA(bas, UCR4, BKEN);
206 DIS(bas, UCR4, WKEN);
207 DIS(bas, UCR1, ADEN);
208 DIS(bas, UCR3, ACIEN);
209 DIS(bas, UCR2, ESCI);
210 DIS(bas, UCR4, ENIRI);
211 DIS(bas, UCR3, AIRINTEN);
212 DIS(bas, UCR3, AWAKEN);
213 DIS(bas, UCR3, FRAERREN);
214 DIS(bas, UCR3, PARERREN);
215 DIS(bas, UCR1, RTSDEN);
216 DIS(bas, UCR2, RTSEN);
217 DIS(bas, UCR3, DTREN);
220 DIS(bas, UCR3, DTRDEN);
222 /* ACK all interrupts */
223 SETREG(bas, REG(USR1), 0xffff);
224 SETREG(bas, REG(USR2), 0xffff);
229 imx_uart_bus_detach(struct uart_softc *sc)
232 SETREG(&sc->sc_bas, REG(UCR4), 0);
238 imx_uart_bus_flush(struct uart_softc *sc, int what)
246 imx_uart_bus_getsig(struct uart_softc *sc)
248 uint32_t new, old, sig;
254 uart_lock(sc->sc_hwmtx);
255 bes = GETREG(&sc->sc_bas, REG(USR2));
256 uart_unlock(sc->sc_hwmtx);
257 /* XXX: chip can show delta */
258 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
259 new = sig & ~SER_MASK_DELTA;
260 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
266 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
268 struct uart_bas *bas;
273 uart_lock(sc->sc_hwmtx);
275 case UART_IOCTL_BREAK:
278 case UART_IOCTL_BAUD:
280 *(int*)data = 115200;
286 uart_unlock(sc->sc_hwmtx);
292 imx_uart_bus_ipend(struct uart_softc *sc)
294 struct uart_bas *bas;
302 uart_lock(sc->sc_hwmtx);
304 /* Read pending interrupts */
305 usr1 = GETREG(bas, REG(USR1));
306 usr2 = GETREG(bas, REG(USR2));
308 SETREG(bas, REG(USR1), usr1);
309 SETREG(bas, REG(USR2), usr2);
311 ucr1 = GETREG(bas, REG(UCR1));
312 ucr4 = GETREG(bas, REG(UCR4));
314 if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) {
315 DIS(bas, UCR1, TXMPTYEN);
317 ipend |= SER_INT_TXIDLE;
319 if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) {
320 DIS(bas, UCR4, DREN);
321 /* Wow, new char on input */
322 ipend |= SER_INT_RXREADY;
324 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
325 ipend |= SER_INT_BREAK;
327 uart_unlock(sc->sc_hwmtx);
333 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
334 int stopbits, int parity)
337 uart_lock(sc->sc_hwmtx);
338 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
339 uart_unlock(sc->sc_hwmtx);
344 imx_uart_bus_probe(struct uart_softc *sc)
348 error = imx_uart_probe(&sc->sc_bas);
355 device_set_desc(sc->sc_dev, "imx_uart");
360 imx_uart_bus_receive(struct uart_softc *sc)
362 struct uart_bas *bas;
366 uart_lock(sc->sc_hwmtx);
368 /* Read while we have anything in FIFO */
369 while (IS(bas, USR2, RDR)) {
370 if (uart_rx_full(sc)) {
371 /* No space left in input buffer */
372 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
376 xc = GETREG(bas, REG(URXD));
378 /* We have valid char */
379 if (xc & FLD(URXD, CHARRDY))
380 out = xc & 0x000000ff;
382 if (xc & FLD(URXD, FRMERR))
383 out |= UART_STAT_FRAMERR;
384 if (xc & FLD(URXD, PRERR))
385 out |= UART_STAT_PARERR;
386 if (xc & FLD(URXD, OVRRUN))
387 out |= UART_STAT_OVERRUN;
388 if (xc & FLD(URXD, BRK))
389 out |= UART_STAT_BREAK;
391 uart_rx_put(sc, out);
393 /* Reenable Data Ready interrupt */
394 ENA(bas, UCR4, DREN);
396 uart_unlock(sc->sc_hwmtx);
401 imx_uart_bus_setsig(struct uart_softc *sc, int sig)
408 imx_uart_bus_transmit(struct uart_softc *sc)
410 struct uart_bas *bas = &sc->sc_bas;
414 uart_lock(sc->sc_hwmtx);
417 for (i = 0; i < sc->sc_txdatasz; i++) {
418 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
422 /* Call me when ready */
423 ENA(bas, UCR1, TXMPTYEN);
425 uart_unlock(sc->sc_hwmtx);
431 imx_uart_bus_grab(struct uart_softc *sc)
433 struct uart_bas *bas = &sc->sc_bas;
436 uart_lock(sc->sc_hwmtx);
437 DIS(bas, UCR4, DREN);
438 uart_unlock(sc->sc_hwmtx);
442 imx_uart_bus_ungrab(struct uart_softc *sc)
444 struct uart_bas *bas = &sc->sc_bas;
447 uart_lock(sc->sc_hwmtx);
448 ENA(bas, UCR4, DREN);
449 uart_unlock(sc->sc_hwmtx);