2 * Copyright (c) 2012 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
40 #include <machine/bus.h>
41 #include <machine/fdt.h>
43 #include <dev/uart/uart.h>
44 #include <dev/uart/uart_cpu.h>
45 #include <dev/uart/uart_cpu_fdt.h>
46 #include <dev/uart/uart_bus.h>
47 #include <dev/uart/uart_dev_imx.h>
50 #include <arm/freescale/imx/imx_ccmvar.h>
53 * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes
54 * available to read or space for 24 more bytes to write. While 8 bytes of
55 * slack before over/underrun might seem excessive, the hardware can run at
56 * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS
57 * to get into the interrupt handler and service the fifo.
60 #define IMX_RXFIFO_LEVEL 24
61 #define IMX_TXFIFO_LEVEL 24
64 * Low-level UART interface.
66 static int imx_uart_probe(struct uart_bas *bas);
67 static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
68 static void imx_uart_term(struct uart_bas *bas);
69 static void imx_uart_putc(struct uart_bas *bas, int);
70 static int imx_uart_rxready(struct uart_bas *bas);
71 static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
73 static struct uart_ops uart_imx_uart_ops = {
74 .probe = imx_uart_probe,
75 .init = imx_uart_init,
76 .term = imx_uart_term,
77 .putc = imx_uart_putc,
78 .rxready = imx_uart_rxready,
79 .getc = imx_uart_getc,
82 #if 0 /* Handy when debugging. */
84 dumpregs(struct uart_bas *bas, const char * msg)
89 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x "
90 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n",
92 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),
93 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),
94 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));
99 imx_uart_probe(struct uart_bas *bas)
106 imx_uart_getbaud(struct uart_bas *bas)
108 uint32_t rate, ubir, ubmr;
109 u_int baud, blo, bhi, i;
110 static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1};
111 static const u_int std_rates[] = {
112 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600
116 * Get the baud rate the hardware is programmed for, then search the
117 * table of standard baud rates for a number that's within 3% of the
118 * actual rate the hardware is programmed for. It's more comforting to
119 * see that your console is running at 115200 than 114942. Note that
120 * here we cannot make a simplifying assumption that the predivider and
121 * numerator are 1 (like we do when setting the baud rate), because we
122 * don't know what u-boot might have set up.
124 i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >>
125 IMXUART_UFCR_RFDIV_SHIFT;
126 rate = imx_ccm_uart_hz() / predivs[i];
127 ubir = GETREG(bas, REG(UBIR)) + 1;
128 ubmr = GETREG(bas, REG(UBMR)) + 1;
129 baud = ((rate / 16 ) * ubir) / ubmr;
131 blo = (baud * 100) / 103;
132 bhi = (baud * 100) / 97;
133 for (i = 0; i < nitems(std_rates); i++) {
135 if (rate >= blo && rate <= bhi) {
145 imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
146 int stopbits, int parity)
148 uint32_t baseclk, reg;
150 /* Enable the device and the RX/TX channels. */
151 SET(bas, REG(UCR1), FLD(UCR1, UARTEN));
152 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));
160 ENA(bas, UCR2, STPB);
162 DIS(bas, UCR2, STPB);
165 case UART_PARITY_ODD:
166 DIS(bas, UCR2, PROE);
167 ENA(bas, UCR2, PREN);
169 case UART_PARITY_EVEN:
170 ENA(bas, UCR2, PROE);
171 ENA(bas, UCR2, PREN);
173 case UART_PARITY_MARK:
174 case UART_PARITY_SPACE:
175 /* FALLTHROUGH: Hardware doesn't support mark/space. */
176 case UART_PARITY_NONE:
178 DIS(bas, UCR2, PREN);
183 * The hardware has an extremely flexible baud clock: it allows setting
184 * both the numerator and denominator of the divider, as well as a
185 * separate pre-divider. We simplify the problem of coming up with a
186 * workable pair of numbers by assuming a pre-divider and numerator of
187 * one because our base clock is so fast we can reach virtually any
188 * reasonable speed with a simple divisor. The numerator value actually
189 * includes the 16x over-sampling (so a value of 16 means divide by 1);
190 * the register value is the numerator-1, so we have a hard-coded 15.
191 * Note that a quirk of the hardware requires that both UBIR and UBMR be
192 * set back to back in order for the change to take effect.
195 baseclk = imx_ccm_uart_hz();
196 reg = GETREG(bas, REG(UFCR));
197 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;
198 SETREG(bas, REG(UFCR), reg);
199 SETREG(bas, REG(UBIR), 15);
200 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);
204 * Program the tx lowater and rx hiwater levels at which fifo-service
205 * interrupts are signaled. The tx value is interpetted as "when there
206 * are only this many bytes remaining" (not "this many free").
208 reg = GETREG(bas, REG(UFCR));
209 reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK);
210 reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT;
211 reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT;
212 SETREG(bas, REG(UFCR), reg);
216 imx_uart_term(struct uart_bas *bas)
222 imx_uart_putc(struct uart_bas *bas, int c)
225 while (!(IS(bas, USR1, TRDY)))
227 SETREG(bas, REG(UTXD), c);
231 imx_uart_rxready(struct uart_bas *bas)
234 return ((IS(bas, USR2, RDR)) ? 1 : 0);
238 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
243 while (!(IS(bas, USR2, RDR)))
246 c = GETREG(bas, REG(URXD));
249 if (c & FLD(URXD, BRK)) {
258 * High-level UART interface.
260 struct imx_uart_softc {
261 struct uart_softc base;
264 static int imx_uart_bus_attach(struct uart_softc *);
265 static int imx_uart_bus_detach(struct uart_softc *);
266 static int imx_uart_bus_flush(struct uart_softc *, int);
267 static int imx_uart_bus_getsig(struct uart_softc *);
268 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
269 static int imx_uart_bus_ipend(struct uart_softc *);
270 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
271 static int imx_uart_bus_probe(struct uart_softc *);
272 static int imx_uart_bus_receive(struct uart_softc *);
273 static int imx_uart_bus_setsig(struct uart_softc *, int);
274 static int imx_uart_bus_transmit(struct uart_softc *);
275 static void imx_uart_bus_grab(struct uart_softc *);
276 static void imx_uart_bus_ungrab(struct uart_softc *);
278 static kobj_method_t imx_uart_methods[] = {
279 KOBJMETHOD(uart_attach, imx_uart_bus_attach),
280 KOBJMETHOD(uart_detach, imx_uart_bus_detach),
281 KOBJMETHOD(uart_flush, imx_uart_bus_flush),
282 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
283 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
284 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
285 KOBJMETHOD(uart_param, imx_uart_bus_param),
286 KOBJMETHOD(uart_probe, imx_uart_bus_probe),
287 KOBJMETHOD(uart_receive, imx_uart_bus_receive),
288 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
289 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
290 KOBJMETHOD(uart_grab, imx_uart_bus_grab),
291 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab),
295 static struct uart_class uart_imx_class = {
298 sizeof(struct imx_uart_softc),
299 .uc_ops = &uart_imx_uart_ops,
301 .uc_rclk = 24000000, /* TODO: get value from CCM */
305 static struct ofw_compat_data compat_data[] = {
306 {"fsl,imx6q-uart", (uintptr_t)&uart_imx_class},
307 {"fsl,imx53-uart", (uintptr_t)&uart_imx_class},
308 {"fsl,imx51-uart", (uintptr_t)&uart_imx_class},
309 {"fsl,imx31-uart", (uintptr_t)&uart_imx_class},
310 {"fsl,imx27-uart", (uintptr_t)&uart_imx_class},
311 {"fsl,imx25-uart", (uintptr_t)&uart_imx_class},
312 {"fsl,imx21-uart", (uintptr_t)&uart_imx_class},
313 {NULL, (uintptr_t)NULL},
315 UART_FDT_CLASS_AND_DEVICE(compat_data);
317 #define SIGCHG(c, i, s, d) \
319 i |= (i & s) ? s : s | d; \
321 i = (i & s) ? (i & ~s) | d : i; \
325 imx_uart_bus_attach(struct uart_softc *sc)
327 struct uart_bas *bas;
328 struct uart_devinfo *di;
331 if (sc->sc_sysdev != NULL) {
333 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
336 imx_uart_init(bas, 115200, 8, 1, 0);
339 (void)imx_uart_bus_getsig(sc);
341 /* Clear all pending interrupts. */
342 SETREG(bas, REG(USR1), 0xffff);
343 SETREG(bas, REG(USR2), 0xffff);
345 DIS(bas, UCR4, DREN);
346 ENA(bas, UCR1, RRDYEN);
347 DIS(bas, UCR1, IDEN);
348 DIS(bas, UCR3, RXDSEN);
349 ENA(bas, UCR2, ATEN);
350 DIS(bas, UCR1, TXMPTYEN);
351 DIS(bas, UCR1, TRDYEN);
352 DIS(bas, UCR4, TCEN);
353 DIS(bas, UCR4, OREN);
354 ENA(bas, UCR4, BKEN);
355 DIS(bas, UCR4, WKEN);
356 DIS(bas, UCR1, ADEN);
357 DIS(bas, UCR3, ACIEN);
358 DIS(bas, UCR2, ESCI);
359 DIS(bas, UCR4, ENIRI);
360 DIS(bas, UCR3, AIRINTEN);
361 DIS(bas, UCR3, AWAKEN);
362 DIS(bas, UCR3, FRAERREN);
363 DIS(bas, UCR3, PARERREN);
364 DIS(bas, UCR1, RTSDEN);
365 DIS(bas, UCR2, RTSEN);
366 DIS(bas, UCR3, DTREN);
369 DIS(bas, UCR3, DTRDEN);
370 ENA(bas, UCR2, IRTS);
371 ENA(bas, UCR3, RXDMUXSEL);
377 imx_uart_bus_detach(struct uart_softc *sc)
380 SETREG(&sc->sc_bas, REG(UCR4), 0);
386 imx_uart_bus_flush(struct uart_softc *sc, int what)
394 imx_uart_bus_getsig(struct uart_softc *sc)
396 uint32_t new, old, sig;
402 uart_lock(sc->sc_hwmtx);
403 bes = GETREG(&sc->sc_bas, REG(USR2));
404 uart_unlock(sc->sc_hwmtx);
405 /* XXX: chip can show delta */
406 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
407 new = sig & ~SER_MASK_DELTA;
408 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
414 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
416 struct uart_bas *bas;
421 uart_lock(sc->sc_hwmtx);
423 case UART_IOCTL_BREAK:
426 case UART_IOCTL_BAUD:
427 *(u_int*)data = imx_uart_getbaud(bas);
433 uart_unlock(sc->sc_hwmtx);
439 imx_uart_bus_ipend(struct uart_softc *sc)
441 struct uart_bas *bas;
444 uint32_t ucr1, ucr2, ucr4;
449 uart_lock(sc->sc_hwmtx);
451 /* Read pending interrupts */
452 usr1 = GETREG(bas, REG(USR1));
453 usr2 = GETREG(bas, REG(USR2));
455 SETREG(bas, REG(USR1), usr1);
456 SETREG(bas, REG(USR2), usr2);
458 ucr1 = GETREG(bas, REG(UCR1));
459 ucr2 = GETREG(bas, REG(UCR2));
460 ucr4 = GETREG(bas, REG(UCR4));
462 /* If we have reached tx low-water, we can tx some more now. */
463 if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) {
464 DIS(bas, UCR1, TRDYEN);
465 ipend |= SER_INT_TXIDLE;
469 * If we have reached the rx high-water, or if there are bytes in the rx
470 * fifo and no new data has arrived for 8 character periods (aging
471 * timer), we have input data to process.
473 if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) ||
474 ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) {
475 DIS(bas, UCR1, RRDYEN);
476 DIS(bas, UCR2, ATEN);
477 ipend |= SER_INT_RXREADY;
480 /* A break can come in at any time, it never gets disabled. */
481 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
482 ipend |= SER_INT_BREAK;
484 uart_unlock(sc->sc_hwmtx);
490 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
491 int stopbits, int parity)
494 uart_lock(sc->sc_hwmtx);
495 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
496 uart_unlock(sc->sc_hwmtx);
501 imx_uart_bus_probe(struct uart_softc *sc)
505 error = imx_uart_probe(&sc->sc_bas);
510 * On input we can read up to the full fifo size at once. On output, we
511 * want to write only as much as the programmed tx low water level,
512 * because that's all we can be certain we have room for in the fifo
513 * when we get a tx-ready interrupt.
515 sc->sc_rxfifosz = IMX_FIFOSZ;
516 sc->sc_txfifosz = IMX_TXFIFO_LEVEL;
518 device_set_desc(sc->sc_dev, "Freescale i.MX UART");
523 imx_uart_bus_receive(struct uart_softc *sc)
525 struct uart_bas *bas;
529 uart_lock(sc->sc_hwmtx);
532 * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL
533 * (the rx high-water level) is reached, but we set sc_rxfifosz to the
534 * full hardware fifo size, so we can safely process however much is
535 * there, not just the highwater size.
537 while (IS(bas, USR2, RDR)) {
538 if (uart_rx_full(sc)) {
539 /* No space left in input buffer */
540 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
543 xc = GETREG(bas, REG(URXD));
544 out = xc & 0x000000ff;
545 if (xc & FLD(URXD, FRMERR))
546 out |= UART_STAT_FRAMERR;
547 if (xc & FLD(URXD, PRERR))
548 out |= UART_STAT_PARERR;
549 if (xc & FLD(URXD, OVRRUN))
550 out |= UART_STAT_OVERRUN;
551 if (xc & FLD(URXD, BRK))
552 out |= UART_STAT_BREAK;
554 uart_rx_put(sc, out);
556 ENA(bas, UCR1, RRDYEN);
557 ENA(bas, UCR2, ATEN);
559 uart_unlock(sc->sc_hwmtx);
564 imx_uart_bus_setsig(struct uart_softc *sc, int sig)
571 imx_uart_bus_transmit(struct uart_softc *sc)
573 struct uart_bas *bas = &sc->sc_bas;
577 uart_lock(sc->sc_hwmtx);
580 * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes
581 * into the txbuf (because that's what sc_txfifosz is set to), and
582 * because we got the TRDY (low-water reached) interrupt we know at
583 * least that much space is available in the fifo.
585 for (i = 0; i < sc->sc_txdatasz; i++) {
586 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
589 ENA(bas, UCR1, TRDYEN);
591 uart_unlock(sc->sc_hwmtx);
597 imx_uart_bus_grab(struct uart_softc *sc)
599 struct uart_bas *bas = &sc->sc_bas;
602 uart_lock(sc->sc_hwmtx);
603 DIS(bas, UCR1, RRDYEN);
604 DIS(bas, UCR2, ATEN);
605 uart_unlock(sc->sc_hwmtx);
609 imx_uart_bus_ungrab(struct uart_softc *sc)
611 struct uart_bas *bas = &sc->sc_bas;
614 uart_lock(sc->sc_hwmtx);
615 ENA(bas, UCR1, RRDYEN);
616 ENA(bas, UCR2, ATEN);
617 uart_unlock(sc->sc_hwmtx);