2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
7 * This software was developed by SRI International and the University of
8 * Cambridge Computer Laboratory (Department of Computer Science and
9 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
10 * DARPA SSITH research programme.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <machine/bus.h>
45 #include <machine/sbi.h>
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #include <dev/uart/uart_cpu_fdt.h>
50 #include <dev/uart/uart_bus.h>
51 #include <dev/uart/uart_dev_lowrisc.h>
55 #define DEFAULT_BAUD_RATE 115200
58 * Low-level UART interface.
60 static int lowrisc_uart_probe(struct uart_bas *bas);
61 static void lowrisc_uart_init(struct uart_bas *bas, int, int, int, int);
62 static void lowrisc_uart_term(struct uart_bas *bas);
63 static void lowrisc_uart_putc(struct uart_bas *bas, int);
64 static int lowrisc_uart_rxready(struct uart_bas *bas);
65 static int lowrisc_uart_getc(struct uart_bas *bas, struct mtx *);
67 static struct uart_ops uart_lowrisc_uart_ops = {
68 .probe = lowrisc_uart_probe,
69 .init = lowrisc_uart_init,
70 .term = lowrisc_uart_term,
71 .putc = lowrisc_uart_putc,
72 .rxready = lowrisc_uart_rxready,
73 .getc = lowrisc_uart_getc,
77 lowrisc_uart_probe(struct uart_bas *bas)
84 lowrisc_uart_getbaud(struct uart_bas *bas)
87 return (DEFAULT_BAUD_RATE);
91 lowrisc_uart_init(struct uart_bas *bas, int baudrate, int databits,
92 int stopbits, int parity)
99 lowrisc_uart_term(struct uart_bas *bas)
106 lowrisc_uart_putc(struct uart_bas *bas, int c)
109 while (GETREG(bas, UART_DR) & DR_TX_FIFO_FULL)
112 SETREG(bas, UART_DR, c);
116 lowrisc_uart_rxready(struct uart_bas *bas)
119 if (GETREG(bas, UART_DR) & DR_RX_FIFO_EMPTY)
126 lowrisc_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
131 SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);
132 reg = GETREG(bas, UART_DR);
139 * High-level UART interface.
141 struct lowrisc_uart_softc {
142 struct uart_softc base;
145 static int lowrisc_uart_bus_attach(struct uart_softc *);
146 static int lowrisc_uart_bus_detach(struct uart_softc *);
147 static int lowrisc_uart_bus_flush(struct uart_softc *, int);
148 static int lowrisc_uart_bus_getsig(struct uart_softc *);
149 static int lowrisc_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
150 static int lowrisc_uart_bus_ipend(struct uart_softc *);
151 static int lowrisc_uart_bus_param(struct uart_softc *, int, int, int, int);
152 static int lowrisc_uart_bus_probe(struct uart_softc *);
153 static int lowrisc_uart_bus_receive(struct uart_softc *);
154 static int lowrisc_uart_bus_setsig(struct uart_softc *, int);
155 static int lowrisc_uart_bus_transmit(struct uart_softc *);
156 static void lowrisc_uart_bus_grab(struct uart_softc *);
157 static void lowrisc_uart_bus_ungrab(struct uart_softc *);
159 static kobj_method_t lowrisc_uart_methods[] = {
160 KOBJMETHOD(uart_attach, lowrisc_uart_bus_attach),
161 KOBJMETHOD(uart_detach, lowrisc_uart_bus_detach),
162 KOBJMETHOD(uart_flush, lowrisc_uart_bus_flush),
163 KOBJMETHOD(uart_getsig, lowrisc_uart_bus_getsig),
164 KOBJMETHOD(uart_ioctl, lowrisc_uart_bus_ioctl),
165 KOBJMETHOD(uart_ipend, lowrisc_uart_bus_ipend),
166 KOBJMETHOD(uart_param, lowrisc_uart_bus_param),
167 KOBJMETHOD(uart_probe, lowrisc_uart_bus_probe),
168 KOBJMETHOD(uart_receive, lowrisc_uart_bus_receive),
169 KOBJMETHOD(uart_setsig, lowrisc_uart_bus_setsig),
170 KOBJMETHOD(uart_transmit, lowrisc_uart_bus_transmit),
171 KOBJMETHOD(uart_grab, lowrisc_uart_bus_grab),
172 KOBJMETHOD(uart_ungrab, lowrisc_uart_bus_ungrab),
176 static struct uart_class uart_lowrisc_class = {
178 lowrisc_uart_methods,
179 sizeof(struct lowrisc_uart_softc),
180 .uc_ops = &uart_lowrisc_uart_ops,
182 .uc_rclk = 12500000, /* TODO: get value from clock manager */
186 static struct ofw_compat_data compat_data[] = {
187 {"lowrisc-fake", (uintptr_t)&uart_lowrisc_class},
188 {NULL, (uintptr_t)NULL},
190 UART_FDT_CLASS_AND_DEVICE(compat_data);
193 lowrisc_uart_bus_attach(struct uart_softc *sc)
195 struct uart_bas *bas;
196 struct uart_devinfo *di;
199 if (sc->sc_sysdev != NULL) {
201 lowrisc_uart_init(bas, di->baudrate, di->databits, di->stopbits,
204 lowrisc_uart_init(bas, DEFAULT_BAUD_RATE, 8, 1, 0);
206 (void)lowrisc_uart_bus_getsig(sc);
208 /* TODO: clear all pending interrupts. */
214 lowrisc_uart_bus_detach(struct uart_softc *sc)
223 lowrisc_uart_bus_flush(struct uart_softc *sc, int what)
232 lowrisc_uart_bus_getsig(struct uart_softc *sc)
241 lowrisc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
243 struct uart_bas *bas;
248 uart_lock(sc->sc_hwmtx);
250 case UART_IOCTL_BREAK:
253 case UART_IOCTL_BAUD:
254 *(u_int*)data = lowrisc_uart_getbaud(bas);
260 uart_unlock(sc->sc_hwmtx);
266 lowrisc_uart_bus_ipend(struct uart_softc *sc)
268 struct uart_bas *bas;
275 uart_lock(sc->sc_hwmtx);
276 if ((GETREG(bas, UART_DR) & DR_RX_FIFO_EMPTY) == 0)
277 ipend |= SER_INT_RXREADY;
278 SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);
279 uart_unlock(sc->sc_hwmtx);
285 lowrisc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
286 int stopbits, int parity)
289 uart_lock(sc->sc_hwmtx);
290 lowrisc_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
291 uart_unlock(sc->sc_hwmtx);
297 lowrisc_uart_bus_probe(struct uart_softc *sc)
301 error = lowrisc_uart_probe(&sc->sc_bas);
306 * On input we can read up to the full fifo size at once. On output, we
307 * want to write only as much as the programmed tx low water level,
308 * because that's all we can be certain we have room for in the fifo
309 * when we get a tx-ready interrupt.
311 sc->sc_rxfifosz = 2048;
312 sc->sc_txfifosz = 2048;
314 device_set_desc(sc->sc_dev, "lowRISC UART");
320 lowrisc_uart_bus_receive(struct uart_softc *sc)
322 struct uart_bas *bas;
327 uart_lock(sc->sc_hwmtx);
330 if (uart_rx_full(sc)) {
331 /* No space left in the input buffer */
332 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
335 reg = GETREG(bas, UART_DR);
336 SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);
337 uart_rx_put(sc, reg & 0xff);
338 } while ((reg & DR_RX_FIFO_EMPTY) == 0);
340 uart_unlock(sc->sc_hwmtx);
346 lowrisc_uart_bus_setsig(struct uart_softc *sc, int sig)
353 lowrisc_uart_bus_transmit(struct uart_softc *sc)
355 struct uart_bas *bas;
360 uart_lock(sc->sc_hwmtx);
361 for (i = 0; i < sc->sc_txdatasz; i++) {
362 while (GETREG(bas, UART_DR) & DR_TX_FIFO_FULL)
364 SETREG(bas, UART_DR, sc->sc_txbuf[i] & 0xff);
366 uart_unlock(sc->sc_hwmtx);
372 lowrisc_uart_bus_grab(struct uart_softc *sc)
374 struct uart_bas *bas;
378 uart_lock(sc->sc_hwmtx);
380 uart_unlock(sc->sc_hwmtx);
384 lowrisc_uart_bus_ungrab(struct uart_softc *sc)
386 struct uart_bas *bas;
390 uart_lock(sc->sc_hwmtx);
392 uart_unlock(sc->sc_hwmtx);