2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_cpu_fdt.h>
39 #include <dev/uart/uart_bus.h>
41 #include <dev/ic/ns16550.h>
42 #include <arm/lpc/lpcreg.h>
46 #define DEFAULT_RCLK (13 * 1000 * 1000)
48 static bus_space_handle_t bsh_clkpwr;
50 #define lpc_ns8250_get_clkreg(_bas, _reg) \
51 bus_space_read_4((_bas)->bst, bsh_clkpwr, (_reg))
52 #define lpc_ns8250_set_clkreg(_bas, _reg, _val) \
53 bus_space_write_4((_bas)->bst, bsh_clkpwr, (_reg), (_val))
56 * Clear pending interrupts. THRE is cleared by reading IIR. Data
57 * that may have been received gets lost here.
60 lpc_ns8250_clrint(struct uart_bas *bas)
64 iir = uart_getreg(bas, REG_IIR);
65 while ((iir & IIR_NOPEND) == 0) {
68 lsr = uart_getreg(bas, REG_LSR);
69 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
70 (void)uart_getreg(bas, REG_DATA);
71 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
72 (void)uart_getreg(bas, REG_DATA);
73 else if (iir == IIR_MLSC)
74 (void)uart_getreg(bas, REG_MSR);
76 iir = uart_getreg(bas, REG_IIR);
81 lpc_ns8250_delay(struct uart_bas *bas)
86 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
88 x = (uclk >> 8) & 0xff;
91 return (16000000 / (bas->rclk * x / y));
95 lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
140 lpc_ns8250_drain(struct uart_bas *bas, int what)
144 delay = lpc_ns8250_delay(bas);
146 if (what & UART_DRAIN_TRANSMITTER) {
148 * Pick an arbitrary high limit to avoid getting stuck in
149 * an infinite loop when the hardware is broken. Make the
150 * limit high enough to handle large FIFOs.
153 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
156 /* printf("lpc_ns8250: transmitter appears stuck... "); */
161 if (what & UART_DRAIN_RECEIVER) {
163 * Pick an arbitrary high limit to avoid getting stuck in
164 * an infinite loop when the hardware is broken. Make the
165 * limit high enough to handle large FIFOs and integrated
166 * UARTs. The HP rx2600 for example has 3 UARTs on the
167 * management board that tend to get a lot of data send
168 * to it when the UART is first activated.
171 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
172 (void)uart_getreg(bas, REG_DATA);
177 /* printf("lpc_ns8250: receiver appears broken... "); */
186 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
187 * drained. WARNING: this function clobbers the FIFO setting!
190 lpc_ns8250_flush(struct uart_bas *bas, int what)
195 if (what & UART_FLUSH_TRANSMITTER)
197 if (what & UART_FLUSH_RECEIVER)
199 uart_setreg(bas, REG_FCR, fcr);
204 lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
213 else if (databits == 7)
215 else if (databits == 6)
225 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
227 uart_setreg(bas, REG_DLL, 0x00);
228 uart_setreg(bas, REG_DLH, 0x00);
231 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
232 lpc_ns8250_set_clkreg(bas,
233 LPC_CLKPWR_UART_U5CLK,
234 LPC_CLKPWR_UART_UCLK_X(xdiv) |
235 LPC_CLKPWR_UART_UCLK_Y(ydiv));
238 /* Set LCR and clear DLAB. */
239 uart_setreg(bas, REG_LCR, lcr);
245 * Low-level UART interface.
247 static int lpc_ns8250_probe(struct uart_bas *bas);
248 static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
249 static void lpc_ns8250_term(struct uart_bas *bas);
250 static void lpc_ns8250_putc(struct uart_bas *bas, int);
251 static int lpc_ns8250_rxready(struct uart_bas *bas);
252 static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
254 static struct uart_ops uart_lpc_ns8250_ops = {
255 .probe = lpc_ns8250_probe,
256 .init = lpc_ns8250_init,
257 .term = lpc_ns8250_term,
258 .putc = lpc_ns8250_putc,
259 .rxready = lpc_ns8250_rxready,
260 .getc = lpc_ns8250_getc,
264 lpc_ns8250_probe(struct uart_bas *bas)
269 /* Check known 0 bits that don't depend on DLAB. */
270 val = uart_getreg(bas, REG_IIR);
274 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
275 * chip, but otherwise doesn't seem to have a function. In
276 * other words, uart(4) works regardless. Ignore that bit so
277 * the probe succeeds.
279 val = uart_getreg(bas, REG_MCR);
287 lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
293 /* Enable UART clock */
294 bus_space_map(bas->bst, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0,
296 clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE);
297 lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode |
298 LPC_UART_CLKMODE_UART5(1));
301 /* Work around H/W bug */
302 uart_setreg(bas, REG_DATA, 0x00);
305 bas->rclk = DEFAULT_RCLK;
306 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
308 /* Disable all interrupt sources. */
310 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
311 * UARTs split the receive time-out interrupt bit out separately as
312 * 0x10. This gets handled by ier_mask and ier_rxbits below.
314 ier = uart_getreg(bas, REG_IER) & 0xe0;
315 uart_setreg(bas, REG_IER, ier);
318 /* Disable the FIFO (if present). */
319 uart_setreg(bas, REG_FCR, 0);
323 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
326 lpc_ns8250_clrint(bas);
330 lpc_ns8250_term(struct uart_bas *bas)
333 /* Clear RTS & DTR. */
334 uart_setreg(bas, REG_MCR, MCR_IE);
339 lpc_ns8250_putc(struct uart_bas *bas, int c)
344 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
346 uart_setreg(bas, REG_DATA, c);
349 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
354 lpc_ns8250_rxready(struct uart_bas *bas)
357 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
361 lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
373 c = uart_getreg(bas, REG_DATA);
381 * High-level UART interface.
383 struct lpc_ns8250_softc {
384 struct uart_softc base;
393 static int lpc_ns8250_bus_attach(struct uart_softc *);
394 static int lpc_ns8250_bus_detach(struct uart_softc *);
395 static int lpc_ns8250_bus_flush(struct uart_softc *, int);
396 static int lpc_ns8250_bus_getsig(struct uart_softc *);
397 static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
398 static int lpc_ns8250_bus_ipend(struct uart_softc *);
399 static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
400 static int lpc_ns8250_bus_probe(struct uart_softc *);
401 static int lpc_ns8250_bus_receive(struct uart_softc *);
402 static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
403 static int lpc_ns8250_bus_transmit(struct uart_softc *);
404 static void lpc_ns8250_bus_grab(struct uart_softc *);
405 static void lpc_ns8250_bus_ungrab(struct uart_softc *);
407 static kobj_method_t lpc_ns8250_methods[] = {
408 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
409 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
410 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
411 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
412 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
413 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
414 KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
415 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
416 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
417 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
418 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
419 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab),
420 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab),
424 static struct uart_class uart_lpc_class = {
427 sizeof(struct lpc_ns8250_softc),
428 .uc_ops = &uart_lpc_ns8250_ops,
430 .uc_rclk = DEFAULT_RCLK,
434 static struct ofw_compat_data compat_data[] = {
435 {"lpc,uart", (uintptr_t)&uart_lpc_class},
436 {NULL, (uintptr_t)NULL},
438 UART_FDT_CLASS_AND_DEVICE(compat_data);
440 #define SIGCHG(c, i, s, d) \
442 i |= (i & s) ? s : s | d; \
444 i = (i & s) ? (i & ~s) | d : i; \
448 lpc_ns8250_bus_attach(struct uart_softc *sc)
450 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
451 struct uart_bas *bas;
456 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
457 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
458 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
460 if (UART_FLAGS_FCR_RX_LOW(ivar))
461 lpc_ns8250->fcr |= FCR_RX_LOW;
462 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
463 lpc_ns8250->fcr |= FCR_RX_MEDL;
464 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
465 lpc_ns8250->fcr |= FCR_RX_HIGH;
467 lpc_ns8250->fcr |= FCR_RX_MEDH;
469 lpc_ns8250->fcr |= FCR_RX_HIGH;
473 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
475 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
477 /* Get IER RX interrupt bits */
478 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
479 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
481 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
483 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
485 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
487 if (lpc_ns8250->mcr & MCR_DTR)
488 sc->sc_hwsig |= SER_DTR;
489 if (lpc_ns8250->mcr & MCR_RTS)
490 sc->sc_hwsig |= SER_RTS;
491 lpc_ns8250_bus_getsig(sc);
493 lpc_ns8250_clrint(bas);
494 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
495 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
496 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
503 lpc_ns8250_bus_detach(struct uart_softc *sc)
505 struct lpc_ns8250_softc *lpc_ns8250;
506 struct uart_bas *bas;
509 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
511 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
512 uart_setreg(bas, REG_IER, ier);
514 lpc_ns8250_clrint(bas);
519 lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
521 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
522 struct uart_bas *bas;
526 uart_lock(sc->sc_hwmtx);
527 if (sc->sc_rxfifosz > 1) {
528 lpc_ns8250_flush(bas, what);
529 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
533 error = lpc_ns8250_drain(bas, what);
534 uart_unlock(sc->sc_hwmtx);
539 lpc_ns8250_bus_getsig(struct uart_softc *sc)
541 uint32_t new, old, sig;
547 uart_lock(sc->sc_hwmtx);
548 msr = uart_getreg(&sc->sc_bas, REG_MSR);
549 uart_unlock(sc->sc_hwmtx);
550 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
551 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
552 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
553 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
554 new = sig & ~SER_MASK_DELTA;
555 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
560 lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
562 struct uart_bas *bas;
563 int baudrate, divisor, error;
568 uart_lock(sc->sc_hwmtx);
570 case UART_IOCTL_BREAK:
571 lcr = uart_getreg(bas, REG_LCR);
576 uart_setreg(bas, REG_LCR, lcr);
579 case UART_IOCTL_IFLOW:
580 lcr = uart_getreg(bas, REG_LCR);
582 uart_setreg(bas, REG_LCR, 0xbf);
584 efr = uart_getreg(bas, REG_EFR);
589 uart_setreg(bas, REG_EFR, efr);
591 uart_setreg(bas, REG_LCR, lcr);
594 case UART_IOCTL_OFLOW:
595 lcr = uart_getreg(bas, REG_LCR);
597 uart_setreg(bas, REG_LCR, 0xbf);
599 efr = uart_getreg(bas, REG_EFR);
604 uart_setreg(bas, REG_EFR, efr);
606 uart_setreg(bas, REG_LCR, lcr);
609 case UART_IOCTL_BAUD:
610 lcr = uart_getreg(bas, REG_LCR);
611 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
613 divisor = uart_getreg(bas, REG_DLL) |
614 (uart_getreg(bas, REG_DLH) << 8);
616 uart_setreg(bas, REG_LCR, lcr);
618 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
620 *(int*)data = baudrate;
628 uart_unlock(sc->sc_hwmtx);
633 lpc_ns8250_bus_ipend(struct uart_softc *sc)
635 struct uart_bas *bas;
636 struct lpc_ns8250_softc *lpc_ns8250;
640 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
642 uart_lock(sc->sc_hwmtx);
643 iir = uart_getreg(bas, REG_IIR);
644 if (iir & IIR_NOPEND) {
645 uart_unlock(sc->sc_hwmtx);
649 if (iir & IIR_RXRDY) {
650 lsr = uart_getreg(bas, REG_LSR);
652 ipend |= SER_INT_OVERRUN;
654 ipend |= SER_INT_BREAK;
656 ipend |= SER_INT_RXREADY;
658 if (iir & IIR_TXRDY) {
659 ipend |= SER_INT_TXIDLE;
660 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
663 ipend |= SER_INT_SIGCHG;
666 lpc_ns8250_clrint(bas);
667 uart_unlock(sc->sc_hwmtx);
672 lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
673 int stopbits, int parity)
675 struct uart_bas *bas;
679 uart_lock(sc->sc_hwmtx);
680 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
681 uart_unlock(sc->sc_hwmtx);
686 lpc_ns8250_bus_probe(struct uart_softc *sc)
688 struct lpc_ns8250_softc *lpc_ns8250;
689 struct uart_bas *bas;
690 int count, delay, error, limit;
691 uint8_t lsr, mcr, ier;
693 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
696 error = lpc_ns8250_probe(bas);
701 if (sc->sc_sysdev == NULL) {
702 /* By using lpc_ns8250_init() we also set DTR and RTS. */
703 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
705 mcr |= MCR_DTR | MCR_RTS;
707 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
712 * Set loopback mode. This avoids having garbage on the wire and
713 * also allows us send and receive data. We set DTR and RTS to
714 * avoid the possibility that automatic flow-control prevents
715 * any data from being sent.
717 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
721 * Enable FIFOs. And check that the UART has them. If not, we're
722 * done. Since this is the first time we enable the FIFOs, we reset
725 uart_setreg(bas, REG_FCR, FCR_ENABLE);
727 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
729 * NS16450 or INS8250. We don't bother to differentiate
730 * between them. They're too old to be interesting.
732 uart_setreg(bas, REG_MCR, mcr);
734 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
735 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
739 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
743 delay = lpc_ns8250_delay(bas);
745 /* We have FIFOs. Drain the transmitter and receiver. */
746 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
748 uart_setreg(bas, REG_MCR, mcr);
749 uart_setreg(bas, REG_FCR, 0);
755 * We should have a sufficiently clean "pipe" to determine the
756 * size of the FIFOs. We send as much characters as is reasonable
757 * and wait for the overflow bit in the LSR register to be
758 * asserted, counting the characters as we send them. Based on
759 * that count we know the FIFO size.
762 uart_setreg(bas, REG_DATA, 0);
769 * LSR bits are cleared upon read, so we must accumulate
770 * them to be able to test LSR_OE below.
772 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
776 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
777 uart_setreg(bas, REG_IER, ier);
778 uart_setreg(bas, REG_MCR, mcr);
779 uart_setreg(bas, REG_FCR, 0);
784 } while ((lsr & LSR_OE) == 0 && count < 130);
787 uart_setreg(bas, REG_MCR, mcr);
790 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
793 sc->sc_rxfifosz = 64;
794 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
797 * Force the Tx FIFO size to 16 bytes for now. We don't program the
798 * Tx trigger. Also, we assume that all data has been sent when the
801 sc->sc_txfifosz = 16;
805 * XXX there are some issues related to hardware flow control and
806 * it's likely that uart(4) is the cause. This basically needs more
807 * investigation, but we avoid using for hardware flow control
810 /* 16650s or higher have automatic flow control. */
811 if (sc->sc_rxfifosz > 16) {
820 lpc_ns8250_bus_receive(struct uart_softc *sc)
822 struct uart_bas *bas;
827 uart_lock(sc->sc_hwmtx);
828 lsr = uart_getreg(bas, REG_LSR);
829 while (lsr & LSR_RXRDY) {
830 if (uart_rx_full(sc)) {
831 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
834 xc = uart_getreg(bas, REG_DATA);
836 xc |= UART_STAT_FRAMERR;
838 xc |= UART_STAT_PARERR;
840 lsr = uart_getreg(bas, REG_LSR);
842 /* Discard everything left in the Rx FIFO. */
843 while (lsr & LSR_RXRDY) {
844 (void)uart_getreg(bas, REG_DATA);
846 lsr = uart_getreg(bas, REG_LSR);
848 uart_unlock(sc->sc_hwmtx);
853 lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
855 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
856 struct uart_bas *bas;
863 if (sig & SER_DDTR) {
864 SIGCHG(sig & SER_DTR, new, SER_DTR,
867 if (sig & SER_DRTS) {
868 SIGCHG(sig & SER_RTS, new, SER_RTS,
871 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
872 uart_lock(sc->sc_hwmtx);
873 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
875 lpc_ns8250->mcr |= MCR_DTR;
877 lpc_ns8250->mcr |= MCR_RTS;
878 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
880 uart_unlock(sc->sc_hwmtx);
885 lpc_ns8250_bus_transmit(struct uart_softc *sc)
887 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
888 struct uart_bas *bas;
892 uart_lock(sc->sc_hwmtx);
893 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
895 for (i = 0; i < sc->sc_txdatasz; i++) {
896 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
899 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
902 uart_unlock(sc->sc_hwmtx);
907 lpc_ns8250_bus_grab(struct uart_softc *sc)
909 struct uart_bas *bas = &sc->sc_bas;
912 * turn off all interrupts to enter polling mode. Leave the
913 * saved mask alone. We'll restore whatever it was in ungrab.
914 * All pending interrupt signals are reset when IER is set to 0.
916 uart_lock(sc->sc_hwmtx);
917 uart_setreg(bas, REG_IER, 0);
919 uart_unlock(sc->sc_hwmtx);
923 lpc_ns8250_bus_ungrab(struct uart_softc *sc)
925 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
926 struct uart_bas *bas = &sc->sc_bas;
929 * Restore previous interrupt mask
931 uart_lock(sc->sc_hwmtx);
932 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
934 uart_unlock(sc->sc_hwmtx);