2 * Copyright (c) 2018 Diane Bruce
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Based on uart_dev_pl011.c
28 * Copyright (c) 2012 Semihalf.
29 * All rights reserved.
32 * The mini Uart has the following features:
33 * - 7 or 8 bit operation.
34 * - 1 start and 1 stop bit.
37 * - 8 symbols deep FIFOs for receive and transmit.
38 * - SW controlled RTS, SW readable CTS.
39 * - Auto flow control with programmable FIFO level.
40 * - 16550 like registers.
41 * - Baudrate derived from system clock.
42 * This is a mini UART and it does NOT have the following capabilities:
44 * - Framing errors detection.
46 * - Receive Time-out interrupt
47 * - DCD, DSR, DTR or RI signals.
48 * The implemented UART is not a 16650 compatible UART However as far
49 * as possible the first 8 control and status registers are laid out
50 * like a 16550 UART. All 16550 register bits which are not supported can
51 * be written but will be ignored and read back as 0. All control bits
52 * for simple UART receive/transmit operations are available.
56 #include "opt_platform.h"
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/kernel.h>
66 #include <machine/bus.h>
67 #include <machine/machdep.h>
68 #include <machine/pcpu.h>
70 #include <dev/uart/uart.h>
71 #include <dev/uart/uart_cpu.h>
73 #include <dev/uart/uart_cpu_fdt.h>
74 #include <dev/ofw/ofw_bus.h>
76 #include <dev/uart/uart_bus.h>
79 /* BCM2835 Micro UART registers and masks*/
80 #define AUX_MU_IO_REG 0x00 /* I/O register */
83 * According to errata bits 1 and 2 are swapped,
84 * Also bits 2 and 3 are required to enable interrupts.
86 #define AUX_MU_IER_REG 0x01
87 #define IER_RXENABLE (1)
88 #define IER_TXENABLE (1<<1)
89 #define IER_REQUIRED (3<<2)
90 #define IER_MASK_ALL (IER_TXENABLE|IER_RXENABLE)
92 #define AUX_MU_IIR_REG 0x02
94 #define IIR_TXREADY (1<<1)
95 #define IIR_RXREADY (1<<2)
96 #define IIR_CLEAR (3<<1)
98 #define AUX_MU_LCR_REG 0x03
100 #define LCR_WLEN8 (3)
102 #define AUX_MU_MCR_REG 0x04
103 #define AUX_MCR_RTS (1<<1)
105 #define AUX_MU_LSR_REG 0x05
106 #define LSR_RXREADY (1)
107 #define LSR_OVRRUN (1<<1)
108 #define LSR_TXEMPTY (1<<5)
109 #define LSR_TXIDLE (1<<6)
111 #define AUX_MU_MSR_REG 0x06
112 #define MSR_CTS (1<<5)
114 #define AUX_MU_SCRATCH_REG 0x07
116 #define AUX_MU_CNTL_REG 0x08
117 #define CNTL_RXENAB (1)
118 #define CNTL_TXENAB (1<<1)
120 #define AUX_MU_STAT_REG 0x09
121 #define STAT_TX_SA (1<<1)
122 #define STAT_RX_SA (1)
124 #define AUX_MU_BAUD_REG 0x0a
127 * FIXME: actual register size is SoC-dependent, we need to handle it
129 #define __uart_getreg(bas, reg) \
130 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
131 #define __uart_setreg(bas, reg, value) \
132 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
135 * Low-level UART interface.
137 static int uart_mu_probe(struct uart_bas *bas);
138 static void uart_mu_init(struct uart_bas *bas, int, int, int, int);
139 static void uart_mu_term(struct uart_bas *bas);
140 static void uart_mu_putc(struct uart_bas *bas, int);
141 static int uart_mu_rxready(struct uart_bas *bas);
142 static int uart_mu_getc(struct uart_bas *bas, struct mtx *);
144 static struct uart_ops uart_mu_ops = {
145 .probe = uart_mu_probe,
146 .init = uart_mu_init,
147 .term = uart_mu_term,
148 .putc = uart_mu_putc,
149 .rxready = uart_mu_rxready,
150 .getc = uart_mu_getc,
154 uart_mu_probe(struct uart_bas *bas)
161 * According to the docs, the cpu clock is locked to 250Mhz when
162 * the micro-uart is used
164 #define CPU_CLOCK 250000000
167 uart_mu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
174 * Zero all settings to make sure
175 * UART is disabled and not configured
178 __uart_setreg(bas, AUX_MU_CNTL_REG, line);
180 /* As I know UART is disabled I can setup the line */
192 __uart_setreg(bas, AUX_MU_LCR_REG, line);
194 /* See 2.2.1 BCM2835-ARM-Peripherals baudrate */
196 baud = CPU_CLOCK / (8 * baudrate);
198 * baud = cpu_clock() / (8 * baudrate);
200 __uart_setreg(bas, AUX_MU_BAUD_REG, ((uint32_t)(baud & 0xFFFF)));
204 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
208 uart_mu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
212 /* Mask all interrupts */
213 __uart_setreg(bas, AUX_MU_IER_REG, 0);
214 uart_mu_param(bas, baudrate, databits, stopbits, parity);
218 uart_mu_term(struct uart_bas *bas)
223 uart_mu_putc(struct uart_bas *bas, int c)
226 /* Wait when TX FIFO full. Push character otherwise. */
227 while ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXEMPTY) == 0)
229 __uart_setreg(bas, AUX_MU_IO_REG, c & 0xff);
233 uart_mu_rxready(struct uart_bas *bas)
236 return ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_RXREADY) != 0);
240 uart_mu_getc(struct uart_bas *bas, struct mtx *hwmtx)
244 while(!uart_mu_rxready(bas))
246 c = __uart_getreg(bas, AUX_MU_IO_REG) & 0xff;
251 * High-level UART interface.
253 struct uart_mu_softc {
254 struct uart_softc bas;
255 uint16_t aux_ier; /* Interrupt mask */
258 static int uart_mu_bus_attach(struct uart_softc *);
259 static int uart_mu_bus_detach(struct uart_softc *);
260 static int uart_mu_bus_flush(struct uart_softc *, int);
261 static int uart_mu_bus_getsig(struct uart_softc *);
262 static int uart_mu_bus_ioctl(struct uart_softc *, int, intptr_t);
263 static int uart_mu_bus_ipend(struct uart_softc *);
264 static int uart_mu_bus_param(struct uart_softc *, int, int, int, int);
265 static int uart_mu_bus_probe(struct uart_softc *);
266 static int uart_mu_bus_receive(struct uart_softc *);
267 static int uart_mu_bus_setsig(struct uart_softc *, int);
268 static int uart_mu_bus_transmit(struct uart_softc *);
269 static void uart_mu_bus_grab(struct uart_softc *);
270 static void uart_mu_bus_ungrab(struct uart_softc *);
272 static kobj_method_t uart_mu_methods[] = {
273 KOBJMETHOD(uart_attach, uart_mu_bus_attach),
274 KOBJMETHOD(uart_detach, uart_mu_bus_detach),
275 KOBJMETHOD(uart_flush, uart_mu_bus_flush),
276 KOBJMETHOD(uart_getsig, uart_mu_bus_getsig),
277 KOBJMETHOD(uart_ioctl, uart_mu_bus_ioctl),
278 KOBJMETHOD(uart_ipend, uart_mu_bus_ipend),
279 KOBJMETHOD(uart_param, uart_mu_bus_param),
280 KOBJMETHOD(uart_probe, uart_mu_bus_probe),
281 KOBJMETHOD(uart_receive, uart_mu_bus_receive),
282 KOBJMETHOD(uart_setsig, uart_mu_bus_setsig),
283 KOBJMETHOD(uart_transmit, uart_mu_bus_transmit),
284 KOBJMETHOD(uart_grab, uart_mu_bus_grab),
285 KOBJMETHOD(uart_ungrab, uart_mu_bus_ungrab),
290 static struct uart_class uart_mu_class = {
293 sizeof(struct uart_mu_softc),
294 .uc_ops = &uart_mu_ops,
301 static struct ofw_compat_data fdt_compat_data[] = {
302 {"brcm,bcm2835-aux-uart" , (uintptr_t)&uart_mu_class},
303 {NULL, (uintptr_t)NULL},
305 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data);
309 uart_mu_bus_attach(struct uart_softc *sc)
311 struct uart_mu_softc *psc;
312 struct uart_bas *bas;
314 psc = (struct uart_mu_softc *)sc;
316 /* Clear interrupts */
317 __uart_setreg(bas, AUX_MU_IIR_REG, IIR_CLEAR);
318 /* Enable interrupts */
319 psc->aux_ier = (IER_RXENABLE|IER_TXENABLE|IER_REQUIRED);
320 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
327 uart_mu_bus_detach(struct uart_softc *sc)
334 uart_mu_bus_flush(struct uart_softc *sc, int what)
341 uart_mu_bus_getsig(struct uart_softc *sc)
348 uart_mu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
350 struct uart_bas *bas;
355 uart_lock(sc->sc_hwmtx);
357 case UART_IOCTL_BREAK:
359 case UART_IOCTL_BAUD:
360 *(int*)data = 115200;
366 uart_unlock(sc->sc_hwmtx);
372 uart_mu_bus_ipend(struct uart_softc *sc)
374 struct uart_mu_softc *psc;
375 struct uart_bas *bas;
379 psc = (struct uart_mu_softc *)sc;
382 uart_lock(sc->sc_hwmtx);
383 ints = __uart_getreg(bas, AUX_MU_IIR_REG);
387 * According to docs only one of IIR_RXREADY
388 * or IIR_TXREADY are valid eg. Only one or the other.
390 if (ints & IIR_RXREADY) {
391 ipend |= SER_INT_RXREADY;
392 } else if (ints & IIR_TXREADY) {
393 if (__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXIDLE) {
395 ipend |= SER_INT_TXIDLE;
397 /* Disable TX interrupt */
398 __uart_setreg(bas, AUX_MU_IER_REG,
399 psc->aux_ier & ~IER_TXENABLE);
403 uart_unlock(sc->sc_hwmtx);
409 uart_mu_bus_param(struct uart_softc *sc, int baudrate, int databits,
410 int stopbits, int parity)
413 uart_lock(sc->sc_hwmtx);
414 uart_mu_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
415 uart_unlock(sc->sc_hwmtx);
421 uart_mu_bus_probe(struct uart_softc *sc)
424 /* MU always has 8 byte deep fifo */
427 device_set_desc(sc->sc_dev, "BCM2835 Mini-UART");
433 uart_mu_bus_receive(struct uart_softc *sc)
435 struct uart_mu_softc *psc;
436 struct uart_bas *bas;
441 uart_lock(sc->sc_hwmtx);
442 psc = (struct uart_mu_softc *)sc;
444 lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
445 while (lsr & LSR_RXREADY) {
446 xc = __uart_getreg(bas, AUX_MU_IO_REG);
448 if (uart_rx_full(sc)) {
449 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
453 lsr = __uart_getreg(bas, AUX_MU_LSR_REG);
455 uart_unlock(sc->sc_hwmtx);
461 uart_mu_bus_setsig(struct uart_softc *sc, int sig)
468 uart_mu_bus_transmit(struct uart_softc *sc)
470 struct uart_mu_softc *psc;
471 struct uart_bas *bas;
474 psc = (struct uart_mu_softc *)sc;
476 uart_lock(sc->sc_hwmtx);
478 for (i = 0; i < sc->sc_txdatasz; i++) {
479 __uart_setreg(bas, AUX_MU_IO_REG, sc->sc_txbuf[i] & 0xff);
483 /* Mark busy and enable TX interrupt */
485 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
487 uart_unlock(sc->sc_hwmtx);
493 uart_mu_bus_grab(struct uart_softc *sc)
495 struct uart_mu_softc *psc;
496 struct uart_bas *bas;
498 psc = (struct uart_mu_softc *)sc;
501 /* Disable interrupts on switch to polling */
502 uart_lock(sc->sc_hwmtx);
503 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier &~IER_MASK_ALL);
504 uart_unlock(sc->sc_hwmtx);
508 uart_mu_bus_ungrab(struct uart_softc *sc)
510 struct uart_mu_softc *psc;
511 struct uart_bas *bas;
513 psc = (struct uart_mu_softc *)sc;
516 /* Switch to using interrupts while not grabbed */
517 uart_lock(sc->sc_hwmtx);
518 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB);
519 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier);
520 uart_unlock(sc->sc_hwmtx);