2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include "opt_platform.h"
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/sysctl.h>
42 #include <machine/bus.h>
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/uart/uart.h>
51 #include <dev/uart/uart_cpu.h>
53 #include <dev/uart/uart_cpu_fdt.h>
55 #include <dev/uart/uart_bus.h>
56 #include <dev/uart/uart_dev_ns8250.h>
57 #include <dev/uart/uart_ppstypes.h>
59 #include <dev/uart/uart_cpu_acpi.h>
62 #include <dev/ic/ns16550.h>
66 #define DEFAULT_RCLK 1843200
69 * Set the default baudrate tolerance to 3.0%.
71 * Some embedded boards have odd reference clocks (eg 25MHz)
72 * and we need to handle higher variances in the target baud rate.
74 #ifndef UART_DEV_TOLERANCE_PCT
75 #define UART_DEV_TOLERANCE_PCT 30
76 #endif /* UART_DEV_TOLERANCE_PCT */
78 static int broken_txfifo = 0;
79 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
80 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
83 * Clear pending interrupts. THRE is cleared by reading IIR. Data
84 * that may have been received gets lost here.
87 ns8250_clrint(struct uart_bas *bas)
91 iir = uart_getreg(bas, REG_IIR);
92 while ((iir & IIR_NOPEND) == 0) {
95 lsr = uart_getreg(bas, REG_LSR);
96 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
97 (void)uart_getreg(bas, REG_DATA);
98 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
99 (void)uart_getreg(bas, REG_DATA);
100 else if (iir == IIR_MLSC)
101 (void)uart_getreg(bas, REG_MSR);
103 iir = uart_getreg(bas, REG_IIR);
108 ns8250_delay(struct uart_bas *bas)
113 lcr = uart_getreg(bas, REG_LCR);
114 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
116 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
118 uart_setreg(bas, REG_LCR, lcr);
121 /* 1/10th the time to transmit 1 character (estimate). */
123 return (16000000 * divisor / bas->rclk);
124 return (16000 * divisor / (bas->rclk / 1000));
128 ns8250_divisor(int rclk, int baudrate)
130 int actual_baud, divisor;
136 divisor = (rclk / (baudrate << 3) + 1) >> 1;
137 if (divisor == 0 || divisor >= 65536)
139 actual_baud = rclk / (divisor << 4);
141 /* 10 times error in percent: */
142 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
144 /* enforce maximum error tolerance: */
145 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
152 ns8250_drain(struct uart_bas *bas, int what)
156 delay = ns8250_delay(bas);
158 if (what & UART_DRAIN_TRANSMITTER) {
160 * Pick an arbitrary high limit to avoid getting stuck in
161 * an infinite loop when the hardware is broken. Make the
162 * limit high enough to handle large FIFOs.
165 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
168 /* printf("ns8250: transmitter appears stuck... "); */
173 if (what & UART_DRAIN_RECEIVER) {
175 * Pick an arbitrary high limit to avoid getting stuck in
176 * an infinite loop when the hardware is broken. Make the
177 * limit high enough to handle large FIFOs and integrated
178 * UARTs. The HP rx2600 for example has 3 UARTs on the
179 * management board that tend to get a lot of data send
180 * to it when the UART is first activated.
183 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
184 (void)uart_getreg(bas, REG_DATA);
189 /* printf("ns8250: receiver appears broken... "); */
198 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
199 * drained. WARNING: this function clobbers the FIFO setting!
202 ns8250_flush(struct uart_bas *bas, int what)
210 if (what & UART_FLUSH_TRANSMITTER)
212 if (what & UART_FLUSH_RECEIVER)
214 uart_setreg(bas, REG_FCR, fcr);
219 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
228 else if (databits == 7)
230 else if (databits == 6)
240 divisor = ns8250_divisor(bas->rclk, baudrate);
243 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
245 uart_setreg(bas, REG_DLL, divisor & 0xff);
246 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
250 /* Set LCR and clear DLAB. */
251 uart_setreg(bas, REG_LCR, lcr);
257 * Low-level UART interface.
259 static int ns8250_probe(struct uart_bas *bas);
260 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
261 static void ns8250_term(struct uart_bas *bas);
262 static void ns8250_putc(struct uart_bas *bas, int);
263 static int ns8250_rxready(struct uart_bas *bas);
264 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
266 struct uart_ops uart_ns8250_ops = {
267 .probe = ns8250_probe,
271 .rxready = ns8250_rxready,
276 ns8250_probe(struct uart_bas *bas)
281 uart_setreg(bas, REG_FCR, FCR_UART_ON);
284 /* Check known 0 bits that don't depend on DLAB. */
285 val = uart_getreg(bas, REG_IIR);
289 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
290 * chip, but otherwise doesn't seem to have a function. In
291 * other words, uart(4) works regardless. Ignore that bit so
292 * the probe succeeds.
294 val = uart_getreg(bas, REG_MCR);
302 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
308 bas->rclk = DEFAULT_RCLK;
309 ns8250_param(bas, baudrate, databits, stopbits, parity);
311 /* Disable all interrupt sources. */
313 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
314 * UARTs split the receive time-out interrupt bit out separately as
315 * 0x10. This gets handled by ier_mask and ier_rxbits below.
317 ier = uart_getreg(bas, REG_IER) & 0xe0;
318 uart_setreg(bas, REG_IER, ier);
321 /* Disable the FIFO (if present). */
326 uart_setreg(bas, REG_FCR, val);
330 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
337 ns8250_term(struct uart_bas *bas)
340 /* Clear RTS & DTR. */
341 uart_setreg(bas, REG_MCR, MCR_IE);
346 ns8250_putc(struct uart_bas *bas, int c)
351 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
353 uart_setreg(bas, REG_DATA, c);
358 ns8250_rxready(struct uart_bas *bas)
361 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
365 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
371 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
377 c = uart_getreg(bas, REG_DATA);
384 static kobj_method_t ns8250_methods[] = {
385 KOBJMETHOD(uart_attach, ns8250_bus_attach),
386 KOBJMETHOD(uart_detach, ns8250_bus_detach),
387 KOBJMETHOD(uart_flush, ns8250_bus_flush),
388 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
389 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
390 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
391 KOBJMETHOD(uart_param, ns8250_bus_param),
392 KOBJMETHOD(uart_probe, ns8250_bus_probe),
393 KOBJMETHOD(uart_receive, ns8250_bus_receive),
394 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
395 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
396 KOBJMETHOD(uart_grab, ns8250_bus_grab),
397 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
401 struct uart_class uart_ns8250_class = {
404 sizeof(struct ns8250_softc),
405 .uc_ops = &uart_ns8250_ops,
407 .uc_rclk = DEFAULT_RCLK,
412 * XXX -- refactor out ACPI and FDT ifdefs
415 static struct acpi_uart_compat_data acpi_compat_data[] = {
416 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
417 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
418 {"MRVL0001", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
419 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
420 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
421 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
422 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
423 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
424 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
425 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
426 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
427 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
428 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
429 {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
431 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
435 static struct ofw_compat_data compat_data[] = {
436 {"ns16550", (uintptr_t)&uart_ns8250_class},
437 {"ns16550a", (uintptr_t)&uart_ns8250_class},
438 {NULL, (uintptr_t)NULL},
440 UART_FDT_CLASS_AND_DEVICE(compat_data);
443 /* Use token-pasting to form SER_ and MSR_ named constants. */
444 #define SER(sig) SER_##sig
445 #define SERD(sig) SER_D##sig
446 #define MSR(sig) MSR_##sig
447 #define MSRD(sig) MSR_D##sig
450 * Detect signal changes using software delta detection. The previous state of
451 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
452 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
453 * new state of both the signal and the delta bits.
455 #define SIGCHGSW(var, msr, sig) \
456 if ((msr) & MSR(sig)) { \
457 if ((var & SER(sig)) == 0) \
458 var |= SERD(sig) | SER(sig); \
460 if ((var & SER(sig)) != 0) \
461 var = SERD(sig) | (var & ~SER(sig)); \
465 * Detect signal changes using the hardware msr delta bits. This is currently
466 * used only when PPS timing information is being captured using the "narrow
467 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
468 * by time the interrupt handler is invoked. The hardware will latch the fact
469 * that it changed in the delta bits.
471 #define SIGCHGHW(var, msr, sig) \
472 if ((msr) & MSRD(sig)) { \
473 if (((msr) & MSR(sig)) != 0) \
474 var |= SERD(sig) | SER(sig); \
476 var = SERD(sig) | (var & ~SER(sig)); \
480 ns8250_bus_attach(struct uart_softc *sc)
482 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
483 struct uart_bas *bas;
491 /* Check whether uart has a broken txfifo. */
492 node = ofw_bus_get_node(sc->sc_dev);
493 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
494 broken_txfifo = cell ? 1 : 0;
499 ns8250->busy_detect = bas->busy_detect;
500 ns8250->mcr = uart_getreg(bas, REG_MCR);
501 ns8250->fcr = FCR_ENABLE;
503 ns8250->fcr |= FCR_UART_ON;
505 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
507 if (UART_FLAGS_FCR_RX_LOW(ivar))
508 ns8250->fcr |= FCR_RX_LOW;
509 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
510 ns8250->fcr |= FCR_RX_MEDL;
511 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
512 ns8250->fcr |= FCR_RX_HIGH;
514 ns8250->fcr |= FCR_RX_MEDH;
516 ns8250->fcr |= FCR_RX_MEDH;
520 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
522 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
524 /* Get IER RX interrupt bits */
525 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
526 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
528 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
530 uart_setreg(bas, REG_FCR, ns8250->fcr);
532 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
534 if (ns8250->mcr & MCR_DTR)
535 sc->sc_hwsig |= SER_DTR;
536 if (ns8250->mcr & MCR_RTS)
537 sc->sc_hwsig |= SER_RTS;
538 ns8250_bus_getsig(sc);
541 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
542 ns8250->ier |= ns8250->ier_rxbits;
543 uart_setreg(bas, REG_IER, ns8250->ier);
547 * Timing of the H/W access was changed with r253161 of uart_core.c
548 * It has been observed that an ITE IT8513E would signal a break
549 * condition with pretty much every character it received, unless
550 * it had enough time to settle between ns8250_bus_attach() and
551 * ns8250_bus_ipend() -- which it accidentally had before r253161.
552 * It's not understood why the UART chip behaves this way and it
553 * could very well be that the DELAY make the H/W work in the same
554 * accidental manner as before. More analysis is warranted, but
555 * at least now we fixed a known regression.
562 ns8250_bus_detach(struct uart_softc *sc)
564 struct ns8250_softc *ns8250;
565 struct uart_bas *bas;
568 ns8250 = (struct ns8250_softc *)sc;
570 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
571 uart_setreg(bas, REG_IER, ier);
578 ns8250_bus_flush(struct uart_softc *sc, int what)
580 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
581 struct uart_bas *bas;
585 uart_lock(sc->sc_hwmtx);
586 if (sc->sc_rxfifosz > 1) {
587 ns8250_flush(bas, what);
588 uart_setreg(bas, REG_FCR, ns8250->fcr);
592 error = ns8250_drain(bas, what);
593 uart_unlock(sc->sc_hwmtx);
598 ns8250_bus_getsig(struct uart_softc *sc)
604 * The delta bits are reputed to be broken on some hardware, so use
605 * software delta detection by default. Use the hardware delta bits
606 * when capturing PPS pulses which are too narrow for software detection
607 * to see the edges. Hardware delta for RI doesn't work like the
608 * others, so always use software for it. Other threads may be changing
609 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
610 * update without other changes happening. Note that the SIGCHGxx()
611 * macros carefully preserve the delta bits when we have to loop several
612 * times and a signal transitions between iterations.
617 uart_lock(sc->sc_hwmtx);
618 msr = uart_getreg(&sc->sc_bas, REG_MSR);
619 uart_unlock(sc->sc_hwmtx);
620 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
621 SIGCHGHW(sig, msr, DSR);
622 SIGCHGHW(sig, msr, CTS);
623 SIGCHGHW(sig, msr, DCD);
625 SIGCHGSW(sig, msr, DSR);
626 SIGCHGSW(sig, msr, CTS);
627 SIGCHGSW(sig, msr, DCD);
629 SIGCHGSW(sig, msr, RI);
630 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
635 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
637 struct uart_bas *bas;
638 int baudrate, divisor, error;
643 uart_lock(sc->sc_hwmtx);
645 case UART_IOCTL_BREAK:
646 lcr = uart_getreg(bas, REG_LCR);
651 uart_setreg(bas, REG_LCR, lcr);
654 case UART_IOCTL_IFLOW:
655 lcr = uart_getreg(bas, REG_LCR);
657 uart_setreg(bas, REG_LCR, 0xbf);
659 efr = uart_getreg(bas, REG_EFR);
664 uart_setreg(bas, REG_EFR, efr);
666 uart_setreg(bas, REG_LCR, lcr);
669 case UART_IOCTL_OFLOW:
670 lcr = uart_getreg(bas, REG_LCR);
672 uart_setreg(bas, REG_LCR, 0xbf);
674 efr = uart_getreg(bas, REG_EFR);
679 uart_setreg(bas, REG_EFR, efr);
681 uart_setreg(bas, REG_LCR, lcr);
684 case UART_IOCTL_BAUD:
685 lcr = uart_getreg(bas, REG_LCR);
686 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
688 divisor = uart_getreg(bas, REG_DLL) |
689 (uart_getreg(bas, REG_DLH) << 8);
691 uart_setreg(bas, REG_LCR, lcr);
693 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
695 *(int*)data = baudrate;
703 uart_unlock(sc->sc_hwmtx);
708 ns8250_bus_ipend(struct uart_softc *sc)
710 struct uart_bas *bas;
711 struct ns8250_softc *ns8250;
715 ns8250 = (struct ns8250_softc *)sc;
717 uart_lock(sc->sc_hwmtx);
718 iir = uart_getreg(bas, REG_IIR);
720 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
721 (void)uart_getreg(bas, DW_REG_USR);
722 uart_unlock(sc->sc_hwmtx);
725 if (iir & IIR_NOPEND) {
726 uart_unlock(sc->sc_hwmtx);
730 if (iir & IIR_RXRDY) {
731 lsr = uart_getreg(bas, REG_LSR);
733 ipend |= SER_INT_OVERRUN;
735 ipend |= SER_INT_BREAK;
737 ipend |= SER_INT_RXREADY;
739 if (iir & IIR_TXRDY) {
740 ipend |= SER_INT_TXIDLE;
741 ns8250->ier &= ~IER_ETXRDY;
742 uart_setreg(bas, REG_IER, ns8250->ier);
745 ipend |= SER_INT_SIGCHG;
749 uart_unlock(sc->sc_hwmtx);
754 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
755 int stopbits, int parity)
757 struct ns8250_softc *ns8250;
758 struct uart_bas *bas;
761 ns8250 = (struct ns8250_softc*)sc;
763 uart_lock(sc->sc_hwmtx);
765 * When using DW UART with BUSY detection it is necessary to wait
766 * until all serial transfers are finished before manipulating the
767 * line control. LCR will not be affected when UART is busy.
769 if (ns8250->busy_detect != 0) {
771 * Pick an arbitrary high limit to avoid getting stuck in
772 * an infinite loop in case when the hardware is broken.
775 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
780 /* UART appears to be stuck */
781 uart_unlock(sc->sc_hwmtx);
786 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
787 uart_unlock(sc->sc_hwmtx);
792 ns8250_bus_probe(struct uart_softc *sc)
794 struct ns8250_softc *ns8250;
795 struct uart_bas *bas;
796 int count, delay, error, limit;
797 uint8_t lsr, mcr, ier;
800 ns8250 = (struct ns8250_softc *)sc;
803 error = ns8250_probe(bas);
808 if (sc->sc_sysdev == NULL) {
809 /* By using ns8250_init() we also set DTR and RTS. */
810 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
812 mcr |= MCR_DTR | MCR_RTS;
814 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
819 * Set loopback mode. This avoids having garbage on the wire and
820 * also allows us send and receive data. We set DTR and RTS to
821 * avoid the possibility that automatic flow-control prevents
822 * any data from being sent.
824 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
828 * Enable FIFOs. And check that the UART has them. If not, we're
829 * done. Since this is the first time we enable the FIFOs, we reset
836 uart_setreg(bas, REG_FCR, val);
838 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
840 * NS16450 or INS8250. We don't bother to differentiate
841 * between them. They're too old to be interesting.
843 uart_setreg(bas, REG_MCR, mcr);
845 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
846 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
850 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
854 uart_setreg(bas, REG_FCR, val);
858 delay = ns8250_delay(bas);
860 /* We have FIFOs. Drain the transmitter and receiver. */
861 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
863 uart_setreg(bas, REG_MCR, mcr);
868 uart_setreg(bas, REG_FCR, val);
874 * We should have a sufficiently clean "pipe" to determine the
875 * size of the FIFOs. We send as much characters as is reasonable
876 * and wait for the overflow bit in the LSR register to be
877 * asserted, counting the characters as we send them. Based on
878 * that count we know the FIFO size.
881 uart_setreg(bas, REG_DATA, 0);
888 * LSR bits are cleared upon read, so we must accumulate
889 * them to be able to test LSR_OE below.
891 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
895 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
896 uart_setreg(bas, REG_IER, ier);
897 uart_setreg(bas, REG_MCR, mcr);
902 uart_setreg(bas, REG_FCR, val);
907 } while ((lsr & LSR_OE) == 0 && count < 260);
910 uart_setreg(bas, REG_MCR, mcr);
913 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
916 if (count >= 14 && count <= 16) {
917 sc->sc_rxfifosz = 16;
918 device_set_desc(sc->sc_dev, "16550 or compatible");
919 } else if (count >= 28 && count <= 32) {
920 sc->sc_rxfifosz = 32;
921 device_set_desc(sc->sc_dev, "16650 or compatible");
922 } else if (count >= 56 && count <= 64) {
923 sc->sc_rxfifosz = 64;
924 device_set_desc(sc->sc_dev, "16750 or compatible");
925 } else if (count >= 112 && count <= 128) {
926 sc->sc_rxfifosz = 128;
927 device_set_desc(sc->sc_dev, "16950 or compatible");
928 } else if (count >= 224 && count <= 256) {
929 sc->sc_rxfifosz = 256;
930 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
932 sc->sc_rxfifosz = 16;
933 device_set_desc(sc->sc_dev,
934 "Non-standard ns8250 class UART with FIFOs");
938 * Force the Tx FIFO size to 16 bytes for now. We don't program the
939 * Tx trigger. Also, we assume that all data has been sent when the
942 sc->sc_txfifosz = 16;
946 * XXX there are some issues related to hardware flow control and
947 * it's likely that uart(4) is the cause. This basically needs more
948 * investigation, but we avoid using for hardware flow control
951 /* 16650s or higher have automatic flow control. */
952 if (sc->sc_rxfifosz > 16) {
962 ns8250_bus_receive(struct uart_softc *sc)
964 struct uart_bas *bas;
969 uart_lock(sc->sc_hwmtx);
970 lsr = uart_getreg(bas, REG_LSR);
971 while (lsr & LSR_RXRDY) {
972 if (uart_rx_full(sc)) {
973 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
976 xc = uart_getreg(bas, REG_DATA);
978 xc |= UART_STAT_FRAMERR;
980 xc |= UART_STAT_PARERR;
982 lsr = uart_getreg(bas, REG_LSR);
984 /* Discard everything left in the Rx FIFO. */
985 while (lsr & LSR_RXRDY) {
986 (void)uart_getreg(bas, REG_DATA);
988 lsr = uart_getreg(bas, REG_LSR);
990 uart_unlock(sc->sc_hwmtx);
995 ns8250_bus_setsig(struct uart_softc *sc, int sig)
997 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
998 struct uart_bas *bas;
1005 if (sig & SER_DDTR) {
1006 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1008 if (sig & SER_DRTS) {
1009 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1011 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1012 uart_lock(sc->sc_hwmtx);
1013 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1015 ns8250->mcr |= MCR_DTR;
1017 ns8250->mcr |= MCR_RTS;
1018 uart_setreg(bas, REG_MCR, ns8250->mcr);
1020 uart_unlock(sc->sc_hwmtx);
1025 ns8250_bus_transmit(struct uart_softc *sc)
1027 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1028 struct uart_bas *bas;
1032 uart_lock(sc->sc_hwmtx);
1033 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1035 for (i = 0; i < sc->sc_txdatasz; i++) {
1036 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1040 ns8250->ier |= IER_ETXRDY;
1041 uart_setreg(bas, REG_IER, ns8250->ier);
1044 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1047 uart_unlock(sc->sc_hwmtx);
1049 uart_sched_softih(sc, SER_INT_TXIDLE);
1054 ns8250_bus_grab(struct uart_softc *sc)
1056 struct uart_bas *bas = &sc->sc_bas;
1057 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1061 * turn off all interrupts to enter polling mode. Leave the
1062 * saved mask alone. We'll restore whatever it was in ungrab.
1063 * All pending interrupt signals are reset when IER is set to 0.
1065 uart_lock(sc->sc_hwmtx);
1066 ier = uart_getreg(bas, REG_IER);
1067 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1069 uart_unlock(sc->sc_hwmtx);
1073 ns8250_bus_ungrab(struct uart_softc *sc)
1075 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1076 struct uart_bas *bas = &sc->sc_bas;
1079 * Restore previous interrupt mask
1081 uart_lock(sc->sc_hwmtx);
1082 uart_setreg(bas, REG_IER, ns8250->ier);
1084 uart_unlock(sc->sc_hwmtx);