2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
48 #include <dev/uart/uart_bus.h>
49 #include <dev/uart/uart_dev_ns8250.h>
51 #include <dev/ic/ns16550.h>
55 #define DEFAULT_RCLK 1843200
57 static int broken_txfifo = 0;
58 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
60 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
63 * Clear pending interrupts. THRE is cleared by reading IIR. Data
64 * that may have been received gets lost here.
67 ns8250_clrint(struct uart_bas *bas)
71 iir = uart_getreg(bas, REG_IIR);
72 while ((iir & IIR_NOPEND) == 0) {
75 lsr = uart_getreg(bas, REG_LSR);
76 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
77 (void)uart_getreg(bas, REG_DATA);
78 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
79 (void)uart_getreg(bas, REG_DATA);
80 else if (iir == IIR_MLSC)
81 (void)uart_getreg(bas, REG_MSR);
83 iir = uart_getreg(bas, REG_IIR);
88 ns8250_delay(struct uart_bas *bas)
93 lcr = uart_getreg(bas, REG_LCR);
94 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
96 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
98 uart_setreg(bas, REG_LCR, lcr);
101 /* 1/10th the time to transmit 1 character (estimate). */
103 return (16000000 * divisor / bas->rclk);
104 return (16000 * divisor / (bas->rclk / 1000));
108 ns8250_divisor(int rclk, int baudrate)
110 int actual_baud, divisor;
116 divisor = (rclk / (baudrate << 3) + 1) >> 1;
117 if (divisor == 0 || divisor >= 65536)
119 actual_baud = rclk / (divisor << 4);
121 /* 10 times error in percent: */
122 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
124 /* 3.0% maximum error tolerance: */
125 if (error < -30 || error > 30)
132 ns8250_drain(struct uart_bas *bas, int what)
136 delay = ns8250_delay(bas);
138 if (what & UART_DRAIN_TRANSMITTER) {
140 * Pick an arbitrary high limit to avoid getting stuck in
141 * an infinite loop when the hardware is broken. Make the
142 * limit high enough to handle large FIFOs.
145 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
148 /* printf("ns8250: transmitter appears stuck... "); */
153 if (what & UART_DRAIN_RECEIVER) {
155 * Pick an arbitrary high limit to avoid getting stuck in
156 * an infinite loop when the hardware is broken. Make the
157 * limit high enough to handle large FIFOs and integrated
158 * UARTs. The HP rx2600 for example has 3 UARTs on the
159 * management board that tend to get a lot of data send
160 * to it when the UART is first activated.
163 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
164 (void)uart_getreg(bas, REG_DATA);
169 /* printf("ns8250: receiver appears broken... "); */
178 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
179 * drained. WARNING: this function clobbers the FIFO setting!
182 ns8250_flush(struct uart_bas *bas, int what)
187 if (what & UART_FLUSH_TRANSMITTER)
189 if (what & UART_FLUSH_RECEIVER)
191 uart_setreg(bas, REG_FCR, fcr);
196 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
205 else if (databits == 7)
207 else if (databits == 6)
217 divisor = ns8250_divisor(bas->rclk, baudrate);
220 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
222 uart_setreg(bas, REG_DLL, divisor & 0xff);
223 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
227 /* Set LCR and clear DLAB. */
228 uart_setreg(bas, REG_LCR, lcr);
234 * Low-level UART interface.
236 static int ns8250_probe(struct uart_bas *bas);
237 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
238 static void ns8250_term(struct uart_bas *bas);
239 static void ns8250_putc(struct uart_bas *bas, int);
240 static int ns8250_rxready(struct uart_bas *bas);
241 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
243 struct uart_ops uart_ns8250_ops = {
244 .probe = ns8250_probe,
248 .rxready = ns8250_rxready,
253 ns8250_probe(struct uart_bas *bas)
257 /* Check known 0 bits that don't depend on DLAB. */
258 val = uart_getreg(bas, REG_IIR);
262 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
263 * chip, but otherwise doesn't seem to have a function. In
264 * other words, uart(4) works regardless. Ignore that bit so
265 * the probe succeeds.
267 val = uart_getreg(bas, REG_MCR);
275 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
281 bas->rclk = DEFAULT_RCLK;
282 ns8250_param(bas, baudrate, databits, stopbits, parity);
284 /* Disable all interrupt sources. */
286 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
287 * UARTs split the receive time-out interrupt bit out separately as
288 * 0x10. This gets handled by ier_mask and ier_rxbits below.
290 ier = uart_getreg(bas, REG_IER) & 0xe0;
291 uart_setreg(bas, REG_IER, ier);
294 /* Disable the FIFO (if present). */
295 uart_setreg(bas, REG_FCR, 0);
299 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
306 ns8250_term(struct uart_bas *bas)
309 /* Clear RTS & DTR. */
310 uart_setreg(bas, REG_MCR, MCR_IE);
315 ns8250_putc(struct uart_bas *bas, int c)
320 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
322 uart_setreg(bas, REG_DATA, c);
325 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
330 ns8250_rxready(struct uart_bas *bas)
333 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
337 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
343 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
349 c = uart_getreg(bas, REG_DATA);
356 static kobj_method_t ns8250_methods[] = {
357 KOBJMETHOD(uart_attach, ns8250_bus_attach),
358 KOBJMETHOD(uart_detach, ns8250_bus_detach),
359 KOBJMETHOD(uart_flush, ns8250_bus_flush),
360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
363 KOBJMETHOD(uart_param, ns8250_bus_param),
364 KOBJMETHOD(uart_probe, ns8250_bus_probe),
365 KOBJMETHOD(uart_receive, ns8250_bus_receive),
366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
368 KOBJMETHOD(uart_grab, ns8250_bus_grab),
369 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
373 struct uart_class uart_ns8250_class = {
376 sizeof(struct ns8250_softc),
377 .uc_ops = &uart_ns8250_ops,
379 .uc_rclk = DEFAULT_RCLK
382 #define SIGCHG(c, i, s, d) \
384 i |= (i & s) ? s : s | d; \
386 i = (i & s) ? (i & ~s) | d : i; \
390 ns8250_bus_attach(struct uart_softc *sc)
392 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
393 struct uart_bas *bas;
400 ns8250->busy_detect = 0;
404 * Check whether uart requires to read USR reg when IIR_BUSY and
407 node = ofw_bus_get_node(sc->sc_dev);
408 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
409 ns8250->busy_detect = 1;
410 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
416 ns8250->mcr = uart_getreg(bas, REG_MCR);
417 ns8250->fcr = FCR_ENABLE;
418 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
420 if (UART_FLAGS_FCR_RX_LOW(ivar))
421 ns8250->fcr |= FCR_RX_LOW;
422 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
423 ns8250->fcr |= FCR_RX_MEDL;
424 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
425 ns8250->fcr |= FCR_RX_HIGH;
427 ns8250->fcr |= FCR_RX_MEDH;
429 ns8250->fcr |= FCR_RX_MEDH;
433 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
435 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
437 /* Get IER RX interrupt bits */
438 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
439 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
441 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
443 uart_setreg(bas, REG_FCR, ns8250->fcr);
445 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
447 if (ns8250->mcr & MCR_DTR)
448 sc->sc_hwsig |= SER_DTR;
449 if (ns8250->mcr & MCR_RTS)
450 sc->sc_hwsig |= SER_RTS;
451 ns8250_bus_getsig(sc);
454 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
455 ns8250->ier |= ns8250->ier_rxbits;
456 uart_setreg(bas, REG_IER, ns8250->ier);
460 * Timing of the H/W access was changed with r253161 of uart_core.c
461 * It has been observed that an ITE IT8513E would signal a break
462 * condition with pretty much every character it received, unless
463 * it had enough time to settle between ns8250_bus_attach() and
464 * ns8250_bus_ipend() -- which it accidentally had before r253161.
465 * It's not understood why the UART chip behaves this way and it
466 * could very well be that the DELAY make the H/W work in the same
467 * accidental manner as before. More analysis is warranted, but
468 * at least now we fixed a known regression.
475 ns8250_bus_detach(struct uart_softc *sc)
477 struct ns8250_softc *ns8250;
478 struct uart_bas *bas;
481 ns8250 = (struct ns8250_softc *)sc;
483 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
484 uart_setreg(bas, REG_IER, ier);
491 ns8250_bus_flush(struct uart_softc *sc, int what)
493 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
494 struct uart_bas *bas;
498 uart_lock(sc->sc_hwmtx);
499 if (sc->sc_rxfifosz > 1) {
500 ns8250_flush(bas, what);
501 uart_setreg(bas, REG_FCR, ns8250->fcr);
505 error = ns8250_drain(bas, what);
506 uart_unlock(sc->sc_hwmtx);
511 ns8250_bus_getsig(struct uart_softc *sc)
513 uint32_t new, old, sig;
519 uart_lock(sc->sc_hwmtx);
520 msr = uart_getreg(&sc->sc_bas, REG_MSR);
521 uart_unlock(sc->sc_hwmtx);
522 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
523 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
524 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
525 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
526 new = sig & ~SER_MASK_DELTA;
527 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
532 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
534 struct uart_bas *bas;
535 int baudrate, divisor, error;
540 uart_lock(sc->sc_hwmtx);
542 case UART_IOCTL_BREAK:
543 lcr = uart_getreg(bas, REG_LCR);
548 uart_setreg(bas, REG_LCR, lcr);
551 case UART_IOCTL_IFLOW:
552 lcr = uart_getreg(bas, REG_LCR);
554 uart_setreg(bas, REG_LCR, 0xbf);
556 efr = uart_getreg(bas, REG_EFR);
561 uart_setreg(bas, REG_EFR, efr);
563 uart_setreg(bas, REG_LCR, lcr);
566 case UART_IOCTL_OFLOW:
567 lcr = uart_getreg(bas, REG_LCR);
569 uart_setreg(bas, REG_LCR, 0xbf);
571 efr = uart_getreg(bas, REG_EFR);
576 uart_setreg(bas, REG_EFR, efr);
578 uart_setreg(bas, REG_LCR, lcr);
581 case UART_IOCTL_BAUD:
582 lcr = uart_getreg(bas, REG_LCR);
583 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
585 divisor = uart_getreg(bas, REG_DLL) |
586 (uart_getreg(bas, REG_DLH) << 8);
588 uart_setreg(bas, REG_LCR, lcr);
590 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
592 *(int*)data = baudrate;
600 uart_unlock(sc->sc_hwmtx);
605 ns8250_bus_ipend(struct uart_softc *sc)
607 struct uart_bas *bas;
608 struct ns8250_softc *ns8250;
612 ns8250 = (struct ns8250_softc *)sc;
614 uart_lock(sc->sc_hwmtx);
615 iir = uart_getreg(bas, REG_IIR);
617 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
618 (void)uart_getreg(bas, DW_REG_USR);
619 uart_unlock(sc->sc_hwmtx);
622 if (iir & IIR_NOPEND) {
623 uart_unlock(sc->sc_hwmtx);
627 if (iir & IIR_RXRDY) {
628 lsr = uart_getreg(bas, REG_LSR);
630 ipend |= SER_INT_OVERRUN;
632 ipend |= SER_INT_BREAK;
634 ipend |= SER_INT_RXREADY;
636 if (iir & IIR_TXRDY) {
637 ipend |= SER_INT_TXIDLE;
638 uart_setreg(bas, REG_IER, ns8250->ier);
640 ipend |= SER_INT_SIGCHG;
644 uart_unlock(sc->sc_hwmtx);
649 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
650 int stopbits, int parity)
652 struct ns8250_softc *ns8250;
653 struct uart_bas *bas;
656 ns8250 = (struct ns8250_softc*)sc;
658 uart_lock(sc->sc_hwmtx);
660 * When using DW UART with BUSY detection it is necessary to wait
661 * until all serial transfers are finished before manipulating the
662 * line control. LCR will not be affected when UART is busy.
664 if (ns8250->busy_detect != 0) {
666 * Pick an arbitrary high limit to avoid getting stuck in
667 * an infinite loop in case when the hardware is broken.
670 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
675 /* UART appears to be stuck */
676 uart_unlock(sc->sc_hwmtx);
681 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
682 uart_unlock(sc->sc_hwmtx);
687 ns8250_bus_probe(struct uart_softc *sc)
689 struct ns8250_softc *ns8250;
690 struct uart_bas *bas;
691 int count, delay, error, limit;
692 uint8_t lsr, mcr, ier;
694 ns8250 = (struct ns8250_softc *)sc;
697 error = ns8250_probe(bas);
702 if (sc->sc_sysdev == NULL) {
703 /* By using ns8250_init() we also set DTR and RTS. */
704 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
706 mcr |= MCR_DTR | MCR_RTS;
708 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
713 * Set loopback mode. This avoids having garbage on the wire and
714 * also allows us send and receive data. We set DTR and RTS to
715 * avoid the possibility that automatic flow-control prevents
716 * any data from being sent.
718 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
722 * Enable FIFOs. And check that the UART has them. If not, we're
723 * done. Since this is the first time we enable the FIFOs, we reset
726 uart_setreg(bas, REG_FCR, FCR_ENABLE);
728 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
730 * NS16450 or INS8250. We don't bother to differentiate
731 * between them. They're too old to be interesting.
733 uart_setreg(bas, REG_MCR, mcr);
735 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
736 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
740 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
744 delay = ns8250_delay(bas);
746 /* We have FIFOs. Drain the transmitter and receiver. */
747 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
749 uart_setreg(bas, REG_MCR, mcr);
750 uart_setreg(bas, REG_FCR, 0);
756 * We should have a sufficiently clean "pipe" to determine the
757 * size of the FIFOs. We send as much characters as is reasonable
758 * and wait for the overflow bit in the LSR register to be
759 * asserted, counting the characters as we send them. Based on
760 * that count we know the FIFO size.
763 uart_setreg(bas, REG_DATA, 0);
770 * LSR bits are cleared upon read, so we must accumulate
771 * them to be able to test LSR_OE below.
773 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
777 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
778 uart_setreg(bas, REG_IER, ier);
779 uart_setreg(bas, REG_MCR, mcr);
780 uart_setreg(bas, REG_FCR, 0);
785 } while ((lsr & LSR_OE) == 0 && count < 130);
788 uart_setreg(bas, REG_MCR, mcr);
791 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
794 if (count >= 14 && count <= 16) {
795 sc->sc_rxfifosz = 16;
796 device_set_desc(sc->sc_dev, "16550 or compatible");
797 } else if (count >= 28 && count <= 32) {
798 sc->sc_rxfifosz = 32;
799 device_set_desc(sc->sc_dev, "16650 or compatible");
800 } else if (count >= 56 && count <= 64) {
801 sc->sc_rxfifosz = 64;
802 device_set_desc(sc->sc_dev, "16750 or compatible");
803 } else if (count >= 112 && count <= 128) {
804 sc->sc_rxfifosz = 128;
805 device_set_desc(sc->sc_dev, "16950 or compatible");
807 sc->sc_rxfifosz = 16;
808 device_set_desc(sc->sc_dev,
809 "Non-standard ns8250 class UART with FIFOs");
813 * Force the Tx FIFO size to 16 bytes for now. We don't program the
814 * Tx trigger. Also, we assume that all data has been sent when the
817 sc->sc_txfifosz = 16;
821 * XXX there are some issues related to hardware flow control and
822 * it's likely that uart(4) is the cause. This basicly needs more
823 * investigation, but we avoid using for hardware flow control
826 /* 16650s or higher have automatic flow control. */
827 if (sc->sc_rxfifosz > 16) {
837 ns8250_bus_receive(struct uart_softc *sc)
839 struct uart_bas *bas;
844 uart_lock(sc->sc_hwmtx);
845 lsr = uart_getreg(bas, REG_LSR);
846 while (lsr & LSR_RXRDY) {
847 if (uart_rx_full(sc)) {
848 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
851 xc = uart_getreg(bas, REG_DATA);
853 xc |= UART_STAT_FRAMERR;
855 xc |= UART_STAT_PARERR;
857 lsr = uart_getreg(bas, REG_LSR);
859 /* Discard everything left in the Rx FIFO. */
860 while (lsr & LSR_RXRDY) {
861 (void)uart_getreg(bas, REG_DATA);
863 lsr = uart_getreg(bas, REG_LSR);
865 uart_unlock(sc->sc_hwmtx);
870 ns8250_bus_setsig(struct uart_softc *sc, int sig)
872 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
873 struct uart_bas *bas;
880 if (sig & SER_DDTR) {
881 SIGCHG(sig & SER_DTR, new, SER_DTR,
884 if (sig & SER_DRTS) {
885 SIGCHG(sig & SER_RTS, new, SER_RTS,
888 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
889 uart_lock(sc->sc_hwmtx);
890 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
892 ns8250->mcr |= MCR_DTR;
894 ns8250->mcr |= MCR_RTS;
895 uart_setreg(bas, REG_MCR, ns8250->mcr);
897 uart_unlock(sc->sc_hwmtx);
902 ns8250_bus_transmit(struct uart_softc *sc)
904 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
905 struct uart_bas *bas;
909 uart_lock(sc->sc_hwmtx);
910 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
912 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
914 for (i = 0; i < sc->sc_txdatasz; i++) {
915 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
919 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
922 uart_unlock(sc->sc_hwmtx);
924 uart_sched_softih(sc, SER_INT_TXIDLE);
929 ns8250_bus_grab(struct uart_softc *sc)
931 struct uart_bas *bas = &sc->sc_bas;
934 * turn off all interrupts to enter polling mode. Leave the
935 * saved mask alone. We'll restore whatever it was in ungrab.
936 * All pending interupt signals are reset when IER is set to 0.
938 uart_lock(sc->sc_hwmtx);
939 uart_setreg(bas, REG_IER, 0);
941 uart_unlock(sc->sc_hwmtx);
945 ns8250_bus_ungrab(struct uart_softc *sc)
947 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
948 struct uart_bas *bas = &sc->sc_bas;
951 * Restore previous interrupt mask
953 uart_lock(sc->sc_hwmtx);
954 uart_setreg(bas, REG_IER, ns8250->ier);
956 uart_unlock(sc->sc_hwmtx);