2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
44 #define DEFAULT_RCLK 1843200
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
51 ns8250_clrint(struct uart_bas *bas)
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
59 (void)uart_getreg(bas, REG_LSR);
60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
61 (void)uart_getreg(bas, REG_DATA);
62 else if (iir == IIR_MLSC)
63 (void)uart_getreg(bas, REG_MSR);
65 iir = uart_getreg(bas, REG_IIR);
70 ns8250_delay(struct uart_bas *bas)
75 lcr = uart_getreg(bas, REG_LCR);
76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
80 uart_setreg(bas, REG_LCR, lcr);
83 /* 1/10th the time to transmit 1 character (estimate). */
84 return (16000000 * divisor / bas->rclk);
88 ns8250_divisor(int rclk, int baudrate)
90 int actual_baud, divisor;
96 divisor = (rclk / (baudrate << 3) + 1) >> 1;
97 if (divisor == 0 || divisor >= 65536)
99 actual_baud = rclk / (divisor << 4);
101 /* 10 times error in percent: */
102 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
104 /* 3.0% maximum error tolerance: */
105 if (error < -30 || error > 30)
112 ns8250_drain(struct uart_bas *bas, int what)
116 delay = ns8250_delay(bas);
118 if (what & UART_DRAIN_TRANSMITTER) {
120 * Pick an arbitrary high limit to avoid getting stuck in
121 * an infinite loop when the hardware is broken. Make the
122 * limit high enough to handle large FIFOs.
125 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
128 /* printf("ns8250: transmitter appears stuck... "); */
133 if (what & UART_DRAIN_RECEIVER) {
135 * Pick an arbitrary high limit to avoid getting stuck in
136 * an infinite loop when the hardware is broken. Make the
137 * limit high enough to handle large FIFOs and integrated
138 * UARTs. The HP rx2600 for example has 3 UARTs on the
139 * management board that tend to get a lot of data send
140 * to it when the UART is first activated.
143 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
144 (void)uart_getreg(bas, REG_DATA);
149 /* printf("ns8250: receiver appears broken... "); */
158 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
159 * drained. WARNING: this function clobbers the FIFO setting!
162 ns8250_flush(struct uart_bas *bas, int what)
167 if (what & UART_FLUSH_TRANSMITTER)
169 if (what & UART_FLUSH_RECEIVER)
171 uart_setreg(bas, REG_FCR, fcr);
176 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
185 else if (databits == 7)
187 else if (databits == 6)
197 divisor = ns8250_divisor(bas->rclk, baudrate);
200 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
202 uart_setreg(bas, REG_DLL, divisor & 0xff);
203 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
207 /* Set LCR and clear DLAB. */
208 uart_setreg(bas, REG_LCR, lcr);
214 * Low-level UART interface.
216 static int ns8250_probe(struct uart_bas *bas);
217 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
218 static void ns8250_term(struct uart_bas *bas);
219 static void ns8250_putc(struct uart_bas *bas, int);
220 static int ns8250_poll(struct uart_bas *bas);
221 static int ns8250_getc(struct uart_bas *bas);
223 struct uart_ops uart_ns8250_ops = {
224 .probe = ns8250_probe,
233 ns8250_probe(struct uart_bas *bas)
237 /* Check known 0 bits that don't depend on DLAB. */
238 val = uart_getreg(bas, REG_IIR);
241 val = uart_getreg(bas, REG_MCR);
249 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
255 bas->rclk = DEFAULT_RCLK;
256 ns8250_param(bas, baudrate, databits, stopbits, parity);
258 /* Disable all interrupt sources. */
259 ier = uart_getreg(bas, REG_IER) & 0xf0;
260 uart_setreg(bas, REG_IER, ier);
263 /* Disable the FIFO (if present). */
264 uart_setreg(bas, REG_FCR, 0);
268 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
275 ns8250_term(struct uart_bas *bas)
278 /* Clear RTS & DTR. */
279 uart_setreg(bas, REG_MCR, MCR_IE);
284 ns8250_putc(struct uart_bas *bas, int c)
288 /* 1/10th the time to transmit 1 character (estimate). */
289 delay = ns8250_delay(bas);
292 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
294 uart_setreg(bas, REG_DATA, c);
297 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
302 ns8250_poll(struct uart_bas *bas)
305 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY)
306 return (uart_getreg(bas, REG_DATA));
311 ns8250_getc(struct uart_bas *bas)
315 /* 1/10th the time to transmit 1 character (estimate). */
316 delay = ns8250_delay(bas);
318 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0)
320 return (uart_getreg(bas, REG_DATA));
324 * High-level UART interface.
326 struct ns8250_softc {
327 struct uart_softc base;
333 static int ns8250_bus_attach(struct uart_softc *);
334 static int ns8250_bus_detach(struct uart_softc *);
335 static int ns8250_bus_flush(struct uart_softc *, int);
336 static int ns8250_bus_getsig(struct uart_softc *);
337 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
338 static int ns8250_bus_ipend(struct uart_softc *);
339 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
340 static int ns8250_bus_probe(struct uart_softc *);
341 static int ns8250_bus_receive(struct uart_softc *);
342 static int ns8250_bus_setsig(struct uart_softc *, int);
343 static int ns8250_bus_transmit(struct uart_softc *);
345 static kobj_method_t ns8250_methods[] = {
346 KOBJMETHOD(uart_attach, ns8250_bus_attach),
347 KOBJMETHOD(uart_detach, ns8250_bus_detach),
348 KOBJMETHOD(uart_flush, ns8250_bus_flush),
349 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
350 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
351 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
352 KOBJMETHOD(uart_param, ns8250_bus_param),
353 KOBJMETHOD(uart_probe, ns8250_bus_probe),
354 KOBJMETHOD(uart_receive, ns8250_bus_receive),
355 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
356 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
360 struct uart_class uart_ns8250_class = {
363 sizeof(struct ns8250_softc),
365 .uc_rclk = DEFAULT_RCLK
368 #define SIGCHG(c, i, s, d) \
370 i |= (i & s) ? s : s | d; \
372 i = (i & s) ? (i & ~s) | d : i; \
376 ns8250_bus_attach(struct uart_softc *sc)
378 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
379 struct uart_bas *bas;
383 ns8250->mcr = uart_getreg(bas, REG_MCR);
384 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH;
385 uart_setreg(bas, REG_FCR, ns8250->fcr);
387 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
389 if (ns8250->mcr & MCR_DTR)
390 sc->sc_hwsig |= SER_DTR;
391 if (ns8250->mcr & MCR_RTS)
392 sc->sc_hwsig |= SER_RTS;
393 ns8250_bus_getsig(sc);
396 ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0;
397 ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
398 uart_setreg(bas, REG_IER, ns8250->ier);
404 ns8250_bus_detach(struct uart_softc *sc)
406 struct uart_bas *bas;
410 ier = uart_getreg(bas, REG_IER) & 0xf0;
411 uart_setreg(bas, REG_IER, ier);
418 ns8250_bus_flush(struct uart_softc *sc, int what)
420 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
421 struct uart_bas *bas;
425 mtx_lock_spin(&sc->sc_hwmtx);
426 if (sc->sc_hasfifo) {
427 ns8250_flush(bas, what);
428 uart_setreg(bas, REG_FCR, ns8250->fcr);
432 error = ns8250_drain(bas, what);
433 mtx_unlock_spin(&sc->sc_hwmtx);
438 ns8250_bus_getsig(struct uart_softc *sc)
440 uint32_t new, old, sig;
446 mtx_lock_spin(&sc->sc_hwmtx);
447 msr = uart_getreg(&sc->sc_bas, REG_MSR);
448 mtx_unlock_spin(&sc->sc_hwmtx);
449 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
450 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
451 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
452 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
453 new = sig & ~UART_SIGMASK_DELTA;
454 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
459 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
461 struct uart_bas *bas;
462 int baudrate, divisor, error;
467 mtx_lock_spin(&sc->sc_hwmtx);
469 case UART_IOCTL_BREAK:
470 lcr = uart_getreg(bas, REG_LCR);
475 uart_setreg(bas, REG_LCR, lcr);
478 case UART_IOCTL_IFLOW:
479 lcr = uart_getreg(bas, REG_LCR);
481 uart_setreg(bas, REG_LCR, 0xbf);
483 efr = uart_getreg(bas, REG_EFR);
488 uart_setreg(bas, REG_EFR, efr);
490 uart_setreg(bas, REG_LCR, lcr);
493 case UART_IOCTL_OFLOW:
494 lcr = uart_getreg(bas, REG_LCR);
496 uart_setreg(bas, REG_LCR, 0xbf);
498 efr = uart_getreg(bas, REG_EFR);
503 uart_setreg(bas, REG_EFR, efr);
505 uart_setreg(bas, REG_LCR, lcr);
508 case UART_IOCTL_BAUD:
509 lcr = uart_getreg(bas, REG_LCR);
510 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
512 divisor = uart_getreg(bas, REG_DLL) |
513 (uart_getreg(bas, REG_DLH) << 8);
515 uart_setreg(bas, REG_LCR, lcr);
517 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
519 *(int*)data = baudrate;
527 mtx_unlock_spin(&sc->sc_hwmtx);
532 ns8250_bus_ipend(struct uart_softc *sc)
534 struct uart_bas *bas;
539 mtx_lock_spin(&sc->sc_hwmtx);
540 iir = uart_getreg(bas, REG_IIR);
541 if (iir & IIR_NOPEND) {
542 mtx_unlock_spin(&sc->sc_hwmtx);
546 if (iir & IIR_RXRDY) {
547 lsr = uart_getreg(bas, REG_LSR);
548 mtx_unlock_spin(&sc->sc_hwmtx);
550 ipend |= UART_IPEND_OVERRUN;
552 ipend |= UART_IPEND_BREAK;
554 ipend |= UART_IPEND_RXREADY;
556 mtx_unlock_spin(&sc->sc_hwmtx);
558 ipend |= UART_IPEND_TXIDLE;
560 ipend |= UART_IPEND_SIGCHG;
562 return ((sc->sc_leaving) ? 0 : ipend);
566 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
567 int stopbits, int parity)
569 struct uart_bas *bas;
573 mtx_lock_spin(&sc->sc_hwmtx);
574 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
575 mtx_unlock_spin(&sc->sc_hwmtx);
580 ns8250_bus_probe(struct uart_softc *sc)
582 struct uart_bas *bas;
583 int count, delay, error, limit;
584 uint8_t lsr, mcr, ier;
588 error = ns8250_probe(bas);
593 if (sc->sc_sysdev == NULL) {
594 /* By using ns8250_init() we also set DTR and RTS. */
595 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
597 mcr |= MCR_DTR | MCR_RTS;
599 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
604 * Set loopback mode. This avoids having garbage on the wire and
605 * also allows us send and receive data. We set DTR and RTS to
606 * avoid the possibility that automatic flow-control prevents
607 * any data from being sent.
609 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
613 * Enable FIFOs. And check that the UART has them. If not, we're
614 * done. Since this is the first time we enable the FIFOs, we reset
617 uart_setreg(bas, REG_FCR, FCR_ENABLE);
619 sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0;
620 if (!sc->sc_hasfifo) {
622 * NS16450 or INS8250. We don't bother to differentiate
623 * between them. They're too old to be interesting.
625 uart_setreg(bas, REG_MCR, mcr);
627 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
631 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
635 delay = ns8250_delay(bas);
637 /* We have FIFOs. Drain the transmitter and receiver. */
638 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
640 uart_setreg(bas, REG_MCR, mcr);
641 uart_setreg(bas, REG_FCR, 0);
647 * We should have a sufficiently clean "pipe" to determine the
648 * size of the FIFOs. We send as much characters as is reasonable
649 * and wait for the the overflow bit in the LSR register to be
650 * asserted, counting the characters as we send them. Based on
651 * that count we know the FIFO size.
654 uart_setreg(bas, REG_DATA, 0);
661 * LSR bits are cleared upon read, so we must accumulate
662 * them to be able to test LSR_OE below.
664 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
668 ier = uart_getreg(bas, REG_IER) & 0xf0;
669 uart_setreg(bas, REG_IER, ier);
670 uart_setreg(bas, REG_MCR, mcr);
671 uart_setreg(bas, REG_FCR, 0);
676 } while ((lsr & LSR_OE) == 0 && count < 130);
679 uart_setreg(bas, REG_MCR, mcr);
682 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
685 if (count >= 14 && count <= 16) {
686 sc->sc_rxfifosz = 16;
687 device_set_desc(sc->sc_dev, "16550 or compatible");
688 } else if (count >= 28 && count <= 32) {
689 sc->sc_rxfifosz = 32;
690 device_set_desc(sc->sc_dev, "16650 or compatible");
691 } else if (count >= 56 && count <= 64) {
692 sc->sc_rxfifosz = 64;
693 device_set_desc(sc->sc_dev, "16750 or compatible");
694 } else if (count >= 112 && count <= 128) {
695 sc->sc_rxfifosz = 128;
696 device_set_desc(sc->sc_dev, "16950 or compatible");
698 sc->sc_rxfifosz = 16;
699 device_set_desc(sc->sc_dev,
700 "Non-standard ns8250 class UART with FIFOs");
704 * Force the Tx FIFO size to 16 bytes for now. We don't program the
705 * Tx trigger. Also, we assume that all data has been sent when the
708 sc->sc_txfifosz = 16;
712 * XXX there are some issues related to hardware flow control and
713 * it's likely that uart(4) is the cause. This basicly needs more
714 * investigation, but we avoid using for hardware flow control
717 /* 16650s or higher have automatic flow control. */
718 if (sc->sc_rxfifosz > 16) {
728 ns8250_bus_receive(struct uart_softc *sc)
730 struct uart_bas *bas;
735 mtx_lock_spin(&sc->sc_hwmtx);
736 lsr = uart_getreg(bas, REG_LSR);
737 while (lsr & LSR_RXRDY) {
738 if (uart_rx_full(sc)) {
739 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
742 xc = uart_getreg(bas, REG_DATA);
744 xc |= UART_STAT_FRAMERR;
746 xc |= UART_STAT_PARERR;
748 lsr = uart_getreg(bas, REG_LSR);
750 /* Discard everything left in the Rx FIFO. */
751 while (lsr & LSR_RXRDY) {
752 (void)uart_getreg(bas, REG_DATA);
754 lsr = uart_getreg(bas, REG_LSR);
756 mtx_unlock_spin(&sc->sc_hwmtx);
761 ns8250_bus_setsig(struct uart_softc *sc, int sig)
763 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
764 struct uart_bas *bas;
771 if (sig & SER_DDTR) {
772 SIGCHG(sig & SER_DTR, new, SER_DTR,
775 if (sig & SER_DRTS) {
776 SIGCHG(sig & SER_RTS, new, SER_RTS,
779 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
780 mtx_lock_spin(&sc->sc_hwmtx);
781 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
783 ns8250->mcr |= MCR_DTR;
785 ns8250->mcr |= MCR_RTS;
786 uart_setreg(bas, REG_MCR, ns8250->mcr);
788 mtx_unlock_spin(&sc->sc_hwmtx);
793 ns8250_bus_transmit(struct uart_softc *sc)
795 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
796 struct uart_bas *bas;
800 mtx_lock_spin(&sc->sc_hwmtx);
801 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
803 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
805 for (i = 0; i < sc->sc_txdatasz; i++) {
806 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
810 mtx_unlock_spin(&sc->sc_hwmtx);