2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
48 #include <dev/uart/uart_bus.h>
49 #include <dev/uart/uart_dev_ns8250.h>
51 #include <dev/ic/ns16550.h>
55 #define DEFAULT_RCLK 1843200
57 static int broken_txfifo = 0;
58 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
62 * Clear pending interrupts. THRE is cleared by reading IIR. Data
63 * that may have been received gets lost here.
66 ns8250_clrint(struct uart_bas *bas)
70 iir = uart_getreg(bas, REG_IIR);
71 while ((iir & IIR_NOPEND) == 0) {
74 lsr = uart_getreg(bas, REG_LSR);
75 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
76 (void)uart_getreg(bas, REG_DATA);
77 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
78 (void)uart_getreg(bas, REG_DATA);
79 else if (iir == IIR_MLSC)
80 (void)uart_getreg(bas, REG_MSR);
82 iir = uart_getreg(bas, REG_IIR);
87 ns8250_delay(struct uart_bas *bas)
92 lcr = uart_getreg(bas, REG_LCR);
93 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
95 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
97 uart_setreg(bas, REG_LCR, lcr);
100 /* 1/10th the time to transmit 1 character (estimate). */
102 return (16000000 * divisor / bas->rclk);
103 return (16000 * divisor / (bas->rclk / 1000));
107 ns8250_divisor(int rclk, int baudrate)
109 int actual_baud, divisor;
115 divisor = (rclk / (baudrate << 3) + 1) >> 1;
116 if (divisor == 0 || divisor >= 65536)
118 actual_baud = rclk / (divisor << 4);
120 /* 10 times error in percent: */
121 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
123 /* 3.0% maximum error tolerance: */
124 if (error < -30 || error > 30)
131 ns8250_drain(struct uart_bas *bas, int what)
135 delay = ns8250_delay(bas);
137 if (what & UART_DRAIN_TRANSMITTER) {
139 * Pick an arbitrary high limit to avoid getting stuck in
140 * an infinite loop when the hardware is broken. Make the
141 * limit high enough to handle large FIFOs.
144 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
147 /* printf("ns8250: transmitter appears stuck... "); */
152 if (what & UART_DRAIN_RECEIVER) {
154 * Pick an arbitrary high limit to avoid getting stuck in
155 * an infinite loop when the hardware is broken. Make the
156 * limit high enough to handle large FIFOs and integrated
157 * UARTs. The HP rx2600 for example has 3 UARTs on the
158 * management board that tend to get a lot of data send
159 * to it when the UART is first activated.
162 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
163 (void)uart_getreg(bas, REG_DATA);
168 /* printf("ns8250: receiver appears broken... "); */
177 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
178 * drained. WARNING: this function clobbers the FIFO setting!
181 ns8250_flush(struct uart_bas *bas, int what)
186 if (what & UART_FLUSH_TRANSMITTER)
188 if (what & UART_FLUSH_RECEIVER)
190 uart_setreg(bas, REG_FCR, fcr);
195 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
204 else if (databits == 7)
206 else if (databits == 6)
216 divisor = ns8250_divisor(bas->rclk, baudrate);
219 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
221 uart_setreg(bas, REG_DLL, divisor & 0xff);
222 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
226 /* Set LCR and clear DLAB. */
227 uart_setreg(bas, REG_LCR, lcr);
233 * Low-level UART interface.
235 static int ns8250_probe(struct uart_bas *bas);
236 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
237 static void ns8250_term(struct uart_bas *bas);
238 static void ns8250_putc(struct uart_bas *bas, int);
239 static int ns8250_rxready(struct uart_bas *bas);
240 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
242 struct uart_ops uart_ns8250_ops = {
243 .probe = ns8250_probe,
247 .rxready = ns8250_rxready,
252 ns8250_probe(struct uart_bas *bas)
256 /* Check known 0 bits that don't depend on DLAB. */
257 val = uart_getreg(bas, REG_IIR);
261 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
262 * chip, but otherwise doesn't seem to have a function. In
263 * other words, uart(4) works regardless. Ignore that bit so
264 * the probe succeeds.
266 val = uart_getreg(bas, REG_MCR);
274 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
280 bas->rclk = DEFAULT_RCLK;
281 ns8250_param(bas, baudrate, databits, stopbits, parity);
283 /* Disable all interrupt sources. */
285 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
286 * UARTs split the receive time-out interrupt bit out separately as
287 * 0x10. This gets handled by ier_mask and ier_rxbits below.
289 ier = uart_getreg(bas, REG_IER) & 0xe0;
290 uart_setreg(bas, REG_IER, ier);
293 /* Disable the FIFO (if present). */
294 uart_setreg(bas, REG_FCR, 0);
298 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
305 ns8250_term(struct uart_bas *bas)
308 /* Clear RTS & DTR. */
309 uart_setreg(bas, REG_MCR, MCR_IE);
314 ns8250_putc(struct uart_bas *bas, int c)
319 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
321 uart_setreg(bas, REG_DATA, c);
324 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
329 ns8250_rxready(struct uart_bas *bas)
332 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
336 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
342 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
348 c = uart_getreg(bas, REG_DATA);
355 static kobj_method_t ns8250_methods[] = {
356 KOBJMETHOD(uart_attach, ns8250_bus_attach),
357 KOBJMETHOD(uart_detach, ns8250_bus_detach),
358 KOBJMETHOD(uart_flush, ns8250_bus_flush),
359 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
360 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
361 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
362 KOBJMETHOD(uart_param, ns8250_bus_param),
363 KOBJMETHOD(uart_probe, ns8250_bus_probe),
364 KOBJMETHOD(uart_receive, ns8250_bus_receive),
365 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
366 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
367 KOBJMETHOD(uart_grab, ns8250_bus_grab),
368 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
372 struct uart_class uart_ns8250_class = {
375 sizeof(struct ns8250_softc),
376 .uc_ops = &uart_ns8250_ops,
378 .uc_rclk = DEFAULT_RCLK
381 #define SIGCHG(c, i, s, d) \
383 i |= (i & s) ? s : s | d; \
385 i = (i & s) ? (i & ~s) | d : i; \
389 ns8250_bus_attach(struct uart_softc *sc)
391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
392 struct uart_bas *bas;
399 ns8250->busy_detect = 0;
403 * Check whether uart requires to read USR reg when IIR_BUSY and
406 node = ofw_bus_get_node(sc->sc_dev);
407 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
408 ns8250->busy_detect = 1;
409 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
415 ns8250->mcr = uart_getreg(bas, REG_MCR);
416 ns8250->fcr = FCR_ENABLE;
417 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
419 if (UART_FLAGS_FCR_RX_LOW(ivar))
420 ns8250->fcr |= FCR_RX_LOW;
421 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
422 ns8250->fcr |= FCR_RX_MEDL;
423 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
424 ns8250->fcr |= FCR_RX_HIGH;
426 ns8250->fcr |= FCR_RX_MEDH;
428 ns8250->fcr |= FCR_RX_MEDH;
432 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
434 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
436 /* Get IER RX interrupt bits */
437 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
438 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
440 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
442 uart_setreg(bas, REG_FCR, ns8250->fcr);
444 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
446 if (ns8250->mcr & MCR_DTR)
447 sc->sc_hwsig |= SER_DTR;
448 if (ns8250->mcr & MCR_RTS)
449 sc->sc_hwsig |= SER_RTS;
450 ns8250_bus_getsig(sc);
453 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
454 ns8250->ier |= ns8250->ier_rxbits;
455 uart_setreg(bas, REG_IER, ns8250->ier);
459 * Timing of the H/W access was changed with r253161 of uart_core.c
460 * It has been observed that an ITE IT8513E would signal a break
461 * condition with pretty much every character it received, unless
462 * it had enough time to settle between ns8250_bus_attach() and
463 * ns8250_bus_ipend() -- which it accidentally had before r253161.
464 * It's not understood why the UART chip behaves this way and it
465 * could very well be that the DELAY make the H/W work in the same
466 * accidental manner as before. More analysis is warranted, but
467 * at least now we fixed a known regression.
474 ns8250_bus_detach(struct uart_softc *sc)
476 struct ns8250_softc *ns8250;
477 struct uart_bas *bas;
480 ns8250 = (struct ns8250_softc *)sc;
482 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
483 uart_setreg(bas, REG_IER, ier);
490 ns8250_bus_flush(struct uart_softc *sc, int what)
492 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
493 struct uart_bas *bas;
497 uart_lock(sc->sc_hwmtx);
498 if (sc->sc_rxfifosz > 1) {
499 ns8250_flush(bas, what);
500 uart_setreg(bas, REG_FCR, ns8250->fcr);
504 error = ns8250_drain(bas, what);
505 uart_unlock(sc->sc_hwmtx);
510 ns8250_bus_getsig(struct uart_softc *sc)
512 uint32_t new, old, sig;
518 uart_lock(sc->sc_hwmtx);
519 msr = uart_getreg(&sc->sc_bas, REG_MSR);
520 uart_unlock(sc->sc_hwmtx);
521 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
522 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
523 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
524 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
525 new = sig & ~SER_MASK_DELTA;
526 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
531 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
533 struct uart_bas *bas;
534 int baudrate, divisor, error;
539 uart_lock(sc->sc_hwmtx);
541 case UART_IOCTL_BREAK:
542 lcr = uart_getreg(bas, REG_LCR);
547 uart_setreg(bas, REG_LCR, lcr);
550 case UART_IOCTL_IFLOW:
551 lcr = uart_getreg(bas, REG_LCR);
553 uart_setreg(bas, REG_LCR, 0xbf);
555 efr = uart_getreg(bas, REG_EFR);
560 uart_setreg(bas, REG_EFR, efr);
562 uart_setreg(bas, REG_LCR, lcr);
565 case UART_IOCTL_OFLOW:
566 lcr = uart_getreg(bas, REG_LCR);
568 uart_setreg(bas, REG_LCR, 0xbf);
570 efr = uart_getreg(bas, REG_EFR);
575 uart_setreg(bas, REG_EFR, efr);
577 uart_setreg(bas, REG_LCR, lcr);
580 case UART_IOCTL_BAUD:
581 lcr = uart_getreg(bas, REG_LCR);
582 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
584 divisor = uart_getreg(bas, REG_DLL) |
585 (uart_getreg(bas, REG_DLH) << 8);
587 uart_setreg(bas, REG_LCR, lcr);
589 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
591 *(int*)data = baudrate;
599 uart_unlock(sc->sc_hwmtx);
604 ns8250_bus_ipend(struct uart_softc *sc)
606 struct uart_bas *bas;
607 struct ns8250_softc *ns8250;
611 ns8250 = (struct ns8250_softc *)sc;
613 uart_lock(sc->sc_hwmtx);
614 iir = uart_getreg(bas, REG_IIR);
616 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
617 (void)uart_getreg(bas, DW_REG_USR);
618 uart_unlock(sc->sc_hwmtx);
621 if (iir & IIR_NOPEND) {
622 uart_unlock(sc->sc_hwmtx);
626 if (iir & IIR_RXRDY) {
627 lsr = uart_getreg(bas, REG_LSR);
629 ipend |= SER_INT_OVERRUN;
631 ipend |= SER_INT_BREAK;
633 ipend |= SER_INT_RXREADY;
635 if (iir & IIR_TXRDY) {
636 ipend |= SER_INT_TXIDLE;
637 uart_setreg(bas, REG_IER, ns8250->ier);
639 ipend |= SER_INT_SIGCHG;
643 uart_unlock(sc->sc_hwmtx);
648 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
649 int stopbits, int parity)
651 struct ns8250_softc *ns8250;
652 struct uart_bas *bas;
655 ns8250 = (struct ns8250_softc*)sc;
657 uart_lock(sc->sc_hwmtx);
659 * When using DW UART with BUSY detection it is necessary to wait
660 * until all serial transfers are finished before manipulating the
661 * line control. LCR will not be affected when UART is busy.
663 if (ns8250->busy_detect != 0) {
665 * Pick an arbitrary high limit to avoid getting stuck in
666 * an infinite loop in case when the hardware is broken.
669 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
674 /* UART appears to be stuck */
675 uart_unlock(sc->sc_hwmtx);
680 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
681 uart_unlock(sc->sc_hwmtx);
686 ns8250_bus_probe(struct uart_softc *sc)
688 struct ns8250_softc *ns8250;
689 struct uart_bas *bas;
690 int count, delay, error, limit;
691 uint8_t lsr, mcr, ier;
693 ns8250 = (struct ns8250_softc *)sc;
696 error = ns8250_probe(bas);
701 if (sc->sc_sysdev == NULL) {
702 /* By using ns8250_init() we also set DTR and RTS. */
703 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
705 mcr |= MCR_DTR | MCR_RTS;
707 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
712 * Set loopback mode. This avoids having garbage on the wire and
713 * also allows us send and receive data. We set DTR and RTS to
714 * avoid the possibility that automatic flow-control prevents
715 * any data from being sent.
717 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
721 * Enable FIFOs. And check that the UART has them. If not, we're
722 * done. Since this is the first time we enable the FIFOs, we reset
725 uart_setreg(bas, REG_FCR, FCR_ENABLE);
727 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
729 * NS16450 or INS8250. We don't bother to differentiate
730 * between them. They're too old to be interesting.
732 uart_setreg(bas, REG_MCR, mcr);
734 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
735 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
739 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
743 delay = ns8250_delay(bas);
745 /* We have FIFOs. Drain the transmitter and receiver. */
746 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
748 uart_setreg(bas, REG_MCR, mcr);
749 uart_setreg(bas, REG_FCR, 0);
755 * We should have a sufficiently clean "pipe" to determine the
756 * size of the FIFOs. We send as much characters as is reasonable
757 * and wait for the overflow bit in the LSR register to be
758 * asserted, counting the characters as we send them. Based on
759 * that count we know the FIFO size.
762 uart_setreg(bas, REG_DATA, 0);
769 * LSR bits are cleared upon read, so we must accumulate
770 * them to be able to test LSR_OE below.
772 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
776 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
777 uart_setreg(bas, REG_IER, ier);
778 uart_setreg(bas, REG_MCR, mcr);
779 uart_setreg(bas, REG_FCR, 0);
784 } while ((lsr & LSR_OE) == 0 && count < 130);
787 uart_setreg(bas, REG_MCR, mcr);
790 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
793 if (count >= 14 && count <= 16) {
794 sc->sc_rxfifosz = 16;
795 device_set_desc(sc->sc_dev, "16550 or compatible");
796 } else if (count >= 28 && count <= 32) {
797 sc->sc_rxfifosz = 32;
798 device_set_desc(sc->sc_dev, "16650 or compatible");
799 } else if (count >= 56 && count <= 64) {
800 sc->sc_rxfifosz = 64;
801 device_set_desc(sc->sc_dev, "16750 or compatible");
802 } else if (count >= 112 && count <= 128) {
803 sc->sc_rxfifosz = 128;
804 device_set_desc(sc->sc_dev, "16950 or compatible");
806 sc->sc_rxfifosz = 16;
807 device_set_desc(sc->sc_dev,
808 "Non-standard ns8250 class UART with FIFOs");
812 * Force the Tx FIFO size to 16 bytes for now. We don't program the
813 * Tx trigger. Also, we assume that all data has been sent when the
816 sc->sc_txfifosz = 16;
820 * XXX there are some issues related to hardware flow control and
821 * it's likely that uart(4) is the cause. This basicly needs more
822 * investigation, but we avoid using for hardware flow control
825 /* 16650s or higher have automatic flow control. */
826 if (sc->sc_rxfifosz > 16) {
836 ns8250_bus_receive(struct uart_softc *sc)
838 struct uart_bas *bas;
843 uart_lock(sc->sc_hwmtx);
844 lsr = uart_getreg(bas, REG_LSR);
845 while (lsr & LSR_RXRDY) {
846 if (uart_rx_full(sc)) {
847 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
850 xc = uart_getreg(bas, REG_DATA);
852 xc |= UART_STAT_FRAMERR;
854 xc |= UART_STAT_PARERR;
856 lsr = uart_getreg(bas, REG_LSR);
858 /* Discard everything left in the Rx FIFO. */
859 while (lsr & LSR_RXRDY) {
860 (void)uart_getreg(bas, REG_DATA);
862 lsr = uart_getreg(bas, REG_LSR);
864 uart_unlock(sc->sc_hwmtx);
869 ns8250_bus_setsig(struct uart_softc *sc, int sig)
871 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
872 struct uart_bas *bas;
879 if (sig & SER_DDTR) {
880 SIGCHG(sig & SER_DTR, new, SER_DTR,
883 if (sig & SER_DRTS) {
884 SIGCHG(sig & SER_RTS, new, SER_RTS,
887 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
888 uart_lock(sc->sc_hwmtx);
889 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
891 ns8250->mcr |= MCR_DTR;
893 ns8250->mcr |= MCR_RTS;
894 uart_setreg(bas, REG_MCR, ns8250->mcr);
896 uart_unlock(sc->sc_hwmtx);
901 ns8250_bus_transmit(struct uart_softc *sc)
903 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
904 struct uart_bas *bas;
908 uart_lock(sc->sc_hwmtx);
909 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
911 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
913 for (i = 0; i < sc->sc_txdatasz; i++) {
914 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
918 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
921 uart_unlock(sc->sc_hwmtx);
923 uart_sched_softih(sc, SER_INT_TXIDLE);
928 ns8250_bus_grab(struct uart_softc *sc)
930 struct uart_bas *bas = &sc->sc_bas;
931 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
935 * turn off all interrupts to enter polling mode. Leave the
936 * saved mask alone. We'll restore whatever it was in ungrab.
937 * All pending interupt signals are reset when IER is set to 0.
939 uart_lock(sc->sc_hwmtx);
940 ier = uart_getreg(bas, REG_IER);
941 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
943 uart_unlock(sc->sc_hwmtx);
947 ns8250_bus_ungrab(struct uart_softc *sc)
949 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
950 struct uart_bas *bas = &sc->sc_bas;
953 * Restore previous interrupt mask
955 uart_lock(sc->sc_hwmtx);
956 uart_setreg(bas, REG_IER, ns8250->ier);
958 uart_unlock(sc->sc_hwmtx);