2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include "opt_platform.h"
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/sysctl.h>
41 #include <machine/bus.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/uart/uart.h>
50 #include <dev/uart/uart_cpu.h>
52 #include <dev/uart/uart_cpu_fdt.h>
54 #include <dev/uart/uart_bus.h>
55 #include <dev/uart/uart_dev_ns8250.h>
56 #include <dev/uart/uart_ppstypes.h>
58 #include <dev/ic/ns16550.h>
62 #define DEFAULT_RCLK 1843200
65 * Set the default baudrate tolerance to 3.0%.
67 * Some embedded boards have odd reference clocks (eg 25MHz)
68 * and we need to handle higher variances in the target baud rate.
70 #ifndef UART_DEV_TOLERANCE_PCT
71 #define UART_DEV_TOLERANCE_PCT 30
72 #endif /* UART_DEV_TOLERANCE_PCT */
74 static int broken_txfifo = 0;
75 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
76 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79 * Clear pending interrupts. THRE is cleared by reading IIR. Data
80 * that may have been received gets lost here.
83 ns8250_clrint(struct uart_bas *bas)
87 iir = uart_getreg(bas, REG_IIR);
88 while ((iir & IIR_NOPEND) == 0) {
91 lsr = uart_getreg(bas, REG_LSR);
92 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
93 (void)uart_getreg(bas, REG_DATA);
94 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
95 (void)uart_getreg(bas, REG_DATA);
96 else if (iir == IIR_MLSC)
97 (void)uart_getreg(bas, REG_MSR);
99 iir = uart_getreg(bas, REG_IIR);
104 ns8250_delay(struct uart_bas *bas)
109 lcr = uart_getreg(bas, REG_LCR);
110 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
112 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
114 uart_setreg(bas, REG_LCR, lcr);
117 /* 1/10th the time to transmit 1 character (estimate). */
119 return (16000000 * divisor / bas->rclk);
120 return (16000 * divisor / (bas->rclk / 1000));
124 ns8250_divisor(int rclk, int baudrate)
126 int actual_baud, divisor;
132 divisor = (rclk / (baudrate << 3) + 1) >> 1;
133 if (divisor == 0 || divisor >= 65536)
135 actual_baud = rclk / (divisor << 4);
137 /* 10 times error in percent: */
138 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
140 /* enforce maximum error tolerance: */
141 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
148 ns8250_drain(struct uart_bas *bas, int what)
152 delay = ns8250_delay(bas);
154 if (what & UART_DRAIN_TRANSMITTER) {
156 * Pick an arbitrary high limit to avoid getting stuck in
157 * an infinite loop when the hardware is broken. Make the
158 * limit high enough to handle large FIFOs.
161 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
164 /* printf("ns8250: transmitter appears stuck... "); */
169 if (what & UART_DRAIN_RECEIVER) {
171 * Pick an arbitrary high limit to avoid getting stuck in
172 * an infinite loop when the hardware is broken. Make the
173 * limit high enough to handle large FIFOs and integrated
174 * UARTs. The HP rx2600 for example has 3 UARTs on the
175 * management board that tend to get a lot of data send
176 * to it when the UART is first activated.
179 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
180 (void)uart_getreg(bas, REG_DATA);
185 /* printf("ns8250: receiver appears broken... "); */
194 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
195 * drained. WARNING: this function clobbers the FIFO setting!
198 ns8250_flush(struct uart_bas *bas, int what)
206 if (what & UART_FLUSH_TRANSMITTER)
208 if (what & UART_FLUSH_RECEIVER)
210 uart_setreg(bas, REG_FCR, fcr);
215 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
224 else if (databits == 7)
226 else if (databits == 6)
236 divisor = ns8250_divisor(bas->rclk, baudrate);
239 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
241 uart_setreg(bas, REG_DLL, divisor & 0xff);
242 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
246 /* Set LCR and clear DLAB. */
247 uart_setreg(bas, REG_LCR, lcr);
253 * Low-level UART interface.
255 static int ns8250_probe(struct uart_bas *bas);
256 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
257 static void ns8250_term(struct uart_bas *bas);
258 static void ns8250_putc(struct uart_bas *bas, int);
259 static int ns8250_rxready(struct uart_bas *bas);
260 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
262 struct uart_ops uart_ns8250_ops = {
263 .probe = ns8250_probe,
267 .rxready = ns8250_rxready,
272 ns8250_probe(struct uart_bas *bas)
277 uart_setreg(bas, REG_FCR, FCR_UART_ON);
280 /* Check known 0 bits that don't depend on DLAB. */
281 val = uart_getreg(bas, REG_IIR);
285 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
286 * chip, but otherwise doesn't seem to have a function. In
287 * other words, uart(4) works regardless. Ignore that bit so
288 * the probe succeeds.
290 val = uart_getreg(bas, REG_MCR);
298 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
304 bas->rclk = DEFAULT_RCLK;
305 ns8250_param(bas, baudrate, databits, stopbits, parity);
307 /* Disable all interrupt sources. */
309 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
310 * UARTs split the receive time-out interrupt bit out separately as
311 * 0x10. This gets handled by ier_mask and ier_rxbits below.
313 ier = uart_getreg(bas, REG_IER) & 0xe0;
314 uart_setreg(bas, REG_IER, ier);
317 /* Disable the FIFO (if present). */
322 uart_setreg(bas, REG_FCR, val);
326 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
333 ns8250_term(struct uart_bas *bas)
336 /* Clear RTS & DTR. */
337 uart_setreg(bas, REG_MCR, MCR_IE);
342 ns8250_putc(struct uart_bas *bas, int c)
347 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
349 uart_setreg(bas, REG_DATA, c);
354 ns8250_rxready(struct uart_bas *bas)
357 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
361 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
373 c = uart_getreg(bas, REG_DATA);
380 static kobj_method_t ns8250_methods[] = {
381 KOBJMETHOD(uart_attach, ns8250_bus_attach),
382 KOBJMETHOD(uart_detach, ns8250_bus_detach),
383 KOBJMETHOD(uart_flush, ns8250_bus_flush),
384 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
385 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
386 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
387 KOBJMETHOD(uart_param, ns8250_bus_param),
388 KOBJMETHOD(uart_probe, ns8250_bus_probe),
389 KOBJMETHOD(uart_receive, ns8250_bus_receive),
390 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
391 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
392 KOBJMETHOD(uart_grab, ns8250_bus_grab),
393 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
397 struct uart_class uart_ns8250_class = {
400 sizeof(struct ns8250_softc),
401 .uc_ops = &uart_ns8250_ops,
403 .uc_rclk = DEFAULT_RCLK,
408 static struct ofw_compat_data compat_data[] = {
409 {"ns16550", (uintptr_t)&uart_ns8250_class},
410 {"ns16550a", (uintptr_t)&uart_ns8250_class},
411 {NULL, (uintptr_t)NULL},
413 UART_FDT_CLASS_AND_DEVICE(compat_data);
416 /* Use token-pasting to form SER_ and MSR_ named constants. */
417 #define SER(sig) SER_##sig
418 #define SERD(sig) SER_D##sig
419 #define MSR(sig) MSR_##sig
420 #define MSRD(sig) MSR_D##sig
423 * Detect signal changes using software delta detection. The previous state of
424 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
425 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
426 * new state of both the signal and the delta bits.
428 #define SIGCHGSW(var, msr, sig) \
429 if ((msr) & MSR(sig)) { \
430 if ((var & SER(sig)) == 0) \
431 var |= SERD(sig) | SER(sig); \
433 if ((var & SER(sig)) != 0) \
434 var = SERD(sig) | (var & ~SER(sig)); \
438 * Detect signal changes using the hardware msr delta bits. This is currently
439 * used only when PPS timing information is being captured using the "narrow
440 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
441 * by time the interrupt handler is invoked. The hardware will latch the fact
442 * that it changed in the delta bits.
444 #define SIGCHGHW(var, msr, sig) \
445 if ((msr) & MSRD(sig)) { \
446 if (((msr) & MSR(sig)) != 0) \
447 var |= SERD(sig) | SER(sig); \
449 var = SERD(sig) | (var & ~SER(sig)); \
453 ns8250_bus_attach(struct uart_softc *sc)
455 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
456 struct uart_bas *bas;
464 /* Check whether uart has a broken txfifo. */
465 node = ofw_bus_get_node(sc->sc_dev);
466 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
467 broken_txfifo = cell ? 1 : 0;
472 ns8250->busy_detect = bas->busy_detect;
473 ns8250->mcr = uart_getreg(bas, REG_MCR);
474 ns8250->fcr = FCR_ENABLE;
476 ns8250->fcr |= FCR_UART_ON;
478 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
480 if (UART_FLAGS_FCR_RX_LOW(ivar))
481 ns8250->fcr |= FCR_RX_LOW;
482 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
483 ns8250->fcr |= FCR_RX_MEDL;
484 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
485 ns8250->fcr |= FCR_RX_HIGH;
487 ns8250->fcr |= FCR_RX_MEDH;
489 ns8250->fcr |= FCR_RX_MEDH;
493 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
495 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
497 /* Get IER RX interrupt bits */
498 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
499 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
501 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
503 uart_setreg(bas, REG_FCR, ns8250->fcr);
505 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
507 if (ns8250->mcr & MCR_DTR)
508 sc->sc_hwsig |= SER_DTR;
509 if (ns8250->mcr & MCR_RTS)
510 sc->sc_hwsig |= SER_RTS;
511 ns8250_bus_getsig(sc);
514 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
515 ns8250->ier |= ns8250->ier_rxbits;
516 uart_setreg(bas, REG_IER, ns8250->ier);
520 * Timing of the H/W access was changed with r253161 of uart_core.c
521 * It has been observed that an ITE IT8513E would signal a break
522 * condition with pretty much every character it received, unless
523 * it had enough time to settle between ns8250_bus_attach() and
524 * ns8250_bus_ipend() -- which it accidentally had before r253161.
525 * It's not understood why the UART chip behaves this way and it
526 * could very well be that the DELAY make the H/W work in the same
527 * accidental manner as before. More analysis is warranted, but
528 * at least now we fixed a known regression.
535 ns8250_bus_detach(struct uart_softc *sc)
537 struct ns8250_softc *ns8250;
538 struct uart_bas *bas;
541 ns8250 = (struct ns8250_softc *)sc;
543 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
544 uart_setreg(bas, REG_IER, ier);
551 ns8250_bus_flush(struct uart_softc *sc, int what)
553 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
554 struct uart_bas *bas;
558 uart_lock(sc->sc_hwmtx);
559 if (sc->sc_rxfifosz > 1) {
560 ns8250_flush(bas, what);
561 uart_setreg(bas, REG_FCR, ns8250->fcr);
565 error = ns8250_drain(bas, what);
566 uart_unlock(sc->sc_hwmtx);
571 ns8250_bus_getsig(struct uart_softc *sc)
577 * The delta bits are reputed to be broken on some hardware, so use
578 * software delta detection by default. Use the hardware delta bits
579 * when capturing PPS pulses which are too narrow for software detection
580 * to see the edges. Hardware delta for RI doesn't work like the
581 * others, so always use software for it. Other threads may be changing
582 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
583 * update without other changes happening. Note that the SIGCHGxx()
584 * macros carefully preserve the delta bits when we have to loop several
585 * times and a signal transitions between iterations.
590 uart_lock(sc->sc_hwmtx);
591 msr = uart_getreg(&sc->sc_bas, REG_MSR);
592 uart_unlock(sc->sc_hwmtx);
593 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
594 SIGCHGHW(sig, msr, DSR);
595 SIGCHGHW(sig, msr, CTS);
596 SIGCHGHW(sig, msr, DCD);
598 SIGCHGSW(sig, msr, DSR);
599 SIGCHGSW(sig, msr, CTS);
600 SIGCHGSW(sig, msr, DCD);
602 SIGCHGSW(sig, msr, RI);
603 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
608 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
610 struct uart_bas *bas;
611 int baudrate, divisor, error;
616 uart_lock(sc->sc_hwmtx);
618 case UART_IOCTL_BREAK:
619 lcr = uart_getreg(bas, REG_LCR);
624 uart_setreg(bas, REG_LCR, lcr);
627 case UART_IOCTL_IFLOW:
628 lcr = uart_getreg(bas, REG_LCR);
630 uart_setreg(bas, REG_LCR, 0xbf);
632 efr = uart_getreg(bas, REG_EFR);
637 uart_setreg(bas, REG_EFR, efr);
639 uart_setreg(bas, REG_LCR, lcr);
642 case UART_IOCTL_OFLOW:
643 lcr = uart_getreg(bas, REG_LCR);
645 uart_setreg(bas, REG_LCR, 0xbf);
647 efr = uart_getreg(bas, REG_EFR);
652 uart_setreg(bas, REG_EFR, efr);
654 uart_setreg(bas, REG_LCR, lcr);
657 case UART_IOCTL_BAUD:
658 lcr = uart_getreg(bas, REG_LCR);
659 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
661 divisor = uart_getreg(bas, REG_DLL) |
662 (uart_getreg(bas, REG_DLH) << 8);
664 uart_setreg(bas, REG_LCR, lcr);
666 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
668 *(int*)data = baudrate;
676 uart_unlock(sc->sc_hwmtx);
681 ns8250_bus_ipend(struct uart_softc *sc)
683 struct uart_bas *bas;
684 struct ns8250_softc *ns8250;
688 ns8250 = (struct ns8250_softc *)sc;
690 uart_lock(sc->sc_hwmtx);
691 iir = uart_getreg(bas, REG_IIR);
693 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
694 (void)uart_getreg(bas, DW_REG_USR);
695 uart_unlock(sc->sc_hwmtx);
698 if (iir & IIR_NOPEND) {
699 uart_unlock(sc->sc_hwmtx);
703 if (iir & IIR_RXRDY) {
704 lsr = uart_getreg(bas, REG_LSR);
706 ipend |= SER_INT_OVERRUN;
708 ipend |= SER_INT_BREAK;
710 ipend |= SER_INT_RXREADY;
712 if (iir & IIR_TXRDY) {
713 ipend |= SER_INT_TXIDLE;
714 uart_setreg(bas, REG_IER, ns8250->ier);
717 ipend |= SER_INT_SIGCHG;
721 uart_unlock(sc->sc_hwmtx);
726 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
727 int stopbits, int parity)
729 struct ns8250_softc *ns8250;
730 struct uart_bas *bas;
733 ns8250 = (struct ns8250_softc*)sc;
735 uart_lock(sc->sc_hwmtx);
737 * When using DW UART with BUSY detection it is necessary to wait
738 * until all serial transfers are finished before manipulating the
739 * line control. LCR will not be affected when UART is busy.
741 if (ns8250->busy_detect != 0) {
743 * Pick an arbitrary high limit to avoid getting stuck in
744 * an infinite loop in case when the hardware is broken.
747 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
752 /* UART appears to be stuck */
753 uart_unlock(sc->sc_hwmtx);
758 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
759 uart_unlock(sc->sc_hwmtx);
764 ns8250_bus_probe(struct uart_softc *sc)
766 struct ns8250_softc *ns8250;
767 struct uart_bas *bas;
768 int count, delay, error, limit;
769 uint8_t lsr, mcr, ier;
772 ns8250 = (struct ns8250_softc *)sc;
775 error = ns8250_probe(bas);
780 if (sc->sc_sysdev == NULL) {
781 /* By using ns8250_init() we also set DTR and RTS. */
782 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
784 mcr |= MCR_DTR | MCR_RTS;
786 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
791 * Set loopback mode. This avoids having garbage on the wire and
792 * also allows us send and receive data. We set DTR and RTS to
793 * avoid the possibility that automatic flow-control prevents
794 * any data from being sent.
796 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
800 * Enable FIFOs. And check that the UART has them. If not, we're
801 * done. Since this is the first time we enable the FIFOs, we reset
808 uart_setreg(bas, REG_FCR, val);
810 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
812 * NS16450 or INS8250. We don't bother to differentiate
813 * between them. They're too old to be interesting.
815 uart_setreg(bas, REG_MCR, mcr);
817 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
818 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
822 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
826 uart_setreg(bas, REG_FCR, val);
830 delay = ns8250_delay(bas);
832 /* We have FIFOs. Drain the transmitter and receiver. */
833 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
835 uart_setreg(bas, REG_MCR, mcr);
840 uart_setreg(bas, REG_FCR, val);
846 * We should have a sufficiently clean "pipe" to determine the
847 * size of the FIFOs. We send as much characters as is reasonable
848 * and wait for the overflow bit in the LSR register to be
849 * asserted, counting the characters as we send them. Based on
850 * that count we know the FIFO size.
853 uart_setreg(bas, REG_DATA, 0);
860 * LSR bits are cleared upon read, so we must accumulate
861 * them to be able to test LSR_OE below.
863 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
867 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
868 uart_setreg(bas, REG_IER, ier);
869 uart_setreg(bas, REG_MCR, mcr);
874 uart_setreg(bas, REG_FCR, val);
879 } while ((lsr & LSR_OE) == 0 && count < 260);
882 uart_setreg(bas, REG_MCR, mcr);
885 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
888 if (count >= 14 && count <= 16) {
889 sc->sc_rxfifosz = 16;
890 device_set_desc(sc->sc_dev, "16550 or compatible");
891 } else if (count >= 28 && count <= 32) {
892 sc->sc_rxfifosz = 32;
893 device_set_desc(sc->sc_dev, "16650 or compatible");
894 } else if (count >= 56 && count <= 64) {
895 sc->sc_rxfifosz = 64;
896 device_set_desc(sc->sc_dev, "16750 or compatible");
897 } else if (count >= 112 && count <= 128) {
898 sc->sc_rxfifosz = 128;
899 device_set_desc(sc->sc_dev, "16950 or compatible");
900 } else if (count >= 224 && count <= 256) {
901 sc->sc_rxfifosz = 256;
902 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
904 sc->sc_rxfifosz = 16;
905 device_set_desc(sc->sc_dev,
906 "Non-standard ns8250 class UART with FIFOs");
910 * Force the Tx FIFO size to 16 bytes for now. We don't program the
911 * Tx trigger. Also, we assume that all data has been sent when the
914 sc->sc_txfifosz = 16;
918 * XXX there are some issues related to hardware flow control and
919 * it's likely that uart(4) is the cause. This basically needs more
920 * investigation, but we avoid using for hardware flow control
923 /* 16650s or higher have automatic flow control. */
924 if (sc->sc_rxfifosz > 16) {
934 ns8250_bus_receive(struct uart_softc *sc)
936 struct uart_bas *bas;
941 uart_lock(sc->sc_hwmtx);
942 lsr = uart_getreg(bas, REG_LSR);
943 while (lsr & LSR_RXRDY) {
944 if (uart_rx_full(sc)) {
945 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
948 xc = uart_getreg(bas, REG_DATA);
950 xc |= UART_STAT_FRAMERR;
952 xc |= UART_STAT_PARERR;
954 lsr = uart_getreg(bas, REG_LSR);
956 /* Discard everything left in the Rx FIFO. */
957 while (lsr & LSR_RXRDY) {
958 (void)uart_getreg(bas, REG_DATA);
960 lsr = uart_getreg(bas, REG_LSR);
962 uart_unlock(sc->sc_hwmtx);
967 ns8250_bus_setsig(struct uart_softc *sc, int sig)
969 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
970 struct uart_bas *bas;
977 if (sig & SER_DDTR) {
978 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
980 if (sig & SER_DRTS) {
981 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
983 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
984 uart_lock(sc->sc_hwmtx);
985 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
987 ns8250->mcr |= MCR_DTR;
989 ns8250->mcr |= MCR_RTS;
990 uart_setreg(bas, REG_MCR, ns8250->mcr);
992 uart_unlock(sc->sc_hwmtx);
997 ns8250_bus_transmit(struct uart_softc *sc)
999 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1000 struct uart_bas *bas;
1004 uart_lock(sc->sc_hwmtx);
1005 if (sc->sc_txdatasz > 1) {
1006 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
1007 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1009 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1012 for (i = 0; i < sc->sc_txdatasz; i++) {
1013 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1016 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
1019 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1022 uart_unlock(sc->sc_hwmtx);
1024 uart_sched_softih(sc, SER_INT_TXIDLE);
1029 ns8250_bus_grab(struct uart_softc *sc)
1031 struct uart_bas *bas = &sc->sc_bas;
1032 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1036 * turn off all interrupts to enter polling mode. Leave the
1037 * saved mask alone. We'll restore whatever it was in ungrab.
1038 * All pending interrupt signals are reset when IER is set to 0.
1040 uart_lock(sc->sc_hwmtx);
1041 ier = uart_getreg(bas, REG_IER);
1042 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1044 uart_unlock(sc->sc_hwmtx);
1048 ns8250_bus_ungrab(struct uart_softc *sc)
1050 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1051 struct uart_bas *bas = &sc->sc_bas;
1054 * Restore previous interrupt mask
1056 uart_lock(sc->sc_hwmtx);
1057 uart_setreg(bas, REG_IER, ns8250->ier);
1059 uart_unlock(sc->sc_hwmtx);