2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
44 #define DEFAULT_RCLK 1843200
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
51 ns8250_clrint(struct uart_bas *bas)
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
59 (void)uart_getreg(bas, REG_LSR);
60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
61 (void)uart_getreg(bas, REG_DATA);
62 else if (iir == IIR_MLSC)
63 (void)uart_getreg(bas, REG_MSR);
65 iir = uart_getreg(bas, REG_IIR);
70 ns8250_delay(struct uart_bas *bas)
75 lcr = uart_getreg(bas, REG_LCR);
76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
80 uart_setreg(bas, REG_LCR, lcr);
83 /* 1/10th the time to transmit 1 character (estimate). */
85 return (16000000 * divisor / bas->rclk);
86 return (16000 * divisor / (bas->rclk / 1000));
90 ns8250_divisor(int rclk, int baudrate)
92 int actual_baud, divisor;
98 divisor = (rclk / (baudrate << 3) + 1) >> 1;
99 if (divisor == 0 || divisor >= 65536)
101 actual_baud = rclk / (divisor << 4);
103 /* 10 times error in percent: */
104 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
106 /* 3.0% maximum error tolerance: */
107 if (error < -30 || error > 30)
114 ns8250_drain(struct uart_bas *bas, int what)
118 delay = ns8250_delay(bas);
120 if (what & UART_DRAIN_TRANSMITTER) {
122 * Pick an arbitrary high limit to avoid getting stuck in
123 * an infinite loop when the hardware is broken. Make the
124 * limit high enough to handle large FIFOs.
127 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
130 /* printf("ns8250: transmitter appears stuck... "); */
135 if (what & UART_DRAIN_RECEIVER) {
137 * Pick an arbitrary high limit to avoid getting stuck in
138 * an infinite loop when the hardware is broken. Make the
139 * limit high enough to handle large FIFOs and integrated
140 * UARTs. The HP rx2600 for example has 3 UARTs on the
141 * management board that tend to get a lot of data send
142 * to it when the UART is first activated.
145 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
146 (void)uart_getreg(bas, REG_DATA);
151 /* printf("ns8250: receiver appears broken... "); */
160 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
161 * drained. WARNING: this function clobbers the FIFO setting!
164 ns8250_flush(struct uart_bas *bas, int what)
169 if (what & UART_FLUSH_TRANSMITTER)
171 if (what & UART_FLUSH_RECEIVER)
173 uart_setreg(bas, REG_FCR, fcr);
178 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
187 else if (databits == 7)
189 else if (databits == 6)
199 divisor = ns8250_divisor(bas->rclk, baudrate);
202 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
204 uart_setreg(bas, REG_DLL, divisor & 0xff);
205 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
209 /* Set LCR and clear DLAB. */
210 uart_setreg(bas, REG_LCR, lcr);
216 * Low-level UART interface.
218 static int ns8250_probe(struct uart_bas *bas);
219 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
220 static void ns8250_term(struct uart_bas *bas);
221 static void ns8250_putc(struct uart_bas *bas, int);
222 static int ns8250_rxready(struct uart_bas *bas);
223 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
225 static struct uart_ops uart_ns8250_ops = {
226 .probe = ns8250_probe,
230 .rxready = ns8250_rxready,
235 ns8250_probe(struct uart_bas *bas)
239 /* Check known 0 bits that don't depend on DLAB. */
240 val = uart_getreg(bas, REG_IIR);
243 val = uart_getreg(bas, REG_MCR);
251 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
257 bas->rclk = DEFAULT_RCLK;
258 ns8250_param(bas, baudrate, databits, stopbits, parity);
260 /* Disable all interrupt sources. */
262 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
263 * UARTs split the receive time-out interrupt bit out separately as
264 * 0x10. This gets handled by ier_mask and ier_rxbits below.
266 ier = uart_getreg(bas, REG_IER) & 0xe0;
267 uart_setreg(bas, REG_IER, ier);
270 /* Disable the FIFO (if present). */
271 uart_setreg(bas, REG_FCR, 0);
275 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
282 ns8250_term(struct uart_bas *bas)
285 /* Clear RTS & DTR. */
286 uart_setreg(bas, REG_MCR, MCR_IE);
291 ns8250_putc(struct uart_bas *bas, int c)
296 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
298 uart_setreg(bas, REG_DATA, c);
301 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
306 ns8250_rxready(struct uart_bas *bas)
309 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
313 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
319 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
325 c = uart_getreg(bas, REG_DATA);
333 * High-level UART interface.
335 struct ns8250_softc {
336 struct uart_softc base;
345 static int ns8250_bus_attach(struct uart_softc *);
346 static int ns8250_bus_detach(struct uart_softc *);
347 static int ns8250_bus_flush(struct uart_softc *, int);
348 static int ns8250_bus_getsig(struct uart_softc *);
349 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
350 static int ns8250_bus_ipend(struct uart_softc *);
351 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
352 static int ns8250_bus_probe(struct uart_softc *);
353 static int ns8250_bus_receive(struct uart_softc *);
354 static int ns8250_bus_setsig(struct uart_softc *, int);
355 static int ns8250_bus_transmit(struct uart_softc *);
357 static kobj_method_t ns8250_methods[] = {
358 KOBJMETHOD(uart_attach, ns8250_bus_attach),
359 KOBJMETHOD(uart_detach, ns8250_bus_detach),
360 KOBJMETHOD(uart_flush, ns8250_bus_flush),
361 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
362 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
363 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
364 KOBJMETHOD(uart_param, ns8250_bus_param),
365 KOBJMETHOD(uart_probe, ns8250_bus_probe),
366 KOBJMETHOD(uart_receive, ns8250_bus_receive),
367 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
368 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
372 struct uart_class uart_ns8250_class = {
375 sizeof(struct ns8250_softc),
376 .uc_ops = &uart_ns8250_ops,
378 .uc_rclk = DEFAULT_RCLK
381 #define SIGCHG(c, i, s, d) \
383 i |= (i & s) ? s : s | d; \
385 i = (i & s) ? (i & ~s) | d : i; \
389 ns8250_bus_attach(struct uart_softc *sc)
391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
392 struct uart_bas *bas;
397 ns8250->mcr = uart_getreg(bas, REG_MCR);
398 ns8250->fcr = FCR_ENABLE;
399 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
401 if (UART_FLAGS_FCR_RX_LOW(ivar))
402 ns8250->fcr |= FCR_RX_LOW;
403 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
404 ns8250->fcr |= FCR_RX_MEDL;
405 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
406 ns8250->fcr |= FCR_RX_HIGH;
408 ns8250->fcr |= FCR_RX_MEDH;
410 ns8250->fcr |= FCR_RX_MEDH;
414 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
416 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
418 /* Get IER RX interrupt bits */
419 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
420 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
422 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
424 uart_setreg(bas, REG_FCR, ns8250->fcr);
426 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
428 if (ns8250->mcr & MCR_DTR)
429 sc->sc_hwsig |= SER_DTR;
430 if (ns8250->mcr & MCR_RTS)
431 sc->sc_hwsig |= SER_RTS;
432 ns8250_bus_getsig(sc);
435 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
436 ns8250->ier |= ns8250->ier_rxbits;
437 uart_setreg(bas, REG_IER, ns8250->ier);
444 ns8250_bus_detach(struct uart_softc *sc)
446 struct ns8250_softc *ns8250;
447 struct uart_bas *bas;
450 ns8250 = (struct ns8250_softc *)sc;
452 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
453 uart_setreg(bas, REG_IER, ier);
460 ns8250_bus_flush(struct uart_softc *sc, int what)
462 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
463 struct uart_bas *bas;
467 uart_lock(sc->sc_hwmtx);
468 if (sc->sc_rxfifosz > 1) {
469 ns8250_flush(bas, what);
470 uart_setreg(bas, REG_FCR, ns8250->fcr);
474 error = ns8250_drain(bas, what);
475 uart_unlock(sc->sc_hwmtx);
480 ns8250_bus_getsig(struct uart_softc *sc)
482 uint32_t new, old, sig;
488 uart_lock(sc->sc_hwmtx);
489 msr = uart_getreg(&sc->sc_bas, REG_MSR);
490 uart_unlock(sc->sc_hwmtx);
491 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
492 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
493 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
494 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
495 new = sig & ~SER_MASK_DELTA;
496 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
501 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
503 struct uart_bas *bas;
504 int baudrate, divisor, error;
509 uart_lock(sc->sc_hwmtx);
511 case UART_IOCTL_BREAK:
512 lcr = uart_getreg(bas, REG_LCR);
517 uart_setreg(bas, REG_LCR, lcr);
520 case UART_IOCTL_IFLOW:
521 lcr = uart_getreg(bas, REG_LCR);
523 uart_setreg(bas, REG_LCR, 0xbf);
525 efr = uart_getreg(bas, REG_EFR);
530 uart_setreg(bas, REG_EFR, efr);
532 uart_setreg(bas, REG_LCR, lcr);
535 case UART_IOCTL_OFLOW:
536 lcr = uart_getreg(bas, REG_LCR);
538 uart_setreg(bas, REG_LCR, 0xbf);
540 efr = uart_getreg(bas, REG_EFR);
545 uart_setreg(bas, REG_EFR, efr);
547 uart_setreg(bas, REG_LCR, lcr);
550 case UART_IOCTL_BAUD:
551 lcr = uart_getreg(bas, REG_LCR);
552 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
554 divisor = uart_getreg(bas, REG_DLL) |
555 (uart_getreg(bas, REG_DLH) << 8);
557 uart_setreg(bas, REG_LCR, lcr);
559 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
561 *(int*)data = baudrate;
569 uart_unlock(sc->sc_hwmtx);
574 ns8250_bus_ipend(struct uart_softc *sc)
576 struct uart_bas *bas;
581 uart_lock(sc->sc_hwmtx);
582 iir = uart_getreg(bas, REG_IIR);
583 if (iir & IIR_NOPEND) {
584 uart_unlock(sc->sc_hwmtx);
588 if (iir & IIR_RXRDY) {
589 lsr = uart_getreg(bas, REG_LSR);
590 uart_unlock(sc->sc_hwmtx);
592 ipend |= SER_INT_OVERRUN;
594 ipend |= SER_INT_BREAK;
596 ipend |= SER_INT_RXREADY;
598 uart_unlock(sc->sc_hwmtx);
600 ipend |= SER_INT_TXIDLE;
602 ipend |= SER_INT_SIGCHG;
604 return ((sc->sc_leaving) ? 0 : ipend);
608 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
609 int stopbits, int parity)
611 struct uart_bas *bas;
615 uart_lock(sc->sc_hwmtx);
616 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
617 uart_unlock(sc->sc_hwmtx);
622 ns8250_bus_probe(struct uart_softc *sc)
624 struct ns8250_softc *ns8250;
625 struct uart_bas *bas;
626 int count, delay, error, limit;
627 uint8_t lsr, mcr, ier;
629 ns8250 = (struct ns8250_softc *)sc;
632 error = ns8250_probe(bas);
637 if (sc->sc_sysdev == NULL) {
638 /* By using ns8250_init() we also set DTR and RTS. */
639 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
641 mcr |= MCR_DTR | MCR_RTS;
643 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
648 * Set loopback mode. This avoids having garbage on the wire and
649 * also allows us send and receive data. We set DTR and RTS to
650 * avoid the possibility that automatic flow-control prevents
651 * any data from being sent.
653 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
657 * Enable FIFOs. And check that the UART has them. If not, we're
658 * done. Since this is the first time we enable the FIFOs, we reset
661 uart_setreg(bas, REG_FCR, FCR_ENABLE);
663 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
665 * NS16450 or INS8250. We don't bother to differentiate
666 * between them. They're too old to be interesting.
668 uart_setreg(bas, REG_MCR, mcr);
670 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
671 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
675 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
679 delay = ns8250_delay(bas);
681 /* We have FIFOs. Drain the transmitter and receiver. */
682 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
684 uart_setreg(bas, REG_MCR, mcr);
685 uart_setreg(bas, REG_FCR, 0);
691 * We should have a sufficiently clean "pipe" to determine the
692 * size of the FIFOs. We send as much characters as is reasonable
693 * and wait for the the overflow bit in the LSR register to be
694 * asserted, counting the characters as we send them. Based on
695 * that count we know the FIFO size.
698 uart_setreg(bas, REG_DATA, 0);
705 * LSR bits are cleared upon read, so we must accumulate
706 * them to be able to test LSR_OE below.
708 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
712 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
713 uart_setreg(bas, REG_IER, ier);
714 uart_setreg(bas, REG_MCR, mcr);
715 uart_setreg(bas, REG_FCR, 0);
720 } while ((lsr & LSR_OE) == 0 && count < 130);
723 uart_setreg(bas, REG_MCR, mcr);
726 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
729 if (count >= 14 && count <= 16) {
730 sc->sc_rxfifosz = 16;
731 device_set_desc(sc->sc_dev, "16550 or compatible");
732 } else if (count >= 28 && count <= 32) {
733 sc->sc_rxfifosz = 32;
734 device_set_desc(sc->sc_dev, "16650 or compatible");
735 } else if (count >= 56 && count <= 64) {
736 sc->sc_rxfifosz = 64;
737 device_set_desc(sc->sc_dev, "16750 or compatible");
738 } else if (count >= 112 && count <= 128) {
739 sc->sc_rxfifosz = 128;
740 device_set_desc(sc->sc_dev, "16950 or compatible");
742 sc->sc_rxfifosz = 16;
743 device_set_desc(sc->sc_dev,
744 "Non-standard ns8250 class UART with FIFOs");
748 * Force the Tx FIFO size to 16 bytes for now. We don't program the
749 * Tx trigger. Also, we assume that all data has been sent when the
752 sc->sc_txfifosz = 16;
756 * XXX there are some issues related to hardware flow control and
757 * it's likely that uart(4) is the cause. This basicly needs more
758 * investigation, but we avoid using for hardware flow control
761 /* 16650s or higher have automatic flow control. */
762 if (sc->sc_rxfifosz > 16) {
772 ns8250_bus_receive(struct uart_softc *sc)
774 struct uart_bas *bas;
779 uart_lock(sc->sc_hwmtx);
780 lsr = uart_getreg(bas, REG_LSR);
781 while (lsr & LSR_RXRDY) {
782 if (uart_rx_full(sc)) {
783 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
786 xc = uart_getreg(bas, REG_DATA);
788 xc |= UART_STAT_FRAMERR;
790 xc |= UART_STAT_PARERR;
792 lsr = uart_getreg(bas, REG_LSR);
794 /* Discard everything left in the Rx FIFO. */
795 while (lsr & LSR_RXRDY) {
796 (void)uart_getreg(bas, REG_DATA);
798 lsr = uart_getreg(bas, REG_LSR);
800 uart_unlock(sc->sc_hwmtx);
805 ns8250_bus_setsig(struct uart_softc *sc, int sig)
807 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
808 struct uart_bas *bas;
815 if (sig & SER_DDTR) {
816 SIGCHG(sig & SER_DTR, new, SER_DTR,
819 if (sig & SER_DRTS) {
820 SIGCHG(sig & SER_RTS, new, SER_RTS,
823 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
824 uart_lock(sc->sc_hwmtx);
825 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
827 ns8250->mcr |= MCR_DTR;
829 ns8250->mcr |= MCR_RTS;
830 uart_setreg(bas, REG_MCR, ns8250->mcr);
832 uart_unlock(sc->sc_hwmtx);
837 ns8250_bus_transmit(struct uart_softc *sc)
839 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
840 struct uart_bas *bas;
844 uart_lock(sc->sc_hwmtx);
845 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
847 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
849 for (i = 0; i < sc->sc_txdatasz; i++) {
850 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
854 uart_unlock(sc->sc_hwmtx);