2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
50 #include <dev/uart/uart_cpu_fdt.h>
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
56 #include <dev/ic/ns16550.h>
60 #define DEFAULT_RCLK 1843200
63 * Set the default baudrate tolerance to 3.0%.
65 * Some embedded boards have odd reference clocks (eg 25MHz)
66 * and we need to handle higher variances in the target baud rate.
68 #ifndef UART_DEV_TOLERANCE_PCT
69 #define UART_DEV_TOLERANCE_PCT 30
70 #endif /* UART_DEV_TOLERANCE_PCT */
72 static int broken_txfifo = 0;
73 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
74 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
77 * Clear pending interrupts. THRE is cleared by reading IIR. Data
78 * that may have been received gets lost here.
81 ns8250_clrint(struct uart_bas *bas)
85 iir = uart_getreg(bas, REG_IIR);
86 while ((iir & IIR_NOPEND) == 0) {
89 lsr = uart_getreg(bas, REG_LSR);
90 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
91 (void)uart_getreg(bas, REG_DATA);
92 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
93 (void)uart_getreg(bas, REG_DATA);
94 else if (iir == IIR_MLSC)
95 (void)uart_getreg(bas, REG_MSR);
97 iir = uart_getreg(bas, REG_IIR);
102 ns8250_delay(struct uart_bas *bas)
107 lcr = uart_getreg(bas, REG_LCR);
108 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
110 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
112 uart_setreg(bas, REG_LCR, lcr);
115 /* 1/10th the time to transmit 1 character (estimate). */
117 return (16000000 * divisor / bas->rclk);
118 return (16000 * divisor / (bas->rclk / 1000));
122 ns8250_divisor(int rclk, int baudrate)
124 int actual_baud, divisor;
130 divisor = (rclk / (baudrate << 3) + 1) >> 1;
131 if (divisor == 0 || divisor >= 65536)
133 actual_baud = rclk / (divisor << 4);
135 /* 10 times error in percent: */
136 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
138 /* enforce maximum error tolerance: */
139 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
146 ns8250_drain(struct uart_bas *bas, int what)
150 delay = ns8250_delay(bas);
152 if (what & UART_DRAIN_TRANSMITTER) {
154 * Pick an arbitrary high limit to avoid getting stuck in
155 * an infinite loop when the hardware is broken. Make the
156 * limit high enough to handle large FIFOs.
159 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
162 /* printf("ns8250: transmitter appears stuck... "); */
167 if (what & UART_DRAIN_RECEIVER) {
169 * Pick an arbitrary high limit to avoid getting stuck in
170 * an infinite loop when the hardware is broken. Make the
171 * limit high enough to handle large FIFOs and integrated
172 * UARTs. The HP rx2600 for example has 3 UARTs on the
173 * management board that tend to get a lot of data send
174 * to it when the UART is first activated.
177 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
178 (void)uart_getreg(bas, REG_DATA);
183 /* printf("ns8250: receiver appears broken... "); */
192 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
193 * drained. WARNING: this function clobbers the FIFO setting!
196 ns8250_flush(struct uart_bas *bas, int what)
201 if (what & UART_FLUSH_TRANSMITTER)
203 if (what & UART_FLUSH_RECEIVER)
205 uart_setreg(bas, REG_FCR, fcr);
210 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
219 else if (databits == 7)
221 else if (databits == 6)
231 divisor = ns8250_divisor(bas->rclk, baudrate);
234 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
236 uart_setreg(bas, REG_DLL, divisor & 0xff);
237 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
241 /* Set LCR and clear DLAB. */
242 uart_setreg(bas, REG_LCR, lcr);
248 * Low-level UART interface.
250 static int ns8250_probe(struct uart_bas *bas);
251 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
252 static void ns8250_term(struct uart_bas *bas);
253 static void ns8250_putc(struct uart_bas *bas, int);
254 static int ns8250_rxready(struct uart_bas *bas);
255 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
257 struct uart_ops uart_ns8250_ops = {
258 .probe = ns8250_probe,
262 .rxready = ns8250_rxready,
267 ns8250_probe(struct uart_bas *bas)
271 /* Check known 0 bits that don't depend on DLAB. */
272 val = uart_getreg(bas, REG_IIR);
276 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
277 * chip, but otherwise doesn't seem to have a function. In
278 * other words, uart(4) works regardless. Ignore that bit so
279 * the probe succeeds.
281 val = uart_getreg(bas, REG_MCR);
289 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
295 bas->rclk = DEFAULT_RCLK;
296 ns8250_param(bas, baudrate, databits, stopbits, parity);
298 /* Disable all interrupt sources. */
300 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
301 * UARTs split the receive time-out interrupt bit out separately as
302 * 0x10. This gets handled by ier_mask and ier_rxbits below.
304 ier = uart_getreg(bas, REG_IER) & 0xe0;
305 uart_setreg(bas, REG_IER, ier);
308 /* Disable the FIFO (if present). */
309 uart_setreg(bas, REG_FCR, 0);
313 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
320 ns8250_term(struct uart_bas *bas)
323 /* Clear RTS & DTR. */
324 uart_setreg(bas, REG_MCR, MCR_IE);
329 ns8250_putc(struct uart_bas *bas, int c)
334 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
336 uart_setreg(bas, REG_DATA, c);
339 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
344 ns8250_rxready(struct uart_bas *bas)
347 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
351 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
357 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
363 c = uart_getreg(bas, REG_DATA);
370 static kobj_method_t ns8250_methods[] = {
371 KOBJMETHOD(uart_attach, ns8250_bus_attach),
372 KOBJMETHOD(uart_detach, ns8250_bus_detach),
373 KOBJMETHOD(uart_flush, ns8250_bus_flush),
374 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
375 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
376 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
377 KOBJMETHOD(uart_param, ns8250_bus_param),
378 KOBJMETHOD(uart_probe, ns8250_bus_probe),
379 KOBJMETHOD(uart_receive, ns8250_bus_receive),
380 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
381 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
382 KOBJMETHOD(uart_grab, ns8250_bus_grab),
383 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
387 struct uart_class uart_ns8250_class = {
390 sizeof(struct ns8250_softc),
391 .uc_ops = &uart_ns8250_ops,
393 .uc_rclk = DEFAULT_RCLK,
398 static struct ofw_compat_data compat_data[] = {
399 {"ns16550", (uintptr_t)&uart_ns8250_class},
400 {"ns16550a", (uintptr_t)&uart_ns8250_class},
401 {"snps,dw-apb-uart", (uintptr_t)&uart_ns8250_class},
402 {NULL, (uintptr_t)NULL},
404 UART_FDT_CLASS_AND_DEVICE(compat_data);
407 /* Use token-pasting to form SER_ and MSR_ named constants. */
408 #define SER(sig) SER_##sig
409 #define SERD(sig) SER_D##sig
410 #define MSR(sig) MSR_##sig
411 #define MSRD(sig) MSR_D##sig
414 * Detect signal changes using software delta detection. The previous state of
415 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
416 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
417 * new state of both the signal and the delta bits.
419 #define SIGCHGSW(var, msr, sig) \
420 if ((msr) & MSR(sig)) { \
421 if ((var & SER(sig)) == 0) \
422 var |= SERD(sig) | SER(sig); \
424 if ((var & SER(sig)) != 0) \
425 var = SERD(sig) | (var & ~SER(sig)); \
429 * Detect signal changes using the hardware msr delta bits. This is currently
430 * used only when PPS timing information is being captured using the "narrow
431 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
432 * by time the interrupt handler is invoked. The hardware will latch the fact
433 * that it changed in the delta bits.
435 #define SIGCHGHW(var, msr, sig) \
436 if ((msr) & MSRD(sig)) { \
437 if (((msr) & MSR(sig)) != 0) \
438 var |= SERD(sig) | SER(sig); \
440 var = SERD(sig) | (var & ~SER(sig)); \
444 ns8250_bus_attach(struct uart_softc *sc)
446 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
447 struct uart_bas *bas;
454 ns8250->busy_detect = 0;
458 * Check whether uart requires to read USR reg when IIR_BUSY and
461 ns8250->busy_detect = ofw_bus_is_compatible(sc->sc_dev, "snps,dw-apb-uart");
462 node = ofw_bus_get_node(sc->sc_dev);
463 /* XXX: This is kept for a short time for compatibility with older device trees */
464 if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0
466 ns8250->busy_detect = 1;
467 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
468 broken_txfifo = cell ? 1 : 0;
473 ns8250->mcr = uart_getreg(bas, REG_MCR);
474 ns8250->fcr = FCR_ENABLE;
475 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
477 if (UART_FLAGS_FCR_RX_LOW(ivar))
478 ns8250->fcr |= FCR_RX_LOW;
479 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
480 ns8250->fcr |= FCR_RX_MEDL;
481 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
482 ns8250->fcr |= FCR_RX_HIGH;
484 ns8250->fcr |= FCR_RX_MEDH;
486 ns8250->fcr |= FCR_RX_MEDH;
490 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
492 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
494 /* Get IER RX interrupt bits */
495 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
496 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
498 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
500 uart_setreg(bas, REG_FCR, ns8250->fcr);
502 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
504 if (ns8250->mcr & MCR_DTR)
505 sc->sc_hwsig |= SER_DTR;
506 if (ns8250->mcr & MCR_RTS)
507 sc->sc_hwsig |= SER_RTS;
508 ns8250_bus_getsig(sc);
511 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
512 ns8250->ier |= ns8250->ier_rxbits;
513 uart_setreg(bas, REG_IER, ns8250->ier);
517 * Timing of the H/W access was changed with r253161 of uart_core.c
518 * It has been observed that an ITE IT8513E would signal a break
519 * condition with pretty much every character it received, unless
520 * it had enough time to settle between ns8250_bus_attach() and
521 * ns8250_bus_ipend() -- which it accidentally had before r253161.
522 * It's not understood why the UART chip behaves this way and it
523 * could very well be that the DELAY make the H/W work in the same
524 * accidental manner as before. More analysis is warranted, but
525 * at least now we fixed a known regression.
532 ns8250_bus_detach(struct uart_softc *sc)
534 struct ns8250_softc *ns8250;
535 struct uart_bas *bas;
538 ns8250 = (struct ns8250_softc *)sc;
540 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
541 uart_setreg(bas, REG_IER, ier);
548 ns8250_bus_flush(struct uart_softc *sc, int what)
550 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
551 struct uart_bas *bas;
555 uart_lock(sc->sc_hwmtx);
556 if (sc->sc_rxfifosz > 1) {
557 ns8250_flush(bas, what);
558 uart_setreg(bas, REG_FCR, ns8250->fcr);
562 error = ns8250_drain(bas, what);
563 uart_unlock(sc->sc_hwmtx);
568 ns8250_bus_getsig(struct uart_softc *sc)
574 * The delta bits are reputed to be broken on some hardware, so use
575 * software delta detection by default. Use the hardware delta bits
576 * when capturing PPS pulses which are too narrow for software detection
577 * to see the edges. Hardware delta for RI doesn't work like the
578 * others, so always use software for it. Other threads may be changing
579 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
580 * update without other changes happening. Note that the SIGCHGxx()
581 * macros carefully preserve the delta bits when we have to loop several
582 * times and a signal transitions between iterations.
587 uart_lock(sc->sc_hwmtx);
588 msr = uart_getreg(&sc->sc_bas, REG_MSR);
589 uart_unlock(sc->sc_hwmtx);
590 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
591 SIGCHGHW(sig, msr, DSR);
592 SIGCHGHW(sig, msr, CTS);
593 SIGCHGHW(sig, msr, DCD);
595 SIGCHGSW(sig, msr, DSR);
596 SIGCHGSW(sig, msr, CTS);
597 SIGCHGSW(sig, msr, DCD);
599 SIGCHGSW(sig, msr, RI);
600 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
605 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
607 struct uart_bas *bas;
608 int baudrate, divisor, error;
613 uart_lock(sc->sc_hwmtx);
615 case UART_IOCTL_BREAK:
616 lcr = uart_getreg(bas, REG_LCR);
621 uart_setreg(bas, REG_LCR, lcr);
624 case UART_IOCTL_IFLOW:
625 lcr = uart_getreg(bas, REG_LCR);
627 uart_setreg(bas, REG_LCR, 0xbf);
629 efr = uart_getreg(bas, REG_EFR);
634 uart_setreg(bas, REG_EFR, efr);
636 uart_setreg(bas, REG_LCR, lcr);
639 case UART_IOCTL_OFLOW:
640 lcr = uart_getreg(bas, REG_LCR);
642 uart_setreg(bas, REG_LCR, 0xbf);
644 efr = uart_getreg(bas, REG_EFR);
649 uart_setreg(bas, REG_EFR, efr);
651 uart_setreg(bas, REG_LCR, lcr);
654 case UART_IOCTL_BAUD:
655 lcr = uart_getreg(bas, REG_LCR);
656 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
658 divisor = uart_getreg(bas, REG_DLL) |
659 (uart_getreg(bas, REG_DLH) << 8);
661 uart_setreg(bas, REG_LCR, lcr);
663 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
665 *(int*)data = baudrate;
673 uart_unlock(sc->sc_hwmtx);
678 ns8250_bus_ipend(struct uart_softc *sc)
680 struct uart_bas *bas;
681 struct ns8250_softc *ns8250;
685 ns8250 = (struct ns8250_softc *)sc;
687 uart_lock(sc->sc_hwmtx);
688 iir = uart_getreg(bas, REG_IIR);
690 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
691 (void)uart_getreg(bas, DW_REG_USR);
692 uart_unlock(sc->sc_hwmtx);
695 if (iir & IIR_NOPEND) {
696 uart_unlock(sc->sc_hwmtx);
700 if (iir & IIR_RXRDY) {
701 lsr = uart_getreg(bas, REG_LSR);
703 ipend |= SER_INT_OVERRUN;
705 ipend |= SER_INT_BREAK;
707 ipend |= SER_INT_RXREADY;
709 if (iir & IIR_TXRDY) {
710 ipend |= SER_INT_TXIDLE;
711 uart_setreg(bas, REG_IER, ns8250->ier);
714 ipend |= SER_INT_SIGCHG;
718 uart_unlock(sc->sc_hwmtx);
723 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
724 int stopbits, int parity)
726 struct ns8250_softc *ns8250;
727 struct uart_bas *bas;
730 ns8250 = (struct ns8250_softc*)sc;
732 uart_lock(sc->sc_hwmtx);
734 * When using DW UART with BUSY detection it is necessary to wait
735 * until all serial transfers are finished before manipulating the
736 * line control. LCR will not be affected when UART is busy.
738 if (ns8250->busy_detect != 0) {
740 * Pick an arbitrary high limit to avoid getting stuck in
741 * an infinite loop in case when the hardware is broken.
744 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
749 /* UART appears to be stuck */
750 uart_unlock(sc->sc_hwmtx);
755 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
756 uart_unlock(sc->sc_hwmtx);
761 ns8250_bus_probe(struct uart_softc *sc)
763 struct ns8250_softc *ns8250;
764 struct uart_bas *bas;
765 int count, delay, error, limit;
766 uint8_t lsr, mcr, ier;
768 ns8250 = (struct ns8250_softc *)sc;
771 error = ns8250_probe(bas);
776 if (sc->sc_sysdev == NULL) {
777 /* By using ns8250_init() we also set DTR and RTS. */
778 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
780 mcr |= MCR_DTR | MCR_RTS;
782 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
787 * Set loopback mode. This avoids having garbage on the wire and
788 * also allows us send and receive data. We set DTR and RTS to
789 * avoid the possibility that automatic flow-control prevents
790 * any data from being sent.
792 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
796 * Enable FIFOs. And check that the UART has them. If not, we're
797 * done. Since this is the first time we enable the FIFOs, we reset
800 uart_setreg(bas, REG_FCR, FCR_ENABLE);
802 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
804 * NS16450 or INS8250. We don't bother to differentiate
805 * between them. They're too old to be interesting.
807 uart_setreg(bas, REG_MCR, mcr);
809 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
810 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
814 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
818 delay = ns8250_delay(bas);
820 /* We have FIFOs. Drain the transmitter and receiver. */
821 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
823 uart_setreg(bas, REG_MCR, mcr);
824 uart_setreg(bas, REG_FCR, 0);
830 * We should have a sufficiently clean "pipe" to determine the
831 * size of the FIFOs. We send as much characters as is reasonable
832 * and wait for the overflow bit in the LSR register to be
833 * asserted, counting the characters as we send them. Based on
834 * that count we know the FIFO size.
837 uart_setreg(bas, REG_DATA, 0);
844 * LSR bits are cleared upon read, so we must accumulate
845 * them to be able to test LSR_OE below.
847 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
851 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
852 uart_setreg(bas, REG_IER, ier);
853 uart_setreg(bas, REG_MCR, mcr);
854 uart_setreg(bas, REG_FCR, 0);
859 } while ((lsr & LSR_OE) == 0 && count < 130);
862 uart_setreg(bas, REG_MCR, mcr);
865 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
868 if (count >= 14 && count <= 16) {
869 sc->sc_rxfifosz = 16;
870 device_set_desc(sc->sc_dev, "16550 or compatible");
871 } else if (count >= 28 && count <= 32) {
872 sc->sc_rxfifosz = 32;
873 device_set_desc(sc->sc_dev, "16650 or compatible");
874 } else if (count >= 56 && count <= 64) {
875 sc->sc_rxfifosz = 64;
876 device_set_desc(sc->sc_dev, "16750 or compatible");
877 } else if (count >= 112 && count <= 128) {
878 sc->sc_rxfifosz = 128;
879 device_set_desc(sc->sc_dev, "16950 or compatible");
881 sc->sc_rxfifosz = 16;
882 device_set_desc(sc->sc_dev,
883 "Non-standard ns8250 class UART with FIFOs");
887 * Force the Tx FIFO size to 16 bytes for now. We don't program the
888 * Tx trigger. Also, we assume that all data has been sent when the
891 sc->sc_txfifosz = 16;
895 * XXX there are some issues related to hardware flow control and
896 * it's likely that uart(4) is the cause. This basicly needs more
897 * investigation, but we avoid using for hardware flow control
900 /* 16650s or higher have automatic flow control. */
901 if (sc->sc_rxfifosz > 16) {
911 ns8250_bus_receive(struct uart_softc *sc)
913 struct uart_bas *bas;
918 uart_lock(sc->sc_hwmtx);
919 lsr = uart_getreg(bas, REG_LSR);
920 while (lsr & LSR_RXRDY) {
921 if (uart_rx_full(sc)) {
922 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
925 xc = uart_getreg(bas, REG_DATA);
927 xc |= UART_STAT_FRAMERR;
929 xc |= UART_STAT_PARERR;
931 lsr = uart_getreg(bas, REG_LSR);
933 /* Discard everything left in the Rx FIFO. */
934 while (lsr & LSR_RXRDY) {
935 (void)uart_getreg(bas, REG_DATA);
937 lsr = uart_getreg(bas, REG_LSR);
939 uart_unlock(sc->sc_hwmtx);
944 ns8250_bus_setsig(struct uart_softc *sc, int sig)
946 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
947 struct uart_bas *bas;
954 if (sig & SER_DDTR) {
955 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
957 if (sig & SER_DRTS) {
958 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
960 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
961 uart_lock(sc->sc_hwmtx);
962 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
964 ns8250->mcr |= MCR_DTR;
966 ns8250->mcr |= MCR_RTS;
967 uart_setreg(bas, REG_MCR, ns8250->mcr);
969 uart_unlock(sc->sc_hwmtx);
974 ns8250_bus_transmit(struct uart_softc *sc)
976 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
977 struct uart_bas *bas;
981 uart_lock(sc->sc_hwmtx);
982 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
984 for (i = 0; i < sc->sc_txdatasz; i++) {
985 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
988 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
991 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
994 uart_unlock(sc->sc_hwmtx);
996 uart_sched_softih(sc, SER_INT_TXIDLE);
1001 ns8250_bus_grab(struct uart_softc *sc)
1003 struct uart_bas *bas = &sc->sc_bas;
1004 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1008 * turn off all interrupts to enter polling mode. Leave the
1009 * saved mask alone. We'll restore whatever it was in ungrab.
1010 * All pending interupt signals are reset when IER is set to 0.
1012 uart_lock(sc->sc_hwmtx);
1013 ier = uart_getreg(bas, REG_IER);
1014 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1016 uart_unlock(sc->sc_hwmtx);
1020 ns8250_bus_ungrab(struct uart_softc *sc)
1022 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1023 struct uart_bas *bas = &sc->sc_bas;
1026 * Restore previous interrupt mask
1028 uart_lock(sc->sc_hwmtx);
1029 uart_setreg(bas, REG_IER, ns8250->ier);
1031 uart_unlock(sc->sc_hwmtx);