2 * Copyright (c) 2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <machine/bus.h>
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
42 #include <dev/uart/uart_cpu_fdt.h>
44 #include <dev/uart/uart_bus.h>
48 #include <dev/uart/uart_cpu_acpi.h>
49 #include <contrib/dev/acpica/include/acpi.h>
50 #include <contrib/dev/acpica/include/accommon.h>
51 #include <contrib/dev/acpica/include/actables.h>
56 /* PL011 UART registers and masks*/
57 #define UART_DR 0x00 /* Data register */
58 #define DR_FE (1 << 8) /* Framing error */
59 #define DR_PE (1 << 9) /* Parity error */
60 #define DR_BE (1 << 10) /* Break error */
61 #define DR_OE (1 << 11) /* Overrun error */
63 #define UART_FR 0x06 /* Flag register */
64 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */
65 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
66 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
67 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
69 #define UART_IBRD 0x09 /* Integer baud rate register */
70 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
72 #define UART_FBRD 0x0a /* Fractional baud rate register */
73 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
75 #define UART_LCR_H 0x0b /* Line control register */
76 #define LCR_H_WLEN8 (0x3 << 5)
77 #define LCR_H_WLEN7 (0x2 << 5)
78 #define LCR_H_WLEN6 (0x1 << 5)
79 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
80 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
81 #define LCR_H_EPS (1 << 2) /* Even parity select */
82 #define LCR_H_PEN (1 << 1) /* Parity enable */
84 #define UART_CR 0x0c /* Control register */
85 #define CR_RXE (1 << 9) /* Receive enable */
86 #define CR_TXE (1 << 8) /* Transmit enable */
87 #define CR_UARTEN (1 << 0) /* UART enable */
89 #define UART_IFLS 0x0d /* FIFO level select register */
90 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */
91 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */
92 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */
93 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */
94 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */
95 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */
96 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */
97 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */
99 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */
100 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
102 #define UART_RIS 0x0f /* Raw interrupt status register */
103 #define UART_RXREADY (1 << 4) /* RX buffer full */
104 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */
105 #define RIS_RTIM (1 << 6) /* Receive timeout */
106 #define RIS_FE (1 << 7) /* Framing error interrupt status */
107 #define RIS_PE (1 << 8) /* Parity error interrupt status */
108 #define RIS_BE (1 << 9) /* Break error interrupt status */
109 #define RIS_OE (1 << 10) /* Overrun interrupt status */
111 #define UART_MIS 0x10 /* Masked interrupt status register */
112 #define UART_ICR 0x11 /* Interrupt clear register */
115 * The hardware FIFOs are 16 bytes each. We configure them to interrupt when
116 * 3/4 full/empty. For RX we set the size to the full hardware capacity so that
117 * the uart core allocates enough buffer space to hold a complete fifo full of
118 * incoming data. For TX, we need to limit the size to the capacity we know
119 * will be available when the interrupt occurs; uart_core will feed exactly that
120 * many bytes to uart_pl011_bus_transmit() which must consume them all.
122 #define FIFO_RX_SIZE 16
123 #define FIFO_TX_SIZE 12
124 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th))
127 * FIXME: actual register size is SoC-dependent, we need to handle it
129 #define __uart_getreg(bas, reg) \
130 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
131 #define __uart_setreg(bas, reg, value) \
132 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
135 * Low-level UART interface.
137 static int uart_pl011_probe(struct uart_bas *bas);
138 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
139 static void uart_pl011_term(struct uart_bas *bas);
140 static void uart_pl011_putc(struct uart_bas *bas, int);
141 static int uart_pl011_rxready(struct uart_bas *bas);
142 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
144 static struct uart_ops uart_pl011_ops = {
145 .probe = uart_pl011_probe,
146 .init = uart_pl011_init,
147 .term = uart_pl011_term,
148 .putc = uart_pl011_putc,
149 .rxready = uart_pl011_rxready,
150 .getc = uart_pl011_getc,
154 uart_pl011_probe(struct uart_bas *bas)
161 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
168 * Zero all settings to make sure
169 * UART is disabled and not configured
172 __uart_setreg(bas, UART_CR, ctrl);
174 /* As we know UART is disabled we may setup the line */
199 /* Configure the rest */
200 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
202 if (bas->rclk != 0 && baudrate != 0) {
203 baud = bas->rclk * 4 / baudrate;
204 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
205 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
208 /* Add config. to line before reenabling UART */
209 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
212 /* Set rx and tx fifo levels. */
213 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS);
215 __uart_setreg(bas, UART_CR, ctrl);
219 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
222 /* Mask all interrupts */
223 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
226 uart_pl011_param(bas, baudrate, databits, stopbits, parity);
230 uart_pl011_term(struct uart_bas *bas)
235 uart_pl011_putc(struct uart_bas *bas, int c)
238 /* Wait when TX FIFO full. Push character otherwise. */
239 while (__uart_getreg(bas, UART_FR) & FR_TXFF)
241 __uart_setreg(bas, UART_DR, c & 0xff);
245 uart_pl011_rxready(struct uart_bas *bas)
248 return !(__uart_getreg(bas, UART_FR) & FR_RXFE);
252 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
256 while (!uart_pl011_rxready(bas))
258 c = __uart_getreg(bas, UART_DR) & 0xff;
264 * High-level UART interface.
266 struct uart_pl011_softc {
267 struct uart_softc base;
268 uint16_t imsc; /* Interrupt mask */
271 static int uart_pl011_bus_attach(struct uart_softc *);
272 static int uart_pl011_bus_detach(struct uart_softc *);
273 static int uart_pl011_bus_flush(struct uart_softc *, int);
274 static int uart_pl011_bus_getsig(struct uart_softc *);
275 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
276 static int uart_pl011_bus_ipend(struct uart_softc *);
277 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
278 static int uart_pl011_bus_probe(struct uart_softc *);
279 static int uart_pl011_bus_receive(struct uart_softc *);
280 static int uart_pl011_bus_setsig(struct uart_softc *, int);
281 static int uart_pl011_bus_transmit(struct uart_softc *);
282 static void uart_pl011_bus_grab(struct uart_softc *);
283 static void uart_pl011_bus_ungrab(struct uart_softc *);
285 static kobj_method_t uart_pl011_methods[] = {
286 KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
287 KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
288 KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
289 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
290 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
291 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
292 KOBJMETHOD(uart_param, uart_pl011_bus_param),
293 KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
294 KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
295 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
296 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
297 KOBJMETHOD(uart_grab, uart_pl011_bus_grab),
298 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab),
303 static struct uart_class uart_pl011_class = {
306 sizeof(struct uart_pl011_softc),
307 .uc_ops = &uart_pl011_ops,
315 static struct ofw_compat_data compat_data[] = {
316 {"arm,pl011", (uintptr_t)&uart_pl011_class},
317 {NULL, (uintptr_t)NULL},
319 UART_FDT_CLASS_AND_DEVICE(compat_data);
323 static struct acpi_uart_compat_data acpi_compat_data[] = {
324 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011},
327 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
331 uart_pl011_bus_attach(struct uart_softc *sc)
333 struct uart_pl011_softc *psc;
334 struct uart_bas *bas;
336 psc = (struct uart_pl011_softc *)sc;
339 /* Enable interrupts */
340 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
341 __uart_setreg(bas, UART_IMSC, psc->imsc);
343 /* Clear interrupts */
344 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
350 uart_pl011_bus_detach(struct uart_softc *sc)
357 uart_pl011_bus_flush(struct uart_softc *sc, int what)
364 uart_pl011_bus_getsig(struct uart_softc *sc)
371 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
373 struct uart_bas *bas;
378 uart_lock(sc->sc_hwmtx);
380 case UART_IOCTL_BREAK:
382 case UART_IOCTL_BAUD:
383 *(int*)data = 115200;
389 uart_unlock(sc->sc_hwmtx);
395 uart_pl011_bus_ipend(struct uart_softc *sc)
397 struct uart_pl011_softc *psc;
398 struct uart_bas *bas;
402 psc = (struct uart_pl011_softc *)sc;
405 uart_lock(sc->sc_hwmtx);
406 ints = __uart_getreg(bas, UART_MIS);
409 if (ints & (UART_RXREADY | RIS_RTIM))
410 ipend |= SER_INT_RXREADY;
412 ipend |= SER_INT_BREAK;
414 ipend |= SER_INT_OVERRUN;
415 if (ints & UART_TXEMPTY) {
417 ipend |= SER_INT_TXIDLE;
419 /* Disable TX interrupt */
420 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);
423 uart_unlock(sc->sc_hwmtx);
429 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
430 int stopbits, int parity)
433 uart_lock(sc->sc_hwmtx);
434 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
435 uart_unlock(sc->sc_hwmtx);
441 uart_pl011_bus_probe(struct uart_softc *sc)
444 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
446 sc->sc_rxfifosz = FIFO_RX_SIZE;
447 sc->sc_txfifosz = FIFO_TX_SIZE;
453 uart_pl011_bus_receive(struct uart_softc *sc)
455 struct uart_bas *bas;
460 uart_lock(sc->sc_hwmtx);
463 ints = __uart_getreg(bas, UART_FR);
466 if (uart_rx_full(sc)) {
467 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
471 xc = __uart_getreg(bas, UART_DR);
475 rx |= UART_STAT_FRAMERR;
477 rx |= UART_STAT_PARERR;
482 uart_unlock(sc->sc_hwmtx);
488 uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
495 uart_pl011_bus_transmit(struct uart_softc *sc)
497 struct uart_pl011_softc *psc;
498 struct uart_bas *bas;
501 psc = (struct uart_pl011_softc *)sc;
503 uart_lock(sc->sc_hwmtx);
505 for (i = 0; i < sc->sc_txdatasz; i++) {
506 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
510 /* Mark busy and enable TX interrupt */
512 __uart_setreg(bas, UART_IMSC, psc->imsc);
514 uart_unlock(sc->sc_hwmtx);
520 uart_pl011_bus_grab(struct uart_softc *sc)
522 struct uart_pl011_softc *psc;
523 struct uart_bas *bas;
525 psc = (struct uart_pl011_softc *)sc;
528 /* Disable interrupts on switch to polling */
529 uart_lock(sc->sc_hwmtx);
530 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);
531 uart_unlock(sc->sc_hwmtx);
535 uart_pl011_bus_ungrab(struct uart_softc *sc)
537 struct uart_pl011_softc *psc;
538 struct uart_bas *bas;
540 psc = (struct uart_pl011_softc *)sc;
543 /* Switch to using interrupts while not grabbed */
544 uart_lock(sc->sc_hwmtx);
545 __uart_setreg(bas, UART_IMSC, psc->imsc);
546 uart_unlock(sc->sc_hwmtx);