2 * Copyright (c) 2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include "opt_platform.h"
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <machine/bus.h>
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
42 #include <dev/uart/uart_cpu_fdt.h>
44 #include <dev/uart/uart_bus.h>
48 #include <dev/uart/uart_cpu_acpi.h>
49 #include <contrib/dev/acpica/include/acpi.h>
50 #include <contrib/dev/acpica/include/accommon.h>
51 #include <contrib/dev/acpica/include/actables.h>
56 /* PL011 UART registers and masks*/
57 #define UART_DR 0x00 /* Data register */
58 #define DR_FE (1 << 8) /* Framing error */
59 #define DR_PE (1 << 9) /* Parity error */
60 #define DR_BE (1 << 10) /* Break error */
61 #define DR_OE (1 << 11) /* Overrun error */
63 #define UART_FR 0x06 /* Flag register */
64 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
65 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
66 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
68 #define UART_IBRD 0x09 /* Integer baud rate register */
69 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
71 #define UART_FBRD 0x0a /* Fractional baud rate register */
72 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
74 #define UART_LCR_H 0x0b /* Line control register */
75 #define LCR_H_WLEN8 (0x3 << 5)
76 #define LCR_H_WLEN7 (0x2 << 5)
77 #define LCR_H_WLEN6 (0x1 << 5)
78 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
79 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
80 #define LCR_H_EPS (1 << 2) /* Even parity select */
81 #define LCR_H_PEN (1 << 1) /* Parity enable */
83 #define UART_CR 0x0c /* Control register */
84 #define CR_RXE (1 << 9) /* Receive enable */
85 #define CR_TXE (1 << 8) /* Transmit enable */
86 #define CR_UARTEN (1 << 0) /* UART enable */
88 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */
89 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
91 #define UART_RIS 0x0f /* Raw interrupt status register */
92 #define UART_RXREADY (1 << 4) /* RX buffer full */
93 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */
94 #define RIS_RTIM (1 << 6) /* Receive timeout */
95 #define RIS_FE (1 << 7) /* Framing error interrupt status */
96 #define RIS_PE (1 << 8) /* Parity error interrupt status */
97 #define RIS_BE (1 << 9) /* Break error interrupt status */
98 #define RIS_OE (1 << 10) /* Overrun interrupt status */
100 #define UART_MIS 0x10 /* Masked interrupt status register */
101 #define UART_ICR 0x11 /* Interrupt clear register */
104 * FIXME: actual register size is SoC-dependent, we need to handle it
106 #define __uart_getreg(bas, reg) \
107 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
108 #define __uart_setreg(bas, reg, value) \
109 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
112 * Low-level UART interface.
114 static int uart_pl011_probe(struct uart_bas *bas);
115 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
116 static void uart_pl011_term(struct uart_bas *bas);
117 static void uart_pl011_putc(struct uart_bas *bas, int);
118 static int uart_pl011_rxready(struct uart_bas *bas);
119 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
121 static struct uart_ops uart_pl011_ops = {
122 .probe = uart_pl011_probe,
123 .init = uart_pl011_init,
124 .term = uart_pl011_term,
125 .putc = uart_pl011_putc,
126 .rxready = uart_pl011_rxready,
127 .getc = uart_pl011_getc,
131 uart_pl011_probe(struct uart_bas *bas)
138 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
145 * Zero all settings to make sure
146 * UART is disabled and not configured
149 __uart_setreg(bas, UART_CR, ctrl);
151 /* As we know UART is disabled we may setup the line */
175 /* Configure the rest */
177 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
179 if (bas->rclk != 0 && baudrate != 0) {
180 baud = bas->rclk * 4 / baudrate;
181 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
182 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
185 /* Add config. to line before reenabling UART */
186 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
189 __uart_setreg(bas, UART_CR, ctrl);
193 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
196 /* Mask all interrupts */
197 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
200 uart_pl011_param(bas, baudrate, databits, stopbits, parity);
204 uart_pl011_term(struct uart_bas *bas)
209 uart_pl011_putc(struct uart_bas *bas, int c)
212 /* Wait when TX FIFO full. Push character otherwise. */
213 while (__uart_getreg(bas, UART_FR) & FR_TXFF)
215 __uart_setreg(bas, UART_DR, c & 0xff);
219 uart_pl011_rxready(struct uart_bas *bas)
222 return (__uart_getreg(bas, UART_FR) & FR_RXFF);
226 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
230 while (!uart_pl011_rxready(bas))
232 c = __uart_getreg(bas, UART_DR) & 0xff;
238 * High-level UART interface.
240 struct uart_pl011_softc {
241 struct uart_softc base;
242 uint16_t imsc; /* Interrupt mask */
245 static int uart_pl011_bus_attach(struct uart_softc *);
246 static int uart_pl011_bus_detach(struct uart_softc *);
247 static int uart_pl011_bus_flush(struct uart_softc *, int);
248 static int uart_pl011_bus_getsig(struct uart_softc *);
249 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
250 static int uart_pl011_bus_ipend(struct uart_softc *);
251 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
252 static int uart_pl011_bus_probe(struct uart_softc *);
253 static int uart_pl011_bus_receive(struct uart_softc *);
254 static int uart_pl011_bus_setsig(struct uart_softc *, int);
255 static int uart_pl011_bus_transmit(struct uart_softc *);
256 static void uart_pl011_bus_grab(struct uart_softc *);
257 static void uart_pl011_bus_ungrab(struct uart_softc *);
259 static kobj_method_t uart_pl011_methods[] = {
260 KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
261 KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
262 KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
263 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
264 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
265 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
266 KOBJMETHOD(uart_param, uart_pl011_bus_param),
267 KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
268 KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
269 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
270 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
271 KOBJMETHOD(uart_grab, uart_pl011_bus_grab),
272 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab),
277 static struct uart_class uart_pl011_class = {
280 sizeof(struct uart_pl011_softc),
281 .uc_ops = &uart_pl011_ops,
289 static struct ofw_compat_data compat_data[] = {
290 {"arm,pl011", (uintptr_t)&uart_pl011_class},
291 {NULL, (uintptr_t)NULL},
293 UART_FDT_CLASS_AND_DEVICE(compat_data);
297 static struct acpi_uart_compat_data acpi_compat_data[] = {
298 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011},
301 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
305 uart_pl011_bus_attach(struct uart_softc *sc)
307 struct uart_pl011_softc *psc;
308 struct uart_bas *bas;
310 psc = (struct uart_pl011_softc *)sc;
313 /* Enable interrupts */
314 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);
315 __uart_setreg(bas, UART_IMSC, psc->imsc);
317 /* Clear interrupts */
318 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
324 uart_pl011_bus_detach(struct uart_softc *sc)
331 uart_pl011_bus_flush(struct uart_softc *sc, int what)
338 uart_pl011_bus_getsig(struct uart_softc *sc)
345 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
347 struct uart_bas *bas;
352 uart_lock(sc->sc_hwmtx);
354 case UART_IOCTL_BREAK:
356 case UART_IOCTL_BAUD:
357 *(int*)data = 115200;
363 uart_unlock(sc->sc_hwmtx);
369 uart_pl011_bus_ipend(struct uart_softc *sc)
371 struct uart_pl011_softc *psc;
372 struct uart_bas *bas;
376 psc = (struct uart_pl011_softc *)sc;
379 uart_lock(sc->sc_hwmtx);
380 ints = __uart_getreg(bas, UART_MIS);
383 if (ints & (UART_RXREADY | RIS_RTIM))
384 ipend |= SER_INT_RXREADY;
386 ipend |= SER_INT_BREAK;
388 ipend |= SER_INT_OVERRUN;
389 if (ints & UART_TXEMPTY) {
391 ipend |= SER_INT_TXIDLE;
393 /* Disable TX interrupt */
394 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);
397 uart_unlock(sc->sc_hwmtx);
403 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
404 int stopbits, int parity)
407 uart_lock(sc->sc_hwmtx);
408 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);
409 uart_unlock(sc->sc_hwmtx);
415 uart_pl011_bus_probe(struct uart_softc *sc)
418 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
427 uart_pl011_bus_receive(struct uart_softc *sc)
429 struct uart_bas *bas;
434 uart_lock(sc->sc_hwmtx);
436 ints = __uart_getreg(bas, UART_MIS);
437 while (ints & (UART_RXREADY | RIS_RTIM)) {
438 if (uart_rx_full(sc)) {
439 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
443 __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM));
444 xc = __uart_getreg(bas, UART_DR);
448 rx |= UART_STAT_FRAMERR;
450 rx |= UART_STAT_PARERR;
453 ints = __uart_getreg(bas, UART_MIS);
456 uart_unlock(sc->sc_hwmtx);
462 uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
469 uart_pl011_bus_transmit(struct uart_softc *sc)
471 struct uart_pl011_softc *psc;
472 struct uart_bas *bas;
475 psc = (struct uart_pl011_softc *)sc;
477 uart_lock(sc->sc_hwmtx);
479 for (i = 0; i < sc->sc_txdatasz; i++) {
480 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
484 /* If not empty wait until it is */
485 if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) {
488 /* Enable TX interrupt */
489 __uart_setreg(bas, UART_IMSC, psc->imsc);
492 uart_unlock(sc->sc_hwmtx);
494 /* No interrupt expected, schedule the next fifo write */
496 uart_sched_softih(sc, SER_INT_TXIDLE);
502 uart_pl011_bus_grab(struct uart_softc *sc)
504 struct uart_pl011_softc *psc;
505 struct uart_bas *bas;
507 psc = (struct uart_pl011_softc *)sc;
510 /* Disable interrupts on switch to polling */
511 uart_lock(sc->sc_hwmtx);
512 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);
513 uart_unlock(sc->sc_hwmtx);
517 uart_pl011_bus_ungrab(struct uart_softc *sc)
519 struct uart_pl011_softc *psc;
520 struct uart_bas *bas;
522 psc = (struct uart_pl011_softc *)sc;
525 /* Switch to using interrupts while not grabbed */
526 uart_lock(sc->sc_hwmtx);
527 __uart_setreg(bas, UART_IMSC, psc->imsc);
528 uart_unlock(sc->sc_hwmtx);