2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Juniper Networks
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <machine/bus.h>
39 #include <dev/ic/quicc.h>
41 #include <dev/uart/uart.h>
42 #include <dev/uart/uart_cpu.h>
43 #include <dev/uart/uart_bus.h>
47 #define DEFAULT_RCLK ((266000000 * 2) / 16)
49 #define quicc_read2(bas, reg) \
50 bus_space_read_2((bas)->bst, (bas)->bsh, reg)
51 #define quicc_read4(bas, reg) \
52 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
54 #define quicc_write2(bas, reg, val) \
55 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
56 #define quicc_write4(bas, reg, val) \
57 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)
60 quicc_divisor(int rclk, int baudrate)
62 int act_baud, divisor, error;
67 divisor = rclk / baudrate / 16;
69 divisor = ((divisor >> 3) - 2) | 1;
70 else if (divisor >= 0)
71 divisor = (divisor - 1) << 1;
72 if (divisor < 0 || divisor >= 8192)
74 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4));
76 /* 10 times error in percent: */
77 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
79 /* 3.0% maximum error tolerance: */
80 if (error < -30 || error > 30)
87 quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
94 divisor = quicc_divisor(bas->rclk, baudrate);
97 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1),
103 case 5: psmr |= 0x0000; break;
104 case 6: psmr |= 0x1000; break;
105 case 7: psmr |= 0x2000; break;
106 case 8: psmr |= 0x3000; break;
107 default: return (EINVAL);
110 case 1: psmr |= 0x0000; break;
111 case 2: psmr |= 0x4000; break;
112 default: return (EINVAL);
115 case UART_PARITY_EVEN: psmr |= 0x1a; break;
116 case UART_PARITY_MARK: psmr |= 0x1f; break;
117 case UART_PARITY_NONE: psmr |= 0x00; break;
118 case UART_PARITY_ODD: psmr |= 0x10; break;
119 case UART_PARITY_SPACE: psmr |= 0x15; break;
120 default: return (EINVAL);
122 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr);
127 quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
132 bas->rclk = DEFAULT_RCLK;
135 * GSMR_L = 0x00028034
136 * GSMR_H = 0x00000020
138 quicc_param(bas, baudrate, databits, stopbits, parity);
140 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
141 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);
145 * Low-level UART interface.
147 static int quicc_probe(struct uart_bas *bas);
148 static void quicc_init(struct uart_bas *bas, int, int, int, int);
149 static void quicc_term(struct uart_bas *bas);
150 static void quicc_putc(struct uart_bas *bas, int);
151 static int quicc_rxready(struct uart_bas *bas);
152 static int quicc_getc(struct uart_bas *bas, struct mtx *);
154 static struct uart_ops uart_quicc_ops = {
155 .probe = quicc_probe,
159 .rxready = quicc_rxready,
164 quicc_probe(struct uart_bas *bas)
171 quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
175 quicc_setup(bas, baudrate, databits, stopbits, parity);
179 quicc_term(struct uart_bas *bas)
184 quicc_putc(struct uart_bas *bas, int c)
189 unit = bas->chan - 1;
190 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)
193 toseq = 0x2000 | (c & 0xff);
194 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq);
198 quicc_rxready(struct uart_bas *bas)
202 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
203 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);
207 quicc_getc(struct uart_bas *bas, struct mtx *hwmtx)
215 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
217 while ((sc = quicc_read2(bas, rb)) & 0x8000) {
223 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
225 quicc_write2(bas, rb, sc | 0x8000);
233 * High-level UART interface.
236 struct uart_softc base;
239 static int quicc_bus_attach(struct uart_softc *);
240 static int quicc_bus_detach(struct uart_softc *);
241 static int quicc_bus_flush(struct uart_softc *, int);
242 static int quicc_bus_getsig(struct uart_softc *);
243 static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t);
244 static int quicc_bus_ipend(struct uart_softc *);
245 static int quicc_bus_param(struct uart_softc *, int, int, int, int);
246 static int quicc_bus_probe(struct uart_softc *);
247 static int quicc_bus_receive(struct uart_softc *);
248 static int quicc_bus_setsig(struct uart_softc *, int);
249 static int quicc_bus_transmit(struct uart_softc *);
250 static void quicc_bus_grab(struct uart_softc *);
251 static void quicc_bus_ungrab(struct uart_softc *);
253 static kobj_method_t quicc_methods[] = {
254 KOBJMETHOD(uart_attach, quicc_bus_attach),
255 KOBJMETHOD(uart_detach, quicc_bus_detach),
256 KOBJMETHOD(uart_flush, quicc_bus_flush),
257 KOBJMETHOD(uart_getsig, quicc_bus_getsig),
258 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl),
259 KOBJMETHOD(uart_ipend, quicc_bus_ipend),
260 KOBJMETHOD(uart_param, quicc_bus_param),
261 KOBJMETHOD(uart_probe, quicc_bus_probe),
262 KOBJMETHOD(uart_receive, quicc_bus_receive),
263 KOBJMETHOD(uart_setsig, quicc_bus_setsig),
264 KOBJMETHOD(uart_transmit, quicc_bus_transmit),
265 KOBJMETHOD(uart_grab, quicc_bus_grab),
266 KOBJMETHOD(uart_ungrab, quicc_bus_ungrab),
270 struct uart_class uart_quicc_class = {
273 sizeof(struct quicc_softc),
274 .uc_ops = &uart_quicc_ops,
276 .uc_rclk = DEFAULT_RCLK,
280 #define SIGCHG(c, i, s, d) \
282 i |= (i & s) ? s : s | d; \
284 i = (i & s) ? (i & ~s) | d : i; \
288 quicc_bus_attach(struct uart_softc *sc)
290 struct uart_bas *bas;
291 struct uart_devinfo *di;
295 if (sc->sc_sysdev != NULL) {
297 quicc_param(bas, di->baudrate, di->databits, di->stopbits,
300 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
303 /* Enable interrupts on the receive buffer. */
304 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
305 st = quicc_read2(bas, rb);
306 quicc_write2(bas, rb, st | 0x9000);
308 (void)quicc_bus_getsig(sc);
314 quicc_bus_detach(struct uart_softc *sc)
321 quicc_bus_flush(struct uart_softc *sc, int what)
328 quicc_bus_getsig(struct uart_softc *sc)
330 uint32_t new, old, sig;
336 uart_lock(sc->sc_hwmtx);
339 uart_unlock(sc->sc_hwmtx);
340 SIGCHG(dummy, sig, SER_CTS, SER_DCTS);
341 SIGCHG(dummy, sig, SER_DCD, SER_DDCD);
342 SIGCHG(dummy, sig, SER_DSR, SER_DDSR);
343 new = sig & ~SER_MASK_DELTA;
344 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
349 quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
351 struct uart_bas *bas;
357 uart_lock(sc->sc_hwmtx);
359 case UART_IOCTL_BREAK:
361 case UART_IOCTL_BAUD:
362 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;
363 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1;
364 baudrate = bas->rclk / (brg * 16);
365 *(int*)data = baudrate;
371 uart_unlock(sc->sc_hwmtx);
376 quicc_bus_ipend(struct uart_softc *sc)
378 struct uart_bas *bas;
385 uart_lock(sc->sc_hwmtx);
386 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1));
387 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
388 uart_unlock(sc->sc_hwmtx);
390 ipend |= SER_INT_RXREADY;
392 ipend |= SER_INT_TXIDLE;
394 ipend |= SER_INT_OVERRUN;
396 ipend |= SER_INT_BREAK;
402 quicc_bus_param(struct uart_softc *sc, int baudrate, int databits,
403 int stopbits, int parity)
407 uart_lock(sc->sc_hwmtx);
408 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits,
410 uart_unlock(sc->sc_hwmtx);
415 quicc_bus_probe(struct uart_softc *sc)
420 error = quicc_probe(&sc->sc_bas);
427 snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan);
428 device_set_desc_copy(sc->sc_dev, buf);
433 quicc_bus_receive(struct uart_softc *sc)
435 struct uart_bas *bas;
440 uart_lock(sc->sc_hwmtx);
441 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
442 st = quicc_read2(bas, rb);
443 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
444 uart_rx_put(sc, *buf);
445 quicc_write2(bas, rb, st | 0x9000);
446 uart_unlock(sc->sc_hwmtx);
451 quicc_bus_setsig(struct uart_softc *sc, int sig)
453 struct uart_bas *bas;
460 if (sig & SER_DDTR) {
461 SIGCHG(sig & SER_DTR, new, SER_DTR,
464 if (sig & SER_DRTS) {
465 SIGCHG(sig & SER_RTS, new, SER_RTS,
468 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
470 uart_lock(sc->sc_hwmtx);
472 uart_unlock(sc->sc_hwmtx);
477 quicc_bus_transmit(struct uart_softc *sc)
480 struct uart_bas *bas;
484 uart_lock(sc->sc_hwmtx);
485 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1));
486 st = quicc_read2(bas, tb);
487 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4);
488 *buf = sc->sc_txbuf[0];
489 quicc_write2(bas, tb + 2, 1);
490 quicc_write2(bas, tb, st | 0x9000);
492 uart_unlock(sc->sc_hwmtx);
497 quicc_bus_grab(struct uart_softc *sc)
499 struct uart_bas *bas;
502 /* Disable interrupts on the receive buffer. */
504 uart_lock(sc->sc_hwmtx);
505 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
506 st = quicc_read2(bas, rb);
507 quicc_write2(bas, rb, st & ~0x9000);
508 uart_unlock(sc->sc_hwmtx);
512 quicc_bus_ungrab(struct uart_softc *sc)
514 struct uart_bas *bas;
517 /* Enable interrupts on the receive buffer. */
519 uart_lock(sc->sc_hwmtx);
520 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
521 st = quicc_read2(bas, rb);
522 quicc_write2(bas, rb, st | 0x9000);
523 uart_unlock(sc->sc_hwmtx);