2 * Copyright (c) 2006 Juniper Networks
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <machine/bus.h>
37 #include <dev/ic/quicc.h>
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
41 #include <dev/uart/uart_bus.h>
45 #define DEFAULT_RCLK ((266000000 * 2) / 16)
47 #define quicc_read2(bas, reg) \
48 bus_space_read_2((bas)->bst, (bas)->bsh, reg)
49 #define quicc_read4(bas, reg) \
50 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
52 #define quicc_write2(bas, reg, val) \
53 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
54 #define quicc_write4(bas, reg, val) \
55 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)
58 quicc_divisor(int rclk, int baudrate)
60 int act_baud, divisor, error;
65 divisor = rclk / baudrate / 16;
67 divisor = ((divisor >> 3) - 2) | 1;
68 else if (divisor >= 0)
69 divisor = (divisor - 1) << 1;
70 if (divisor < 0 || divisor >= 8192)
72 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4));
74 /* 10 times error in percent: */
75 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
77 /* 3.0% maximum error tolerance: */
78 if (error < -30 || error > 30)
85 quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
92 divisor = quicc_divisor(bas->rclk, baudrate);
95 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1),
101 case 5: psmr |= 0x0000; break;
102 case 6: psmr |= 0x1000; break;
103 case 7: psmr |= 0x2000; break;
104 case 8: psmr |= 0x3000; break;
105 default: return (EINVAL);
108 case 1: psmr |= 0x0000; break;
109 case 2: psmr |= 0x4000; break;
110 default: return (EINVAL);
113 case UART_PARITY_EVEN: psmr |= 0x1a; break;
114 case UART_PARITY_MARK: psmr |= 0x1f; break;
115 case UART_PARITY_NONE: psmr |= 0x00; break;
116 case UART_PARITY_ODD: psmr |= 0x10; break;
117 case UART_PARITY_SPACE: psmr |= 0x15; break;
118 default: return (EINVAL);
120 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr);
125 quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
130 bas->rclk = DEFAULT_RCLK;
133 * GSMR_L = 0x00028034
134 * GSMR_H = 0x00000020
136 quicc_param(bas, baudrate, databits, stopbits, parity);
138 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
139 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);
143 * Low-level UART interface.
145 static int quicc_probe(struct uart_bas *bas);
146 static void quicc_init(struct uart_bas *bas, int, int, int, int);
147 static void quicc_term(struct uart_bas *bas);
148 static void quicc_putc(struct uart_bas *bas, int);
149 static int quicc_rxready(struct uart_bas *bas);
150 static int quicc_getc(struct uart_bas *bas, struct mtx *);
152 static struct uart_ops uart_quicc_ops = {
153 .probe = quicc_probe,
157 .rxready = quicc_rxready,
162 quicc_probe(struct uart_bas *bas)
169 quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
173 quicc_setup(bas, baudrate, databits, stopbits, parity);
177 quicc_term(struct uart_bas *bas)
182 quicc_putc(struct uart_bas *bas, int c)
187 unit = bas->chan - 1;
188 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)
191 toseq = 0x2000 | (c & 0xff);
192 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq);
196 quicc_rxready(struct uart_bas *bas)
200 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
201 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);
205 quicc_getc(struct uart_bas *bas, struct mtx *hwmtx)
213 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
215 while ((sc = quicc_read2(bas, rb)) & 0x8000) {
221 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
223 quicc_write2(bas, rb, sc | 0x8000);
231 * High-level UART interface.
234 struct uart_softc base;
237 static int quicc_bus_attach(struct uart_softc *);
238 static int quicc_bus_detach(struct uart_softc *);
239 static int quicc_bus_flush(struct uart_softc *, int);
240 static int quicc_bus_getsig(struct uart_softc *);
241 static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t);
242 static int quicc_bus_ipend(struct uart_softc *);
243 static int quicc_bus_param(struct uart_softc *, int, int, int, int);
244 static int quicc_bus_probe(struct uart_softc *);
245 static int quicc_bus_receive(struct uart_softc *);
246 static int quicc_bus_setsig(struct uart_softc *, int);
247 static int quicc_bus_transmit(struct uart_softc *);
248 static void quicc_bus_grab(struct uart_softc *);
249 static void quicc_bus_ungrab(struct uart_softc *);
251 static kobj_method_t quicc_methods[] = {
252 KOBJMETHOD(uart_attach, quicc_bus_attach),
253 KOBJMETHOD(uart_detach, quicc_bus_detach),
254 KOBJMETHOD(uart_flush, quicc_bus_flush),
255 KOBJMETHOD(uart_getsig, quicc_bus_getsig),
256 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl),
257 KOBJMETHOD(uart_ipend, quicc_bus_ipend),
258 KOBJMETHOD(uart_param, quicc_bus_param),
259 KOBJMETHOD(uart_probe, quicc_bus_probe),
260 KOBJMETHOD(uart_receive, quicc_bus_receive),
261 KOBJMETHOD(uart_setsig, quicc_bus_setsig),
262 KOBJMETHOD(uart_transmit, quicc_bus_transmit),
263 KOBJMETHOD(uart_grab, quicc_bus_grab),
264 KOBJMETHOD(uart_ungrab, quicc_bus_ungrab),
268 struct uart_class uart_quicc_class = {
271 sizeof(struct quicc_softc),
272 .uc_ops = &uart_quicc_ops,
274 .uc_rclk = DEFAULT_RCLK
277 #define SIGCHG(c, i, s, d) \
279 i |= (i & s) ? s : s | d; \
281 i = (i & s) ? (i & ~s) | d : i; \
285 quicc_bus_attach(struct uart_softc *sc)
287 struct uart_bas *bas;
288 struct uart_devinfo *di;
292 if (sc->sc_sysdev != NULL) {
294 quicc_param(bas, di->baudrate, di->databits, di->stopbits,
297 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
300 /* Enable interrupts on the receive buffer. */
301 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
302 st = quicc_read2(bas, rb);
303 quicc_write2(bas, rb, st | 0x9000);
305 (void)quicc_bus_getsig(sc);
311 quicc_bus_detach(struct uart_softc *sc)
318 quicc_bus_flush(struct uart_softc *sc, int what)
325 quicc_bus_getsig(struct uart_softc *sc)
327 uint32_t new, old, sig;
333 uart_lock(sc->sc_hwmtx);
336 uart_unlock(sc->sc_hwmtx);
337 SIGCHG(dummy, sig, SER_CTS, SER_DCTS);
338 SIGCHG(dummy, sig, SER_DCD, SER_DDCD);
339 SIGCHG(dummy, sig, SER_DSR, SER_DDSR);
340 new = sig & ~SER_MASK_DELTA;
341 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
346 quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
348 struct uart_bas *bas;
354 uart_lock(sc->sc_hwmtx);
356 case UART_IOCTL_BREAK:
358 case UART_IOCTL_BAUD:
359 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;
360 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1;
361 baudrate = bas->rclk / (brg * 16);
362 *(int*)data = baudrate;
368 uart_unlock(sc->sc_hwmtx);
373 quicc_bus_ipend(struct uart_softc *sc)
375 struct uart_bas *bas;
382 uart_lock(sc->sc_hwmtx);
383 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1));
384 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
385 uart_unlock(sc->sc_hwmtx);
387 ipend |= SER_INT_RXREADY;
389 ipend |= SER_INT_TXIDLE;
391 ipend |= SER_INT_OVERRUN;
393 ipend |= SER_INT_BREAK;
399 quicc_bus_param(struct uart_softc *sc, int baudrate, int databits,
400 int stopbits, int parity)
404 uart_lock(sc->sc_hwmtx);
405 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits,
407 uart_unlock(sc->sc_hwmtx);
412 quicc_bus_probe(struct uart_softc *sc)
417 error = quicc_probe(&sc->sc_bas);
424 snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan);
425 device_set_desc_copy(sc->sc_dev, buf);
430 quicc_bus_receive(struct uart_softc *sc)
432 struct uart_bas *bas;
437 uart_lock(sc->sc_hwmtx);
438 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
439 st = quicc_read2(bas, rb);
440 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
441 uart_rx_put(sc, *buf);
442 quicc_write2(bas, rb, st | 0x9000);
443 uart_unlock(sc->sc_hwmtx);
448 quicc_bus_setsig(struct uart_softc *sc, int sig)
450 struct uart_bas *bas;
457 if (sig & SER_DDTR) {
458 SIGCHG(sig & SER_DTR, new, SER_DTR,
461 if (sig & SER_DRTS) {
462 SIGCHG(sig & SER_RTS, new, SER_RTS,
465 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
467 uart_lock(sc->sc_hwmtx);
469 uart_unlock(sc->sc_hwmtx);
474 quicc_bus_transmit(struct uart_softc *sc)
477 struct uart_bas *bas;
481 uart_lock(sc->sc_hwmtx);
482 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1));
483 st = quicc_read2(bas, tb);
484 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4);
485 *buf = sc->sc_txbuf[0];
486 quicc_write2(bas, tb + 2, 1);
487 quicc_write2(bas, tb, st | 0x9000);
489 uart_unlock(sc->sc_hwmtx);
494 quicc_bus_grab(struct uart_softc *sc)
496 struct uart_bas *bas;
499 /* Disable interrupts on the receive buffer. */
501 uart_lock(sc->sc_hwmtx);
502 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
503 st = quicc_read2(bas, rb);
504 quicc_write2(bas, rb, st & ~0x9000);
505 uart_unlock(sc->sc_hwmtx);
509 quicc_bus_ungrab(struct uart_softc *sc)
511 struct uart_bas *bas;
514 /* Enable interrupts on the receive buffer. */
516 uart_lock(sc->sc_hwmtx);
517 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
518 st = quicc_read2(bas, rb);
519 quicc_write2(bas, rb, st | 0x9000);
520 uart_unlock(sc->sc_hwmtx);