2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006 Juniper Networks
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/endian.h>
34 #include <machine/bus.h>
36 #include <dev/ic/quicc.h>
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_bus.h>
44 #define DEFAULT_RCLK ((266000000 * 2) / 16)
46 #define quicc_read2(bas, reg) \
47 bus_space_read_2((bas)->bst, (bas)->bsh, reg)
48 #define quicc_read4(bas, reg) \
49 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
51 #define quicc_write2(bas, reg, val) \
52 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
53 #define quicc_write4(bas, reg, val) \
54 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)
57 quicc_divisor(int rclk, int baudrate)
59 int act_baud, divisor, error;
64 divisor = rclk / baudrate / 16;
66 divisor = ((divisor >> 3) - 2) | 1;
67 else if (divisor >= 0)
68 divisor = (divisor - 1) << 1;
69 if (divisor < 0 || divisor >= 8192)
71 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4));
73 /* 10 times error in percent: */
74 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
76 /* 3.0% maximum error tolerance: */
77 if (error < -30 || error > 30)
84 quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
91 divisor = quicc_divisor(bas->rclk, baudrate);
94 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1),
100 case 5: psmr |= 0x0000; break;
101 case 6: psmr |= 0x1000; break;
102 case 7: psmr |= 0x2000; break;
103 case 8: psmr |= 0x3000; break;
104 default: return (EINVAL);
107 case 1: psmr |= 0x0000; break;
108 case 2: psmr |= 0x4000; break;
109 default: return (EINVAL);
112 case UART_PARITY_EVEN: psmr |= 0x1a; break;
113 case UART_PARITY_MARK: psmr |= 0x1f; break;
114 case UART_PARITY_NONE: psmr |= 0x00; break;
115 case UART_PARITY_ODD: psmr |= 0x10; break;
116 case UART_PARITY_SPACE: psmr |= 0x15; break;
117 default: return (EINVAL);
119 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr);
124 quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
129 bas->rclk = DEFAULT_RCLK;
132 * GSMR_L = 0x00028034
133 * GSMR_H = 0x00000020
135 quicc_param(bas, baudrate, databits, stopbits, parity);
137 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
138 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);
142 * Low-level UART interface.
144 static int quicc_probe(struct uart_bas *bas);
145 static void quicc_init(struct uart_bas *bas, int, int, int, int);
146 static void quicc_term(struct uart_bas *bas);
147 static void quicc_putc(struct uart_bas *bas, int);
148 static int quicc_rxready(struct uart_bas *bas);
149 static int quicc_getc(struct uart_bas *bas, struct mtx *);
151 static struct uart_ops uart_quicc_ops = {
152 .probe = quicc_probe,
156 .rxready = quicc_rxready,
161 quicc_probe(struct uart_bas *bas)
168 quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
172 quicc_setup(bas, baudrate, databits, stopbits, parity);
176 quicc_term(struct uart_bas *bas)
181 quicc_putc(struct uart_bas *bas, int c)
186 unit = bas->chan - 1;
187 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)
190 toseq = 0x2000 | (c & 0xff);
191 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq);
195 quicc_rxready(struct uart_bas *bas)
199 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
200 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);
204 quicc_getc(struct uart_bas *bas, struct mtx *hwmtx)
212 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
214 while ((sc = quicc_read2(bas, rb)) & 0x8000) {
220 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
222 quicc_write2(bas, rb, sc | 0x8000);
230 * High-level UART interface.
233 struct uart_softc base;
236 static int quicc_bus_attach(struct uart_softc *);
237 static int quicc_bus_detach(struct uart_softc *);
238 static int quicc_bus_flush(struct uart_softc *, int);
239 static int quicc_bus_getsig(struct uart_softc *);
240 static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t);
241 static int quicc_bus_ipend(struct uart_softc *);
242 static int quicc_bus_param(struct uart_softc *, int, int, int, int);
243 static int quicc_bus_probe(struct uart_softc *);
244 static int quicc_bus_receive(struct uart_softc *);
245 static int quicc_bus_setsig(struct uart_softc *, int);
246 static int quicc_bus_transmit(struct uart_softc *);
247 static void quicc_bus_grab(struct uart_softc *);
248 static void quicc_bus_ungrab(struct uart_softc *);
250 static kobj_method_t quicc_methods[] = {
251 KOBJMETHOD(uart_attach, quicc_bus_attach),
252 KOBJMETHOD(uart_detach, quicc_bus_detach),
253 KOBJMETHOD(uart_flush, quicc_bus_flush),
254 KOBJMETHOD(uart_getsig, quicc_bus_getsig),
255 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl),
256 KOBJMETHOD(uart_ipend, quicc_bus_ipend),
257 KOBJMETHOD(uart_param, quicc_bus_param),
258 KOBJMETHOD(uart_probe, quicc_bus_probe),
259 KOBJMETHOD(uart_receive, quicc_bus_receive),
260 KOBJMETHOD(uart_setsig, quicc_bus_setsig),
261 KOBJMETHOD(uart_transmit, quicc_bus_transmit),
262 KOBJMETHOD(uart_grab, quicc_bus_grab),
263 KOBJMETHOD(uart_ungrab, quicc_bus_ungrab),
267 struct uart_class uart_quicc_class = {
270 sizeof(struct quicc_softc),
271 .uc_ops = &uart_quicc_ops,
273 .uc_rclk = DEFAULT_RCLK,
276 UART_CLASS(uart_quicc_class);
278 #define SIGCHG(c, i, s, d) \
280 i |= (i & s) ? s : s | d; \
282 i = (i & s) ? (i & ~s) | d : i; \
286 quicc_bus_attach(struct uart_softc *sc)
288 struct uart_bas *bas;
289 struct uart_devinfo *di;
293 if (sc->sc_sysdev != NULL) {
295 quicc_param(bas, di->baudrate, di->databits, di->stopbits,
298 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
301 /* Enable interrupts on the receive buffer. */
302 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
303 st = quicc_read2(bas, rb);
304 quicc_write2(bas, rb, st | 0x9000);
306 (void)quicc_bus_getsig(sc);
312 quicc_bus_detach(struct uart_softc *sc)
319 quicc_bus_flush(struct uart_softc *sc, int what)
326 quicc_bus_getsig(struct uart_softc *sc)
328 uint32_t new, old, sig;
334 uart_lock(sc->sc_hwmtx);
337 uart_unlock(sc->sc_hwmtx);
338 SIGCHG(dummy, sig, SER_CTS, SER_DCTS);
339 SIGCHG(dummy, sig, SER_DCD, SER_DDCD);
340 SIGCHG(dummy, sig, SER_DSR, SER_DDSR);
341 new = sig & ~SER_MASK_DELTA;
342 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
347 quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
349 struct uart_bas *bas;
355 uart_lock(sc->sc_hwmtx);
357 case UART_IOCTL_BREAK:
359 case UART_IOCTL_BAUD:
360 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;
361 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1;
362 baudrate = bas->rclk / (brg * 16);
363 *(int*)data = baudrate;
369 uart_unlock(sc->sc_hwmtx);
374 quicc_bus_ipend(struct uart_softc *sc)
376 struct uart_bas *bas;
383 uart_lock(sc->sc_hwmtx);
384 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1));
385 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
386 uart_unlock(sc->sc_hwmtx);
388 ipend |= SER_INT_RXREADY;
390 ipend |= SER_INT_TXIDLE;
392 ipend |= SER_INT_OVERRUN;
394 ipend |= SER_INT_BREAK;
400 quicc_bus_param(struct uart_softc *sc, int baudrate, int databits,
401 int stopbits, int parity)
405 uart_lock(sc->sc_hwmtx);
406 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits,
408 uart_unlock(sc->sc_hwmtx);
413 quicc_bus_probe(struct uart_softc *sc)
418 error = quicc_probe(&sc->sc_bas);
425 snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan);
426 device_set_desc_copy(sc->sc_dev, buf);
431 quicc_bus_receive(struct uart_softc *sc)
433 struct uart_bas *bas;
438 uart_lock(sc->sc_hwmtx);
439 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
440 st = quicc_read2(bas, rb);
441 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
442 uart_rx_put(sc, *buf);
443 quicc_write2(bas, rb, st | 0x9000);
444 uart_unlock(sc->sc_hwmtx);
449 quicc_bus_setsig(struct uart_softc *sc, int sig)
456 if (sig & SER_DDTR) {
457 SIGCHG(sig & SER_DTR, new, SER_DTR,
460 if (sig & SER_DRTS) {
461 SIGCHG(sig & SER_RTS, new, SER_RTS,
464 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
466 uart_lock(sc->sc_hwmtx);
468 uart_unlock(sc->sc_hwmtx);
473 quicc_bus_transmit(struct uart_softc *sc)
476 struct uart_bas *bas;
480 uart_lock(sc->sc_hwmtx);
481 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1));
482 st = quicc_read2(bas, tb);
483 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4);
484 *buf = sc->sc_txbuf[0];
485 quicc_write2(bas, tb + 2, 1);
486 quicc_write2(bas, tb, st | 0x9000);
488 uart_unlock(sc->sc_hwmtx);
493 quicc_bus_grab(struct uart_softc *sc)
495 struct uart_bas *bas;
498 /* Disable interrupts on the receive buffer. */
500 uart_lock(sc->sc_hwmtx);
501 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
502 st = quicc_read2(bas, rb);
503 quicc_write2(bas, rb, st & ~0x9000);
504 uart_unlock(sc->sc_hwmtx);
508 quicc_bus_ungrab(struct uart_softc *sc)
510 struct uart_bas *bas;
513 /* Enable interrupts on the receive buffer. */
515 uart_lock(sc->sc_hwmtx);
516 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
517 st = quicc_read2(bas, rb);
518 quicc_write2(bas, rb, st | 0x9000);
519 uart_unlock(sc->sc_hwmtx);