2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/sab82532.h>
44 #define DEFAULT_RCLK 29491200
47 * NOTE: To allow us to read the baudrate divisor from the chip, we
48 * copy the value written to the write-only BGR register to an unused
49 * read-write register. We use TCR for that.
53 sab82532_delay(struct uart_bas *bas)
58 bgr = uart_getreg(bas, SAB_TCR);
59 ccr2 = uart_getreg(bas, SAB_CCR2);
61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
64 /* 1/10th the time to transmit 1 character (estimate). */
65 return (16000000 * divisor / bas->rclk);
69 sab82532_divisor(int rclk, int baudrate)
71 int act_baud, act_div, divisor;
77 divisor = (rclk / (baudrate << 3) + 1) >> 1;
78 if (divisor < 2 || divisor >= 1048576)
81 /* Find the best (N+1,M) pair. */
82 for (m = 1; m < 15; m++) {
87 act_baud = rclk / (act_div << 4);
89 /* 10 times error in percent: */
90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
92 /* 3.0% maximum error tolerance: */
93 if (error < -30 || error > 30)
97 return ((n - 1) | (m << 6));
104 sab82532_flush(struct uart_bas *bas, int what)
107 if (what & UART_FLUSH_TRANSMITTER) {
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
113 if (what & UART_FLUSH_RECEIVER) {
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
122 sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
129 dafo = SAB_DAFO_CHL_CS8;
130 else if (databits == 7)
131 dafo = SAB_DAFO_CHL_CS7;
132 else if (databits == 6)
133 dafo = SAB_DAFO_CHL_CS6;
135 dafo = SAB_DAFO_CHL_CS5;
137 dafo |= SAB_DAFO_STOP;
139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
144 default: return (EINVAL);
149 divisor = sab82532_divisor(bas->rclk, baudrate);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
154 /* Allow reading the (n-1,m) tuple from the chip. */
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
157 ccr2 = uart_getreg(bas, SAB_CCR2);
158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
160 uart_setreg(bas, SAB_CCR2, ccr2);
164 uart_setreg(bas, SAB_DAFO, dafo);
170 * Low-level UART interface.
172 static int sab82532_probe(struct uart_bas *bas);
173 static void sab82532_init(struct uart_bas *bas, int, int, int, int);
174 static void sab82532_term(struct uart_bas *bas);
175 static void sab82532_putc(struct uart_bas *bas, int);
176 static int sab82532_rxready(struct uart_bas *bas);
177 static int sab82532_getc(struct uart_bas *bas, struct mtx *);
179 static struct uart_ops uart_sab82532_ops = {
180 .probe = sab82532_probe,
181 .init = sab82532_init,
182 .term = sab82532_term,
183 .putc = sab82532_putc,
184 .rxready = sab82532_rxready,
185 .getc = sab82532_getc,
189 sab82532_probe(struct uart_bas *bas)
196 sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
202 bas->rclk = DEFAULT_RCLK;
205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
206 * Pin 4 is magical, meaning that I don't know what it does, but
207 * it too has to be set to output.
209 uart_setreg(bas, SAB_PCR,
210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
212 /* Disable port interrupts. */
213 uart_setreg(bas, SAB_PIM, 0xff);
215 /* Interrupts are active low. */
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
219 pvr = uart_getreg(bas, SAB_PVR);
222 pvr &= ~SAB_PVR_DTR_A;
225 pvr &= ~SAB_PVR_DTR_B;
228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
232 uart_setreg(bas, SAB_CCR0, 0);
235 /* set basic configuration */
236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
237 uart_setreg(bas, SAB_CCR0, ccr0);
239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
243 uart_setreg(bas, SAB_CCR3, 0);
245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
250 SAB_RFC_RFTH_32CHAR);
253 sab82532_param(bas, baudrate, databits, stopbits, parity);
255 /* Clear interrupts. */
256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
257 uart_setreg(bas, SAB_IMR1, 0xff);
259 uart_getreg(bas, SAB_ISR0);
260 uart_getreg(bas, SAB_ISR1);
263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
271 sab82532_term(struct uart_bas *bas)
275 pvr = uart_getreg(bas, SAB_PVR);
278 pvr |= SAB_PVR_DTR_A;
281 pvr |= SAB_PVR_DTR_B;
284 uart_setreg(bas, SAB_PVR, pvr);
289 sab82532_putc(struct uart_bas *bas, int c)
293 /* 1/10th the time to transmit 1 character (estimate). */
294 delay = sab82532_delay(bas);
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
299 uart_setreg(bas, SAB_TIC, c);
301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
306 sab82532_rxready(struct uart_bas *bas)
309 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
313 sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
319 /* 1/10th the time to transmit 1 character (estimate). */
320 delay = sab82532_delay(bas);
322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
328 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
330 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
333 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
336 c = uart_getreg(bas, SAB_RFIFO);
339 /* Blow away everything left in the FIFO... */
340 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
342 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
351 * High-level UART interface.
353 struct sab82532_softc {
354 struct uart_softc base;
357 static int sab82532_bus_attach(struct uart_softc *);
358 static int sab82532_bus_detach(struct uart_softc *);
359 static int sab82532_bus_flush(struct uart_softc *, int);
360 static int sab82532_bus_getsig(struct uart_softc *);
361 static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
362 static int sab82532_bus_ipend(struct uart_softc *);
363 static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
364 static int sab82532_bus_probe(struct uart_softc *);
365 static int sab82532_bus_receive(struct uart_softc *);
366 static int sab82532_bus_setsig(struct uart_softc *, int);
367 static int sab82532_bus_transmit(struct uart_softc *);
368 static void sab82532_bus_grab(struct uart_softc *);
369 static void sab82532_bus_ungrab(struct uart_softc *);
371 static kobj_method_t sab82532_methods[] = {
372 KOBJMETHOD(uart_attach, sab82532_bus_attach),
373 KOBJMETHOD(uart_detach, sab82532_bus_detach),
374 KOBJMETHOD(uart_flush, sab82532_bus_flush),
375 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
376 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
377 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
378 KOBJMETHOD(uart_param, sab82532_bus_param),
379 KOBJMETHOD(uart_probe, sab82532_bus_probe),
380 KOBJMETHOD(uart_receive, sab82532_bus_receive),
381 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
382 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
383 KOBJMETHOD(uart_grab, sab82532_bus_grab),
384 KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab),
388 struct uart_class uart_sab82532_class = {
391 sizeof(struct sab82532_softc),
392 .uc_ops = &uart_sab82532_ops,
394 .uc_rclk = DEFAULT_RCLK,
398 #define SIGCHG(c, i, s, d) \
400 i |= (i & s) ? s : s | d; \
402 i = (i & s) ? (i & ~s) | d : i; \
406 sab82532_bus_attach(struct uart_softc *sc)
408 struct uart_bas *bas;
412 if (sc->sc_sysdev == NULL)
413 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
415 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
417 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
418 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
419 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
422 if (sc->sc_sysdev == NULL)
423 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
424 (void)sab82532_bus_getsig(sc);
429 sab82532_bus_detach(struct uart_softc *sc)
431 struct uart_bas *bas;
434 uart_setreg(bas, SAB_IMR0, 0xff);
435 uart_setreg(bas, SAB_IMR1, 0xff);
437 uart_getreg(bas, SAB_ISR0);
438 uart_getreg(bas, SAB_ISR1);
440 uart_setreg(bas, SAB_CCR0, 0);
446 sab82532_bus_flush(struct uart_softc *sc, int what)
449 uart_lock(sc->sc_hwmtx);
450 sab82532_flush(&sc->sc_bas, what);
451 uart_unlock(sc->sc_hwmtx);
456 sab82532_bus_getsig(struct uart_softc *sc)
458 struct uart_bas *bas;
459 uint32_t new, old, sig;
460 uint8_t pvr, star, vstr;
466 uart_lock(sc->sc_hwmtx);
467 star = uart_getreg(bas, SAB_STAR);
468 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
469 vstr = uart_getreg(bas, SAB_VSTR);
470 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
471 pvr = ~uart_getreg(bas, SAB_PVR);
474 pvr &= SAB_PVR_DSR_A;
477 pvr &= SAB_PVR_DSR_B;
480 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
481 uart_unlock(sc->sc_hwmtx);
482 new = sig & ~SER_MASK_DELTA;
483 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
488 sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
490 struct uart_bas *bas;
496 uart_lock(sc->sc_hwmtx);
498 case UART_IOCTL_BREAK:
499 dafo = uart_getreg(bas, SAB_DAFO);
501 dafo |= SAB_DAFO_XBRK;
503 dafo &= ~SAB_DAFO_XBRK;
504 uart_setreg(bas, SAB_DAFO, dafo);
507 case UART_IOCTL_IFLOW:
508 mode = uart_getreg(bas, SAB_MODE);
510 mode &= ~SAB_MODE_RTS;
511 mode |= SAB_MODE_FRTS;
513 mode |= SAB_MODE_RTS;
514 mode &= ~SAB_MODE_FRTS;
516 uart_setreg(bas, SAB_MODE, mode);
519 case UART_IOCTL_OFLOW:
520 mode = uart_getreg(bas, SAB_MODE);
522 mode &= ~SAB_MODE_FCTS;
524 mode |= SAB_MODE_FCTS;
525 uart_setreg(bas, SAB_MODE, mode);
532 uart_unlock(sc->sc_hwmtx);
537 sab82532_bus_ipend(struct uart_softc *sc)
539 struct uart_bas *bas;
544 uart_lock(sc->sc_hwmtx);
545 isr0 = uart_getreg(bas, SAB_ISR0);
546 isr1 = uart_getreg(bas, SAB_ISR1);
548 if (isr0 & SAB_ISR0_TIME) {
549 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
551 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
554 uart_unlock(sc->sc_hwmtx);
557 if (isr1 & SAB_ISR1_BRKT)
558 ipend |= SER_INT_BREAK;
559 if (isr0 & SAB_ISR0_RFO)
560 ipend |= SER_INT_OVERRUN;
561 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
562 ipend |= SER_INT_RXREADY;
563 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
564 ipend |= SER_INT_SIGCHG;
565 if (isr1 & SAB_ISR1_ALLS)
566 ipend |= SER_INT_TXIDLE;
572 sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
573 int stopbits, int parity)
575 struct uart_bas *bas;
579 uart_lock(sc->sc_hwmtx);
580 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
581 uart_unlock(sc->sc_hwmtx);
586 sab82532_bus_probe(struct uart_softc *sc)
593 error = sab82532_probe(&sc->sc_bas);
597 sc->sc_rxfifosz = 32;
598 sc->sc_txfifosz = 32;
600 ch = sc->sc_bas.chan - 1 + 'A';
602 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
611 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
619 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
620 device_set_desc_copy(sc->sc_dev, buf);
625 sab82532_bus_receive(struct uart_softc *sc)
627 struct uart_bas *bas;
632 uart_lock(sc->sc_hwmtx);
633 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
634 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
637 for (i = 0; i < rbcl; i += 2) {
638 if (uart_rx_full(sc)) {
639 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
642 xc = uart_getreg(bas, SAB_RFIFO);
643 s = uart_getreg(bas, SAB_RFIFO + 1);
644 if (s & SAB_RSTAT_FE)
645 xc |= UART_STAT_FRAMERR;
646 if (s & SAB_RSTAT_PE)
647 xc |= UART_STAT_PARERR;
652 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
654 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
656 uart_unlock(sc->sc_hwmtx);
661 sab82532_bus_setsig(struct uart_softc *sc, int sig)
663 struct uart_bas *bas;
671 if (sig & SER_DDTR) {
672 SIGCHG(sig & SER_DTR, new, SER_DTR,
675 if (sig & SER_DRTS) {
676 SIGCHG(sig & SER_RTS, new, SER_RTS,
679 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
681 uart_lock(sc->sc_hwmtx);
683 pvr = uart_getreg(bas, SAB_PVR);
687 pvr &= ~SAB_PVR_DTR_A;
689 pvr |= SAB_PVR_DTR_A;
693 pvr &= ~SAB_PVR_DTR_B;
695 pvr |= SAB_PVR_DTR_B;
698 uart_setreg(bas, SAB_PVR, pvr);
701 mode = uart_getreg(bas, SAB_MODE);
703 mode &= ~SAB_MODE_FRTS;
705 mode |= SAB_MODE_FRTS;
706 uart_setreg(bas, SAB_MODE, mode);
708 uart_unlock(sc->sc_hwmtx);
713 sab82532_bus_transmit(struct uart_softc *sc)
715 struct uart_bas *bas;
719 uart_lock(sc->sc_hwmtx);
720 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
722 for (i = 0; i < sc->sc_txdatasz; i++)
723 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
725 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
727 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
729 uart_unlock(sc->sc_hwmtx);
734 sab82532_bus_grab(struct uart_softc *sc)
736 struct uart_bas *bas;
740 imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */
741 uart_lock(sc->sc_hwmtx);
742 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
744 uart_unlock(sc->sc_hwmtx);
748 sab82532_bus_ungrab(struct uart_softc *sc)
750 struct uart_bas *bas;
754 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
756 uart_lock(sc->sc_hwmtx);
757 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
759 uart_unlock(sc->sc_hwmtx);