2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <machine/bus.h>
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_bus.h>
42 #include <dev/ic/sab82532.h>
46 #define DEFAULT_RCLK 29491200
49 * NOTE: To allow us to read the baudrate divisor from the chip, we
50 * copy the value written to the write-only BGR register to an unused
51 * read-write register. We use TCR for that.
55 sab82532_delay(struct uart_bas *bas)
60 bgr = uart_getreg(bas, SAB_TCR);
61 ccr2 = uart_getreg(bas, SAB_CCR2);
63 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
66 /* 1/10th the time to transmit 1 character (estimate). */
67 return (16000000 * divisor / bas->rclk);
71 sab82532_divisor(int rclk, int baudrate)
73 int act_baud, act_div, divisor;
79 divisor = (rclk / (baudrate << 3) + 1) >> 1;
80 if (divisor < 2 || divisor >= 1048576)
83 /* Find the best (N+1,M) pair. */
84 for (m = 1; m < 15; m++) {
89 act_baud = rclk / (act_div << 4);
91 /* 10 times error in percent: */
92 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
94 /* 3.0% maximum error tolerance: */
95 if (error < -30 || error > 30)
99 return ((n - 1) | (m << 6));
106 sab82532_flush(struct uart_bas *bas, int what)
109 if (what & UART_FLUSH_TRANSMITTER) {
110 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
112 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
115 if (what & UART_FLUSH_RECEIVER) {
116 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
118 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
124 sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
131 dafo = SAB_DAFO_CHL_CS8;
132 else if (databits == 7)
133 dafo = SAB_DAFO_CHL_CS7;
134 else if (databits == 6)
135 dafo = SAB_DAFO_CHL_CS6;
137 dafo = SAB_DAFO_CHL_CS5;
139 dafo |= SAB_DAFO_STOP;
141 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
142 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
143 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
144 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
145 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
146 default: return (EINVAL);
151 divisor = sab82532_divisor(bas->rclk, baudrate);
154 uart_setreg(bas, SAB_BGR, divisor & 0xff);
156 /* Allow reading the (n-1,m) tuple from the chip. */
157 uart_setreg(bas, SAB_TCR, divisor & 0xff);
159 ccr2 = uart_getreg(bas, SAB_CCR2);
160 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
161 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
162 uart_setreg(bas, SAB_CCR2, ccr2);
166 uart_setreg(bas, SAB_DAFO, dafo);
172 * Low-level UART interface.
174 static int sab82532_probe(struct uart_bas *bas);
175 static void sab82532_init(struct uart_bas *bas, int, int, int, int);
176 static void sab82532_term(struct uart_bas *bas);
177 static void sab82532_putc(struct uart_bas *bas, int);
178 static int sab82532_rxready(struct uart_bas *bas);
179 static int sab82532_getc(struct uart_bas *bas, struct mtx *);
181 static struct uart_ops uart_sab82532_ops = {
182 .probe = sab82532_probe,
183 .init = sab82532_init,
184 .term = sab82532_term,
185 .putc = sab82532_putc,
186 .rxready = sab82532_rxready,
187 .getc = sab82532_getc,
191 sab82532_probe(struct uart_bas *bas)
198 sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
204 bas->rclk = DEFAULT_RCLK;
207 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
208 * Pin 4 is magical, meaning that I don't know what it does, but
209 * it too has to be set to output.
211 uart_setreg(bas, SAB_PCR,
212 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
214 /* Disable port interrupts. */
215 uart_setreg(bas, SAB_PIM, 0xff);
217 /* Interrupts are active low. */
218 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
221 pvr = uart_getreg(bas, SAB_PVR);
224 pvr &= ~SAB_PVR_DTR_A;
227 pvr &= ~SAB_PVR_DTR_B;
230 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
234 uart_setreg(bas, SAB_CCR0, 0);
237 /* set basic configuration */
238 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
239 uart_setreg(bas, SAB_CCR0, ccr0);
241 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
243 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
245 uart_setreg(bas, SAB_CCR3, 0);
247 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
249 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
251 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
252 SAB_RFC_RFTH_32CHAR);
255 sab82532_param(bas, baudrate, databits, stopbits, parity);
257 /* Clear interrupts. */
258 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
259 uart_setreg(bas, SAB_IMR1, 0xff);
261 uart_getreg(bas, SAB_ISR0);
262 uart_getreg(bas, SAB_ISR1);
265 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
268 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
273 sab82532_term(struct uart_bas *bas)
277 pvr = uart_getreg(bas, SAB_PVR);
280 pvr |= SAB_PVR_DTR_A;
283 pvr |= SAB_PVR_DTR_B;
286 uart_setreg(bas, SAB_PVR, pvr);
291 sab82532_putc(struct uart_bas *bas, int c)
295 /* 1/10th the time to transmit 1 character (estimate). */
296 delay = sab82532_delay(bas);
299 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
301 uart_setreg(bas, SAB_TIC, c);
303 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
308 sab82532_rxready(struct uart_bas *bas)
311 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
315 sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
321 /* 1/10th the time to transmit 1 character (estimate). */
322 delay = sab82532_delay(bas);
324 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
330 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
332 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
335 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
338 c = uart_getreg(bas, SAB_RFIFO);
341 /* Blow away everything left in the FIFO... */
342 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
344 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
353 * High-level UART interface.
355 struct sab82532_softc {
356 struct uart_softc base;
359 static int sab82532_bus_attach(struct uart_softc *);
360 static int sab82532_bus_detach(struct uart_softc *);
361 static int sab82532_bus_flush(struct uart_softc *, int);
362 static int sab82532_bus_getsig(struct uart_softc *);
363 static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
364 static int sab82532_bus_ipend(struct uart_softc *);
365 static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
366 static int sab82532_bus_probe(struct uart_softc *);
367 static int sab82532_bus_receive(struct uart_softc *);
368 static int sab82532_bus_setsig(struct uart_softc *, int);
369 static int sab82532_bus_transmit(struct uart_softc *);
370 static void sab82532_bus_grab(struct uart_softc *);
371 static void sab82532_bus_ungrab(struct uart_softc *);
373 static kobj_method_t sab82532_methods[] = {
374 KOBJMETHOD(uart_attach, sab82532_bus_attach),
375 KOBJMETHOD(uart_detach, sab82532_bus_detach),
376 KOBJMETHOD(uart_flush, sab82532_bus_flush),
377 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
378 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
379 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
380 KOBJMETHOD(uart_param, sab82532_bus_param),
381 KOBJMETHOD(uart_probe, sab82532_bus_probe),
382 KOBJMETHOD(uart_receive, sab82532_bus_receive),
383 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
384 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
385 KOBJMETHOD(uart_grab, sab82532_bus_grab),
386 KOBJMETHOD(uart_ungrab, sab82532_bus_ungrab),
390 struct uart_class uart_sab82532_class = {
393 sizeof(struct sab82532_softc),
394 .uc_ops = &uart_sab82532_ops,
396 .uc_rclk = DEFAULT_RCLK,
400 #define SIGCHG(c, i, s, d) \
402 i |= (i & s) ? s : s | d; \
404 i = (i & s) ? (i & ~s) | d : i; \
408 sab82532_bus_attach(struct uart_softc *sc)
410 struct uart_bas *bas;
414 if (sc->sc_sysdev == NULL)
415 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
417 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
419 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
420 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
421 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
424 if (sc->sc_sysdev == NULL)
425 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
426 (void)sab82532_bus_getsig(sc);
431 sab82532_bus_detach(struct uart_softc *sc)
433 struct uart_bas *bas;
436 uart_setreg(bas, SAB_IMR0, 0xff);
437 uart_setreg(bas, SAB_IMR1, 0xff);
439 uart_getreg(bas, SAB_ISR0);
440 uart_getreg(bas, SAB_ISR1);
442 uart_setreg(bas, SAB_CCR0, 0);
448 sab82532_bus_flush(struct uart_softc *sc, int what)
451 uart_lock(sc->sc_hwmtx);
452 sab82532_flush(&sc->sc_bas, what);
453 uart_unlock(sc->sc_hwmtx);
458 sab82532_bus_getsig(struct uart_softc *sc)
460 struct uart_bas *bas;
461 uint32_t new, old, sig;
462 uint8_t pvr, star, vstr;
468 uart_lock(sc->sc_hwmtx);
469 star = uart_getreg(bas, SAB_STAR);
470 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
471 vstr = uart_getreg(bas, SAB_VSTR);
472 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
473 pvr = ~uart_getreg(bas, SAB_PVR);
476 pvr &= SAB_PVR_DSR_A;
479 pvr &= SAB_PVR_DSR_B;
482 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
483 uart_unlock(sc->sc_hwmtx);
484 new = sig & ~SER_MASK_DELTA;
485 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
490 sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
492 struct uart_bas *bas;
498 uart_lock(sc->sc_hwmtx);
500 case UART_IOCTL_BREAK:
501 dafo = uart_getreg(bas, SAB_DAFO);
503 dafo |= SAB_DAFO_XBRK;
505 dafo &= ~SAB_DAFO_XBRK;
506 uart_setreg(bas, SAB_DAFO, dafo);
509 case UART_IOCTL_IFLOW:
510 mode = uart_getreg(bas, SAB_MODE);
512 mode &= ~SAB_MODE_RTS;
513 mode |= SAB_MODE_FRTS;
515 mode |= SAB_MODE_RTS;
516 mode &= ~SAB_MODE_FRTS;
518 uart_setreg(bas, SAB_MODE, mode);
521 case UART_IOCTL_OFLOW:
522 mode = uart_getreg(bas, SAB_MODE);
524 mode &= ~SAB_MODE_FCTS;
526 mode |= SAB_MODE_FCTS;
527 uart_setreg(bas, SAB_MODE, mode);
534 uart_unlock(sc->sc_hwmtx);
539 sab82532_bus_ipend(struct uart_softc *sc)
541 struct uart_bas *bas;
546 uart_lock(sc->sc_hwmtx);
547 isr0 = uart_getreg(bas, SAB_ISR0);
548 isr1 = uart_getreg(bas, SAB_ISR1);
550 if (isr0 & SAB_ISR0_TIME) {
551 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
553 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
556 uart_unlock(sc->sc_hwmtx);
559 if (isr1 & SAB_ISR1_BRKT)
560 ipend |= SER_INT_BREAK;
561 if (isr0 & SAB_ISR0_RFO)
562 ipend |= SER_INT_OVERRUN;
563 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
564 ipend |= SER_INT_RXREADY;
565 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
566 ipend |= SER_INT_SIGCHG;
567 if (isr1 & SAB_ISR1_ALLS)
568 ipend |= SER_INT_TXIDLE;
574 sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
575 int stopbits, int parity)
577 struct uart_bas *bas;
581 uart_lock(sc->sc_hwmtx);
582 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
583 uart_unlock(sc->sc_hwmtx);
588 sab82532_bus_probe(struct uart_softc *sc)
595 error = sab82532_probe(&sc->sc_bas);
599 sc->sc_rxfifosz = 32;
600 sc->sc_txfifosz = 32;
602 ch = sc->sc_bas.chan - 1 + 'A';
604 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
613 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
621 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
622 device_set_desc_copy(sc->sc_dev, buf);
627 sab82532_bus_receive(struct uart_softc *sc)
629 struct uart_bas *bas;
634 uart_lock(sc->sc_hwmtx);
635 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
636 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
639 for (i = 0; i < rbcl; i += 2) {
640 if (uart_rx_full(sc)) {
641 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
644 xc = uart_getreg(bas, SAB_RFIFO);
645 s = uart_getreg(bas, SAB_RFIFO + 1);
646 if (s & SAB_RSTAT_FE)
647 xc |= UART_STAT_FRAMERR;
648 if (s & SAB_RSTAT_PE)
649 xc |= UART_STAT_PARERR;
654 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
656 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
658 uart_unlock(sc->sc_hwmtx);
663 sab82532_bus_setsig(struct uart_softc *sc, int sig)
665 struct uart_bas *bas;
673 if (sig & SER_DDTR) {
674 SIGCHG(sig & SER_DTR, new, SER_DTR,
677 if (sig & SER_DRTS) {
678 SIGCHG(sig & SER_RTS, new, SER_RTS,
681 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
683 uart_lock(sc->sc_hwmtx);
685 pvr = uart_getreg(bas, SAB_PVR);
689 pvr &= ~SAB_PVR_DTR_A;
691 pvr |= SAB_PVR_DTR_A;
695 pvr &= ~SAB_PVR_DTR_B;
697 pvr |= SAB_PVR_DTR_B;
700 uart_setreg(bas, SAB_PVR, pvr);
703 mode = uart_getreg(bas, SAB_MODE);
705 mode &= ~SAB_MODE_FRTS;
707 mode |= SAB_MODE_FRTS;
708 uart_setreg(bas, SAB_MODE, mode);
710 uart_unlock(sc->sc_hwmtx);
715 sab82532_bus_transmit(struct uart_softc *sc)
717 struct uart_bas *bas;
721 uart_lock(sc->sc_hwmtx);
722 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
724 for (i = 0; i < sc->sc_txdatasz; i++)
725 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
727 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
729 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
731 uart_unlock(sc->sc_hwmtx);
736 sab82532_bus_grab(struct uart_softc *sc)
738 struct uart_bas *bas;
742 imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */
743 uart_lock(sc->sc_hwmtx);
744 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
746 uart_unlock(sc->sc_hwmtx);
750 sab82532_bus_ungrab(struct uart_softc *sc)
752 struct uart_bas *bas;
756 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
758 uart_lock(sc->sc_hwmtx);
759 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
761 uart_unlock(sc->sc_hwmtx);