2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/z8530.h>
44 #define DEFAULT_RCLK 307200
46 /* Multiplexed I/O. */
48 uart_setmreg(struct uart_bas *bas, int reg, int val)
51 uart_setreg(bas, REG_CTRL, reg);
53 uart_setreg(bas, REG_CTRL, val);
56 static __inline uint8_t
57 uart_getmreg(struct uart_bas *bas, int reg)
60 uart_setreg(bas, REG_CTRL, reg);
62 return (uart_getreg(bas, REG_CTRL));
66 z8530_divisor(int rclk, int baudrate)
68 int act_baud, divisor, error;
73 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
76 act_baud = rclk / 2 / (divisor + 2);
78 /* 10 times error in percent: */
79 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
81 /* 3.0% maximum error tolerance: */
82 if (error < -30 || error > 30)
89 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
90 int parity, uint8_t *tpcp)
93 uint8_t mpm, rpc, tpc;
97 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
102 } else if (databits == 7) {
105 } else if (databits == 6) {
112 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
114 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
115 case UART_PARITY_NONE: break;
116 case UART_PARITY_ODD: mpm |= MPM_PE; break;
117 default: return (EINVAL);
122 divisor = z8530_divisor(bas->rclk, baudrate);
125 uart_setmreg(bas, WR_TCL, divisor & 0xff);
127 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
131 uart_setmreg(bas, WR_RPC, rpc);
133 uart_setmreg(bas, WR_MPM, mpm);
135 uart_setmreg(bas, WR_TPC, tpc);
142 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
148 bas->rclk = DEFAULT_RCLK;
150 /* Assume we don't need to perform a full hardware reset. */
153 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
156 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
160 /* Set clock sources and enable BRG. */
161 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
162 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
164 /* Set data encoding. */
165 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
168 tpc = TPC_DTR | TPC_RTS;
169 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
174 * Low-level UART interface.
176 static int z8530_probe(struct uart_bas *bas);
177 static void z8530_init(struct uart_bas *bas, int, int, int, int);
178 static void z8530_term(struct uart_bas *bas);
179 static void z8530_putc(struct uart_bas *bas, int);
180 static int z8530_poll(struct uart_bas *bas);
181 static int z8530_getc(struct uart_bas *bas);
183 struct uart_ops uart_z8530_ops = {
184 .probe = z8530_probe,
193 z8530_probe(struct uart_bas *bas)
200 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
204 z8530_setup(bas, baudrate, databits, stopbits, parity);
208 z8530_term(struct uart_bas *bas)
213 z8530_putc(struct uart_bas *bas, int c)
216 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
218 uart_setreg(bas, REG_DATA, c);
223 z8530_poll(struct uart_bas *bas)
226 if (!(uart_getreg(bas, REG_CTRL) & BES_RXA))
228 return (uart_getreg(bas, REG_DATA));
232 z8530_getc(struct uart_bas *bas)
235 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA))
237 return (uart_getreg(bas, REG_DATA));
241 * High-level UART interface.
244 struct uart_softc base;
249 static int z8530_bus_attach(struct uart_softc *);
250 static int z8530_bus_detach(struct uart_softc *);
251 static int z8530_bus_flush(struct uart_softc *, int);
252 static int z8530_bus_getsig(struct uart_softc *);
253 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
254 static int z8530_bus_ipend(struct uart_softc *);
255 static int z8530_bus_param(struct uart_softc *, int, int, int, int);
256 static int z8530_bus_probe(struct uart_softc *);
257 static int z8530_bus_receive(struct uart_softc *);
258 static int z8530_bus_setsig(struct uart_softc *, int);
259 static int z8530_bus_transmit(struct uart_softc *);
261 static kobj_method_t z8530_methods[] = {
262 KOBJMETHOD(uart_attach, z8530_bus_attach),
263 KOBJMETHOD(uart_detach, z8530_bus_detach),
264 KOBJMETHOD(uart_flush, z8530_bus_flush),
265 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
266 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
267 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
268 KOBJMETHOD(uart_param, z8530_bus_param),
269 KOBJMETHOD(uart_probe, z8530_bus_probe),
270 KOBJMETHOD(uart_receive, z8530_bus_receive),
271 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
272 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
276 struct uart_class uart_z8530_class = {
279 sizeof(struct z8530_softc),
281 .uc_rclk = DEFAULT_RCLK
284 #define SIGCHG(c, i, s, d) \
286 i |= (i & s) ? s : s | d; \
288 i = (i & s) ? (i & ~s) | d : i; \
292 z8530_bus_attach(struct uart_softc *sc)
294 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
295 struct uart_bas *bas;
296 struct uart_devinfo *di;
299 if (sc->sc_sysdev != NULL) {
301 z8530->tpc = TPC_DTR|TPC_RTS;
302 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
303 di->parity, &z8530->tpc);
305 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
306 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
308 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE. */
313 (void)z8530_bus_getsig(sc);
315 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
317 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
319 uart_setmreg(bas, WR_IV, 0);
321 uart_setmreg(bas, WR_TPC, z8530->tpc);
323 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
329 z8530_bus_detach(struct uart_softc *sc)
336 z8530_bus_flush(struct uart_softc *sc, int what)
343 z8530_bus_getsig(struct uart_softc *sc)
345 uint32_t new, old, sig;
351 mtx_lock_spin(&sc->sc_hwmtx);
352 bes = uart_getmreg(&sc->sc_bas, RR_BES);
353 mtx_unlock_spin(&sc->sc_hwmtx);
354 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
355 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
356 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
357 new = sig & ~UART_SIGMASK_DELTA;
358 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
363 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
365 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
366 struct uart_bas *bas;
371 mtx_lock_spin(&sc->sc_hwmtx);
373 case UART_IOCTL_BREAK:
375 z8530->tpc |= TPC_BRK;
377 z8530->tpc &= ~TPC_BRK;
378 uart_setmreg(bas, WR_TPC, z8530->tpc);
385 mtx_unlock_spin(&sc->sc_hwmtx);
390 z8530_bus_ipend(struct uart_softc *sc)
392 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
393 struct uart_bas *bas;
396 uint8_t bes, ip, iv, src;
401 mtx_lock_spin(&sc->sc_hwmtx);
404 ip = uart_getmreg(bas, RR_IP);
406 case 2: /* XXX hack!!! */
407 iv = uart_getmreg(bas, RR_IV) & 0x0E;
409 case IV_TEB: ip = IP_TIA; break;
410 case IV_XSB: ip = IP_SIA; break;
411 case IV_RAB: ip = IP_RIA; break;
412 default: ip = 0; break;
421 ipend |= UART_IPEND_RXREADY;
424 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
427 ipend |= UART_IPEND_TXIDLE;
428 z8530->txidle = 0; /* Mask UART_IPEND_TXIDLE. */
433 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
435 bes = uart_getmreg(bas, RR_BES);
437 ipend |= UART_IPEND_BREAK;
439 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
440 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
441 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
442 if (sig & UART_SIGMASK_DELTA)
443 ipend |= UART_IPEND_SIGCHG;
444 src = uart_getmreg(bas, RR_SRC);
446 uart_setreg(bas, REG_CTRL, CR_RSTERR);
448 ipend |= UART_IPEND_OVERRUN;
453 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
457 mtx_unlock_spin(&sc->sc_hwmtx);
463 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
464 int stopbits, int parity)
466 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
469 mtx_lock_spin(&sc->sc_hwmtx);
470 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
472 mtx_unlock_spin(&sc->sc_hwmtx);
477 z8530_bus_probe(struct uart_softc *sc)
483 error = z8530_probe(&sc->sc_bas);
487 ch = sc->sc_bas.chan - 1 + 'A';
489 snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
490 device_set_desc_copy(sc->sc_dev, buf);
495 z8530_bus_receive(struct uart_softc *sc)
497 struct uart_bas *bas;
502 mtx_lock_spin(&sc->sc_hwmtx);
503 bes = uart_getmreg(bas, RR_BES);
504 while (bes & BES_RXA) {
505 if (uart_rx_full(sc)) {
506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
509 xc = uart_getreg(bas, REG_DATA);
511 src = uart_getmreg(bas, RR_SRC);
513 xc |= UART_STAT_FRAMERR;
515 xc |= UART_STAT_PARERR;
517 xc |= UART_STAT_OVERRUN;
519 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
520 uart_setreg(bas, REG_CTRL, CR_RSTERR);
523 bes = uart_getmreg(bas, RR_BES);
525 /* Discard everything left in the Rx FIFO. */
526 while (bes & BES_RXA) {
527 (void)uart_getreg(bas, REG_DATA);
529 src = uart_getmreg(bas, RR_SRC);
530 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
531 uart_setreg(bas, REG_CTRL, CR_RSTERR);
534 bes = uart_getmreg(bas, RR_BES);
536 mtx_unlock_spin(&sc->sc_hwmtx);
541 z8530_bus_setsig(struct uart_softc *sc, int sig)
543 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
544 struct uart_bas *bas;
551 if (sig & SER_DDTR) {
552 SIGCHG(sig & SER_DTR, new, SER_DTR,
555 if (sig & SER_DRTS) {
556 SIGCHG(sig & SER_RTS, new, SER_RTS,
559 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
561 mtx_lock_spin(&sc->sc_hwmtx);
563 z8530->tpc |= TPC_DTR;
565 z8530->tpc &= ~TPC_DTR;
567 z8530->tpc |= TPC_RTS;
569 z8530->tpc &= ~TPC_RTS;
570 uart_setmreg(bas, WR_TPC, z8530->tpc);
572 mtx_unlock_spin(&sc->sc_hwmtx);
577 z8530_bus_transmit(struct uart_softc *sc)
579 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
580 struct uart_bas *bas;
583 mtx_lock_spin(&sc->sc_hwmtx);
584 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
586 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
589 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE again. */
590 mtx_unlock_spin(&sc->sc_hwmtx);