2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <machine/bus.h>
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_bus.h>
42 #include <dev/ic/z8530.h>
46 #define DEFAULT_RCLK 307200
52 #define UART_PCLK MCB2_PCLK
55 /* Multiplexed I/O. */
57 uart_setmreg(struct uart_bas *bas, int reg, int val)
60 uart_setreg(bas, REG_CTRL, reg);
62 uart_setreg(bas, REG_CTRL, val);
65 static __inline uint8_t
66 uart_getmreg(struct uart_bas *bas, int reg)
69 uart_setreg(bas, REG_CTRL, reg);
71 return (uart_getreg(bas, REG_CTRL));
75 z8530_divisor(int rclk, int baudrate)
77 int act_baud, divisor, error;
82 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
83 if (divisor < 0 || divisor >= 65536)
85 act_baud = rclk / 2 / (divisor + 2);
87 /* 10 times error in percent: */
88 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
90 /* 3.0% maximum error tolerance: */
91 if (error < -30 || error > 30)
98 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
99 int parity, uint8_t *tpcp)
102 uint8_t mpm, rpc, tpc;
106 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
111 } else if (databits == 7) {
114 } else if (databits == 6) {
121 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
123 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
124 case UART_PARITY_NONE: break;
125 case UART_PARITY_ODD: mpm |= MPM_PE; break;
126 default: return (EINVAL);
130 divisor = z8530_divisor(bas->rclk, baudrate);
136 uart_setmreg(bas, WR_MCB2, UART_PCLK);
140 uart_setmreg(bas, WR_TCL, divisor & 0xff);
142 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
146 uart_setmreg(bas, WR_RPC, rpc);
148 uart_setmreg(bas, WR_MPM, mpm);
150 uart_setmreg(bas, WR_TPC, tpc);
152 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
159 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
165 bas->rclk = DEFAULT_RCLK;
167 /* Assume we don't need to perform a full hardware reset. */
170 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
173 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
177 /* Set clock sources. */
178 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
179 uart_setmreg(bas, WR_MCB2, UART_PCLK);
181 /* Set data encoding. */
182 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
185 tpc = TPC_DTR | TPC_RTS;
186 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
191 * Low-level UART interface.
193 static int z8530_probe(struct uart_bas *bas);
194 static void z8530_init(struct uart_bas *bas, int, int, int, int);
195 static void z8530_term(struct uart_bas *bas);
196 static void z8530_putc(struct uart_bas *bas, int);
197 static int z8530_rxready(struct uart_bas *bas);
198 static int z8530_getc(struct uart_bas *bas, struct mtx *);
200 static struct uart_ops uart_z8530_ops = {
201 .probe = z8530_probe,
205 .rxready = z8530_rxready,
210 z8530_probe(struct uart_bas *bas)
217 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
221 z8530_setup(bas, baudrate, databits, stopbits, parity);
225 z8530_term(struct uart_bas *bas)
230 z8530_putc(struct uart_bas *bas, int c)
233 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
235 uart_setreg(bas, REG_DATA, c);
240 z8530_rxready(struct uart_bas *bas)
243 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
247 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
253 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
259 c = uart_getreg(bas, REG_DATA);
267 * High-level UART interface.
270 struct uart_softc base;
275 static int z8530_bus_attach(struct uart_softc *);
276 static int z8530_bus_detach(struct uart_softc *);
277 static int z8530_bus_flush(struct uart_softc *, int);
278 static int z8530_bus_getsig(struct uart_softc *);
279 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
280 static int z8530_bus_ipend(struct uart_softc *);
281 static int z8530_bus_param(struct uart_softc *, int, int, int, int);
282 static int z8530_bus_probe(struct uart_softc *);
283 static int z8530_bus_receive(struct uart_softc *);
284 static int z8530_bus_setsig(struct uart_softc *, int);
285 static int z8530_bus_transmit(struct uart_softc *);
286 static void z8530_bus_grab(struct uart_softc *);
287 static void z8530_bus_ungrab(struct uart_softc *);
289 static kobj_method_t z8530_methods[] = {
290 KOBJMETHOD(uart_attach, z8530_bus_attach),
291 KOBJMETHOD(uart_detach, z8530_bus_detach),
292 KOBJMETHOD(uart_flush, z8530_bus_flush),
293 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
294 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
295 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
296 KOBJMETHOD(uart_param, z8530_bus_param),
297 KOBJMETHOD(uart_probe, z8530_bus_probe),
298 KOBJMETHOD(uart_receive, z8530_bus_receive),
299 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
300 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
301 KOBJMETHOD(uart_grab, z8530_bus_grab),
302 KOBJMETHOD(uart_ungrab, z8530_bus_ungrab),
306 struct uart_class uart_z8530_class = {
309 sizeof(struct z8530_softc),
310 .uc_ops = &uart_z8530_ops,
312 .uc_rclk = DEFAULT_RCLK,
316 #define SIGCHG(c, i, s, d) \
318 i |= (i & s) ? s : s | d; \
320 i = (i & s) ? (i & ~s) | d : i; \
324 z8530_bus_attach(struct uart_softc *sc)
326 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
327 struct uart_bas *bas;
328 struct uart_devinfo *di;
331 if (sc->sc_sysdev != NULL) {
333 z8530->tpc = TPC_DTR|TPC_RTS;
334 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
335 di->parity, &z8530->tpc);
337 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
338 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
340 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
342 (void)z8530_bus_getsig(sc);
344 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
346 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
348 uart_setmreg(bas, WR_IV, 0);
350 uart_setmreg(bas, WR_TPC, z8530->tpc);
352 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
358 z8530_bus_detach(struct uart_softc *sc)
365 z8530_bus_flush(struct uart_softc *sc, int what)
372 z8530_bus_getsig(struct uart_softc *sc)
374 uint32_t new, old, sig;
380 uart_lock(sc->sc_hwmtx);
381 bes = uart_getmreg(&sc->sc_bas, RR_BES);
382 uart_unlock(sc->sc_hwmtx);
383 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
384 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
385 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
386 new = sig & ~SER_MASK_DELTA;
387 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
392 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
394 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
395 struct uart_bas *bas;
396 int baudrate, divisor, error;
400 uart_lock(sc->sc_hwmtx);
402 case UART_IOCTL_BREAK:
404 z8530->tpc |= TPC_BRK;
406 z8530->tpc &= ~TPC_BRK;
407 uart_setmreg(bas, WR_TPC, z8530->tpc);
410 case UART_IOCTL_BAUD:
411 divisor = uart_getmreg(bas, RR_TCH);
412 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
413 baudrate = bas->rclk / 2 / (divisor + 2);
414 *(int*)data = baudrate;
420 uart_unlock(sc->sc_hwmtx);
425 z8530_bus_ipend(struct uart_softc *sc)
427 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
428 struct uart_bas *bas;
431 uint8_t bes, ip, iv, src;
436 uart_lock(sc->sc_hwmtx);
439 ip = uart_getmreg(bas, RR_IP);
441 case 2: /* XXX hack!!! */
442 iv = uart_getmreg(bas, RR_IV) & 0x0E;
444 case IV_TEB: ip = IP_TIA; break;
445 case IV_XSB: ip = IP_SIA; break;
446 case IV_RAB: ip = IP_RIA; break;
447 default: ip = 0; break;
456 ipend |= SER_INT_RXREADY;
459 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
462 ipend |= SER_INT_TXIDLE;
463 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */
468 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
470 bes = uart_getmreg(bas, RR_BES);
472 ipend |= SER_INT_BREAK;
474 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
475 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
476 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
477 if (sig & SER_MASK_DELTA)
478 ipend |= SER_INT_SIGCHG;
479 src = uart_getmreg(bas, RR_SRC);
481 uart_setreg(bas, REG_CTRL, CR_RSTERR);
483 ipend |= SER_INT_OVERRUN;
488 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
492 uart_unlock(sc->sc_hwmtx);
498 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
499 int stopbits, int parity)
501 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
504 uart_lock(sc->sc_hwmtx);
505 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
507 uart_unlock(sc->sc_hwmtx);
512 z8530_bus_probe(struct uart_softc *sc)
518 error = z8530_probe(&sc->sc_bas);
525 ch = sc->sc_bas.chan - 1 + 'A';
527 snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
528 device_set_desc_copy(sc->sc_dev, buf);
533 z8530_bus_receive(struct uart_softc *sc)
535 struct uart_bas *bas;
540 uart_lock(sc->sc_hwmtx);
541 bes = uart_getmreg(bas, RR_BES);
542 while (bes & BES_RXA) {
543 if (uart_rx_full(sc)) {
544 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
547 xc = uart_getreg(bas, REG_DATA);
549 src = uart_getmreg(bas, RR_SRC);
551 xc |= UART_STAT_FRAMERR;
553 xc |= UART_STAT_PARERR;
555 xc |= UART_STAT_OVERRUN;
557 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
558 uart_setreg(bas, REG_CTRL, CR_RSTERR);
561 bes = uart_getmreg(bas, RR_BES);
563 /* Discard everything left in the Rx FIFO. */
564 while (bes & BES_RXA) {
565 (void)uart_getreg(bas, REG_DATA);
567 src = uart_getmreg(bas, RR_SRC);
568 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
569 uart_setreg(bas, REG_CTRL, CR_RSTERR);
572 bes = uart_getmreg(bas, RR_BES);
574 uart_unlock(sc->sc_hwmtx);
579 z8530_bus_setsig(struct uart_softc *sc, int sig)
581 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
582 struct uart_bas *bas;
589 if (sig & SER_DDTR) {
590 SIGCHG(sig & SER_DTR, new, SER_DTR,
593 if (sig & SER_DRTS) {
594 SIGCHG(sig & SER_RTS, new, SER_RTS,
597 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
599 uart_lock(sc->sc_hwmtx);
601 z8530->tpc |= TPC_DTR;
603 z8530->tpc &= ~TPC_DTR;
605 z8530->tpc |= TPC_RTS;
607 z8530->tpc &= ~TPC_RTS;
608 uart_setmreg(bas, WR_TPC, z8530->tpc);
610 uart_unlock(sc->sc_hwmtx);
615 z8530_bus_transmit(struct uart_softc *sc)
617 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
618 struct uart_bas *bas;
621 uart_lock(sc->sc_hwmtx);
622 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
624 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
627 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
628 uart_unlock(sc->sc_hwmtx);
633 z8530_bus_grab(struct uart_softc *sc)
635 struct uart_bas *bas;
638 uart_lock(sc->sc_hwmtx);
639 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE);
641 uart_unlock(sc->sc_hwmtx);
645 z8530_bus_ungrab(struct uart_softc *sc)
647 struct uart_bas *bas;
650 uart_lock(sc->sc_hwmtx);
651 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
653 uart_unlock(sc->sc_hwmtx);