1 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
36 * Effort sponsored in part by the Defense Advanced Research Projects
37 * Agency (DARPA) and Air Force Research Laboratory, Air Force
38 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
48 #include "opt_ubsec.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/endian.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
71 #include <crypto/sha1.h>
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/cryptosoft.h>
75 #include <sys/random.h>
78 #include "cryptodev_if.h"
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcireg.h>
83 /* grr, #defines for gratuitous incompatibility in queue.h */
84 #define SIMPLEQ_HEAD STAILQ_HEAD
85 #define SIMPLEQ_ENTRY STAILQ_ENTRY
86 #define SIMPLEQ_INIT STAILQ_INIT
87 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
88 #define SIMPLEQ_EMPTY STAILQ_EMPTY
89 #define SIMPLEQ_FIRST STAILQ_FIRST
90 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
91 #define SIMPLEQ_FOREACH STAILQ_FOREACH
92 /* ditto for endian.h */
93 #define letoh16(x) le16toh(x)
94 #define letoh32(x) le32toh(x)
97 #include <dev/rndtest/rndtest.h>
99 #include <dev/ubsec/ubsecreg.h>
100 #include <dev/ubsec/ubsecvar.h>
103 * Prototypes and count for the pci_device structure
105 static int ubsec_probe(device_t);
106 static int ubsec_attach(device_t);
107 static int ubsec_detach(device_t);
108 static int ubsec_suspend(device_t);
109 static int ubsec_resume(device_t);
110 static int ubsec_shutdown(device_t);
112 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
113 static int ubsec_freesession(device_t, u_int64_t);
114 static int ubsec_process(device_t, struct cryptop *, int);
115 static int ubsec_kprocess(device_t, struct cryptkop *, int);
117 static device_method_t ubsec_methods[] = {
118 /* Device interface */
119 DEVMETHOD(device_probe, ubsec_probe),
120 DEVMETHOD(device_attach, ubsec_attach),
121 DEVMETHOD(device_detach, ubsec_detach),
122 DEVMETHOD(device_suspend, ubsec_suspend),
123 DEVMETHOD(device_resume, ubsec_resume),
124 DEVMETHOD(device_shutdown, ubsec_shutdown),
126 /* crypto device methods */
127 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
128 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
129 DEVMETHOD(cryptodev_process, ubsec_process),
130 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
134 static driver_t ubsec_driver = {
137 sizeof (struct ubsec_softc)
139 static devclass_t ubsec_devclass;
141 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
142 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
144 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
147 static void ubsec_intr(void *);
148 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
149 static void ubsec_feed(struct ubsec_softc *);
150 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
151 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
152 static int ubsec_feed2(struct ubsec_softc *);
153 static void ubsec_rng(void *);
154 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
155 struct ubsec_dma_alloc *, int);
156 #define ubsec_dma_sync(_dma, _flags) \
157 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
158 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
159 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
161 static void ubsec_reset_board(struct ubsec_softc *sc);
162 static void ubsec_init_board(struct ubsec_softc *sc);
163 static void ubsec_init_pciregs(device_t dev);
164 static void ubsec_totalreset(struct ubsec_softc *sc);
166 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
168 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
169 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
170 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
171 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
172 static int ubsec_ksigbits(struct crparam *);
173 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
174 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
176 static SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0,
177 "Broadcom driver parameters");
180 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
181 static void ubsec_dump_mcr(struct ubsec_mcr *);
182 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
184 static int ubsec_debug = 0;
185 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
186 0, "control debugging msgs");
189 #define READ_REG(sc,r) \
190 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
192 #define WRITE_REG(sc,reg,val) \
193 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
195 #define SWAP32(x) (x) = htole32(ntohl((x)))
196 #define HTOLE32(x) (x) = htole32(x)
198 struct ubsec_stats ubsecstats;
199 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
200 ubsec_stats, "driver statistics");
203 ubsec_probe(device_t dev)
205 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
206 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
207 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
208 return (BUS_PROBE_DEFAULT);
209 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
210 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
211 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
212 return (BUS_PROBE_DEFAULT);
213 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
214 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
221 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
223 return (BUS_PROBE_DEFAULT);
228 ubsec_partname(struct ubsec_softc *sc)
230 /* XXX sprintf numbers when not decoded */
231 switch (pci_get_vendor(sc->sc_dev)) {
232 case PCI_VENDOR_BROADCOM:
233 switch (pci_get_device(sc->sc_dev)) {
234 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
235 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
236 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
237 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
238 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
239 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
240 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
241 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
243 return "Broadcom unknown-part";
244 case PCI_VENDOR_BLUESTEEL:
245 switch (pci_get_device(sc->sc_dev)) {
246 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
248 return "Bluesteel unknown-part";
250 switch (pci_get_device(sc->sc_dev)) {
251 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
252 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
254 return "Sun unknown-part";
256 return "Unknown-vendor unknown-part";
260 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
262 /* MarkM: FIX!! Check that this does not swamp the harvester! */
263 random_harvest_queue(buf, count, count*NBBY/2, RANDOM_PURE_UBSEC);
267 ubsec_attach(device_t dev)
269 struct ubsec_softc *sc = device_get_softc(dev);
270 struct ubsec_dma *dmap;
274 bzero(sc, sizeof (*sc));
277 SIMPLEQ_INIT(&sc->sc_queue);
278 SIMPLEQ_INIT(&sc->sc_qchip);
279 SIMPLEQ_INIT(&sc->sc_queue2);
280 SIMPLEQ_INIT(&sc->sc_qchip2);
281 SIMPLEQ_INIT(&sc->sc_q2free);
283 /* XXX handle power management */
285 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
287 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
288 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
291 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
294 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
296 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
297 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
298 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
299 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
301 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
302 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
305 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
306 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
307 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
308 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
309 /* NB: the 5821/5822 defines some additional status bits */
310 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
311 BS_STAT_MCR2_ALLEMPTY;
312 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
313 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
316 pci_enable_busmaster(dev);
319 * Setup memory-mapping of PCI registers.
322 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
324 if (sc->sc_sr == NULL) {
325 device_printf(dev, "cannot map register space\n");
328 sc->sc_st = rman_get_bustag(sc->sc_sr);
329 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
332 * Arrange interrupt line.
335 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
336 RF_SHAREABLE|RF_ACTIVE);
337 if (sc->sc_irq == NULL) {
338 device_printf(dev, "could not map interrupt\n");
342 * NB: Network code assumes we are blocked with splimp()
343 * so make sure the IRQ is mapped appropriately.
345 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
346 NULL, ubsec_intr, sc, &sc->sc_ih)) {
347 device_printf(dev, "could not establish interrupt\n");
351 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
352 if (sc->sc_cid < 0) {
353 device_printf(dev, "could not get crypto driver id\n");
358 * Setup DMA descriptor area.
360 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
361 1, 0, /* alignment, bounds */
362 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
363 BUS_SPACE_MAXADDR, /* highaddr */
364 NULL, NULL, /* filter, filterarg */
365 0x3ffff, /* maxsize */
366 UBS_MAX_SCATTER, /* nsegments */
367 0xffff, /* maxsegsize */
368 BUS_DMA_ALLOCNOW, /* flags */
369 NULL, NULL, /* lockfunc, lockarg */
371 device_printf(dev, "cannot allocate DMA tag\n");
374 SIMPLEQ_INIT(&sc->sc_freequeue);
376 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
379 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
382 device_printf(dev, "cannot allocate queue buffers\n");
386 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
387 &dmap->d_alloc, 0)) {
388 device_printf(dev, "cannot allocate dma buffers\n");
392 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
395 sc->sc_queuea[i] = q;
397 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
399 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
400 "mcr1 operations", MTX_DEF);
401 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
402 "mcr1 free q", MTX_DEF);
404 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
406 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
407 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
408 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
409 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
412 * Reset Broadcom chip
414 ubsec_reset_board(sc);
417 * Init Broadcom specific PCI settings
419 ubsec_init_pciregs(dev);
424 ubsec_init_board(sc);
427 if (sc->sc_flags & UBS_FLAGS_RNG) {
428 sc->sc_statmask |= BS_STAT_MCR2_DONE;
430 sc->sc_rndtest = rndtest_attach(dev);
432 sc->sc_harvest = rndtest_harvest;
434 sc->sc_harvest = default_harvest;
436 sc->sc_harvest = default_harvest;
439 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
440 &sc->sc_rng.rng_q.q_mcr, 0))
443 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
444 &sc->sc_rng.rng_q.q_ctx, 0)) {
445 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
449 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
450 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
452 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
457 sc->sc_rnghz = hz / 100;
460 callout_init(&sc->sc_rngto, 1);
461 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
465 #endif /* UBSEC_NO_RNG */
466 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
467 "mcr2 operations", MTX_DEF);
469 if (sc->sc_flags & UBS_FLAGS_KEY) {
470 sc->sc_statmask |= BS_STAT_MCR2_DONE;
472 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
474 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
479 crypto_unregister_all(sc->sc_cid);
481 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
485 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
491 * Detach a device that successfully probed.
494 ubsec_detach(device_t dev)
496 struct ubsec_softc *sc = device_get_softc(dev);
498 /* XXX wait/abort active ops */
500 /* disable interrupts */
501 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
502 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
504 callout_stop(&sc->sc_rngto);
506 crypto_unregister_all(sc->sc_cid);
510 rndtest_detach(sc->sc_rndtest);
513 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
516 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
517 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
518 ubsec_dma_free(sc, &q->q_dma->d_alloc);
521 mtx_destroy(&sc->sc_mcr1lock);
522 mtx_destroy(&sc->sc_freeqlock);
524 if (sc->sc_flags & UBS_FLAGS_RNG) {
525 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
526 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
527 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
529 #endif /* UBSEC_NO_RNG */
530 mtx_destroy(&sc->sc_mcr2lock);
532 bus_generic_detach(dev);
533 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
534 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
536 bus_dma_tag_destroy(sc->sc_dmat);
537 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
543 * Stop all chip i/o so that the kernel's probe routines don't
544 * get confused by errant DMAs when rebooting.
547 ubsec_shutdown(device_t dev)
550 ubsec_stop(device_get_softc(dev));
556 * Device suspend routine.
559 ubsec_suspend(device_t dev)
561 struct ubsec_softc *sc = device_get_softc(dev);
564 /* XXX stop the device and save PCI settings */
566 sc->sc_suspended = 1;
572 ubsec_resume(device_t dev)
574 struct ubsec_softc *sc = device_get_softc(dev);
577 /* XXX retore PCI settings and start the device */
579 sc->sc_suspended = 0;
584 * UBSEC Interrupt routine
587 ubsec_intr(void *arg)
589 struct ubsec_softc *sc = arg;
590 volatile u_int32_t stat;
592 struct ubsec_dma *dmap;
595 stat = READ_REG(sc, BS_STAT);
596 stat &= sc->sc_statmask;
600 WRITE_REG(sc, BS_STAT, stat); /* IACK */
603 * Check to see if we have any packets waiting for us
605 if ((stat & BS_STAT_MCR1_DONE)) {
606 mtx_lock(&sc->sc_mcr1lock);
607 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
608 q = SIMPLEQ_FIRST(&sc->sc_qchip);
611 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
614 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
616 npkts = q->q_nstacked_mcrs;
617 sc->sc_nqchip -= 1+npkts;
619 * search for further sc_qchip ubsec_q's that share
620 * the same MCR, and complete them too, they must be
623 for (i = 0; i < npkts; i++) {
624 if(q->q_stacked_mcr[i]) {
625 ubsec_callback(sc, q->q_stacked_mcr[i]);
630 ubsec_callback(sc, q);
633 * Don't send any more packet to chip if there has been
636 if (!(stat & BS_STAT_DMAERR))
638 mtx_unlock(&sc->sc_mcr1lock);
642 * Check to see if we have any key setups/rng's waiting for us
644 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
645 (stat & BS_STAT_MCR2_DONE)) {
647 struct ubsec_mcr *mcr;
649 mtx_lock(&sc->sc_mcr2lock);
650 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
651 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
653 ubsec_dma_sync(&q2->q_mcr,
654 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
656 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
657 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
658 ubsec_dma_sync(&q2->q_mcr,
659 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
662 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
663 ubsec_callback2(sc, q2);
665 * Don't send any more packet to chip if there has been
668 if (!(stat & BS_STAT_DMAERR))
671 mtx_unlock(&sc->sc_mcr2lock);
675 * Check to see if we got any DMA Error
677 if (stat & BS_STAT_DMAERR) {
680 volatile u_int32_t a = READ_REG(sc, BS_ERR);
682 printf("dmaerr %s@%08x\n",
683 (a & BS_ERR_READ) ? "read" : "write",
686 #endif /* UBSEC_DEBUG */
687 ubsecstats.hst_dmaerr++;
688 mtx_lock(&sc->sc_mcr1lock);
689 ubsec_totalreset(sc);
691 mtx_unlock(&sc->sc_mcr1lock);
694 if (sc->sc_needwakeup) { /* XXX check high watermark */
697 mtx_lock(&sc->sc_freeqlock);
698 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
701 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
703 #endif /* UBSEC_DEBUG */
704 sc->sc_needwakeup &= ~wakeup;
705 mtx_unlock(&sc->sc_freeqlock);
706 crypto_unblock(sc->sc_cid, wakeup);
711 * ubsec_feed() - aggregate and post requests to chip
714 ubsec_feed(struct ubsec_softc *sc)
716 struct ubsec_q *q, *q2;
722 * Decide how many ops to combine in a single MCR. We cannot
723 * aggregate more than UBS_MAX_AGGR because this is the number
724 * of slots defined in the data structure. Note that
725 * aggregation only happens if ops are marked batch'able.
726 * Aggregating ops reduces the number of interrupts to the host
727 * but also (potentially) increases the latency for processing
728 * completed ops as we only get an interrupt when all aggregated
729 * ops have completed.
731 if (sc->sc_nqueue == 0)
733 if (sc->sc_nqueue > 1) {
735 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
737 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
743 * Check device status before going any further.
745 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
746 if (stat & BS_STAT_DMAERR) {
747 ubsec_totalreset(sc);
748 ubsecstats.hst_dmaerr++;
750 ubsecstats.hst_mcr1full++;
753 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
754 ubsecstats.hst_maxqueue = sc->sc_nqueue;
755 if (npkts > UBS_MAX_AGGR)
756 npkts = UBS_MAX_AGGR;
757 if (npkts < 2) /* special case 1 op */
760 ubsecstats.hst_totbatch += npkts-1;
763 printf("merging %d records\n", npkts);
764 #endif /* UBSEC_DEBUG */
766 q = SIMPLEQ_FIRST(&sc->sc_queue);
767 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
770 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
771 if (q->q_dst_map != NULL)
772 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
774 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
776 for (i = 0; i < q->q_nstacked_mcrs; i++) {
777 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
778 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
779 BUS_DMASYNC_PREWRITE);
780 if (q2->q_dst_map != NULL)
781 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
782 BUS_DMASYNC_PREREAD);
783 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
786 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
787 sizeof(struct ubsec_mcr_add));
788 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
789 q->q_stacked_mcr[i] = q2;
791 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
792 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
793 sc->sc_nqchip += npkts;
794 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
795 ubsecstats.hst_maxqchip = sc->sc_nqchip;
796 ubsec_dma_sync(&q->q_dma->d_alloc,
797 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
798 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
799 offsetof(struct ubsec_dmachunk, d_mcr));
802 q = SIMPLEQ_FIRST(&sc->sc_queue);
804 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
805 if (q->q_dst_map != NULL)
806 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
807 ubsec_dma_sync(&q->q_dma->d_alloc,
808 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
810 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
811 offsetof(struct ubsec_dmachunk, d_mcr));
814 printf("feed1: q->chip %p %08x stat %08x\n",
815 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
817 #endif /* UBSEC_DEBUG */
818 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
820 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
822 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
823 ubsecstats.hst_maxqchip = sc->sc_nqchip;
828 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
831 /* Go ahead and compute key in ubsec's byte order */
832 if (algo == CRYPTO_DES_CBC) {
833 bcopy(key, &ses->ses_deskey[0], 8);
834 bcopy(key, &ses->ses_deskey[2], 8);
835 bcopy(key, &ses->ses_deskey[4], 8);
837 bcopy(key, ses->ses_deskey, 24);
839 SWAP32(ses->ses_deskey[0]);
840 SWAP32(ses->ses_deskey[1]);
841 SWAP32(ses->ses_deskey[2]);
842 SWAP32(ses->ses_deskey[3]);
843 SWAP32(ses->ses_deskey[4]);
844 SWAP32(ses->ses_deskey[5]);
848 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
854 for (i = 0; i < klen; i++)
855 key[i] ^= HMAC_IPAD_VAL;
857 if (algo == CRYPTO_MD5_HMAC) {
859 MD5Update(&md5ctx, key, klen);
860 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
861 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
864 SHA1Update(&sha1ctx, key, klen);
865 SHA1Update(&sha1ctx, hmac_ipad_buffer,
866 SHA1_HMAC_BLOCK_LEN - klen);
867 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
870 for (i = 0; i < klen; i++)
871 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
873 if (algo == CRYPTO_MD5_HMAC) {
875 MD5Update(&md5ctx, key, klen);
876 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
877 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
880 SHA1Update(&sha1ctx, key, klen);
881 SHA1Update(&sha1ctx, hmac_opad_buffer,
882 SHA1_HMAC_BLOCK_LEN - klen);
883 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
886 for (i = 0; i < klen; i++)
887 key[i] ^= HMAC_OPAD_VAL;
891 * Allocate a new 'session' and return an encoded session id. 'sidp'
892 * contains our registration id, and should contain an encoded session
893 * id on successful allocation.
896 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
898 struct ubsec_softc *sc = device_get_softc(dev);
899 struct cryptoini *c, *encini = NULL, *macini = NULL;
900 struct ubsec_session *ses = NULL;
903 if (sidp == NULL || cri == NULL || sc == NULL)
906 for (c = cri; c != NULL; c = c->cri_next) {
907 if (c->cri_alg == CRYPTO_MD5_HMAC ||
908 c->cri_alg == CRYPTO_SHA1_HMAC) {
912 } else if (c->cri_alg == CRYPTO_DES_CBC ||
913 c->cri_alg == CRYPTO_3DES_CBC) {
920 if (encini == NULL && macini == NULL)
923 if (sc->sc_sessions == NULL) {
924 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
925 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
929 sc->sc_nsessions = 1;
931 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
932 if (sc->sc_sessions[sesn].ses_used == 0) {
933 ses = &sc->sc_sessions[sesn];
939 sesn = sc->sc_nsessions;
940 ses = (struct ubsec_session *)malloc((sesn + 1) *
941 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
944 bcopy(sc->sc_sessions, ses, sesn *
945 sizeof(struct ubsec_session));
946 bzero(sc->sc_sessions, sesn *
947 sizeof(struct ubsec_session));
948 free(sc->sc_sessions, M_DEVBUF);
949 sc->sc_sessions = ses;
950 ses = &sc->sc_sessions[sesn];
954 bzero(ses, sizeof(struct ubsec_session));
958 /* get an IV, network byte order */
959 /* XXX may read fewer than requested */
960 read_random(ses->ses_iv, sizeof(ses->ses_iv));
962 if (encini->cri_key != NULL) {
963 ubsec_setup_enckey(ses, encini->cri_alg,
969 ses->ses_mlen = macini->cri_mlen;
970 if (ses->ses_mlen == 0) {
971 if (macini->cri_alg == CRYPTO_MD5_HMAC)
972 ses->ses_mlen = MD5_HASH_LEN;
974 ses->ses_mlen = SHA1_HASH_LEN;
977 if (macini->cri_key != NULL) {
978 ubsec_setup_mackey(ses, macini->cri_alg,
979 macini->cri_key, macini->cri_klen / 8);
983 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
988 * Deallocate a session.
991 ubsec_freesession(device_t dev, u_int64_t tid)
993 struct ubsec_softc *sc = device_get_softc(dev);
995 u_int32_t sid = CRYPTO_SESID2LID(tid);
1000 session = UBSEC_SESSION(sid);
1001 if (session < sc->sc_nsessions) {
1002 bzero(&sc->sc_sessions[session],
1003 sizeof(sc->sc_sessions[session]));
1012 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1014 struct ubsec_operand *op = arg;
1016 KASSERT(nsegs <= UBS_MAX_SCATTER,
1017 ("Too many DMA segments returned when mapping operand"));
1020 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1021 (u_int) mapsize, nsegs, error);
1025 op->mapsize = mapsize;
1027 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1031 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1033 struct ubsec_softc *sc = device_get_softc(dev);
1034 struct ubsec_q *q = NULL;
1035 int err = 0, i, j, nicealign;
1036 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1037 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1038 int sskip, dskip, stheend, dtheend;
1040 struct ubsec_session *ses;
1041 struct ubsec_pktctx ctx;
1042 struct ubsec_dma *dmap = NULL;
1044 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1045 ubsecstats.hst_invalid++;
1048 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1049 ubsecstats.hst_badsession++;
1053 mtx_lock(&sc->sc_freeqlock);
1054 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1055 ubsecstats.hst_queuefull++;
1056 sc->sc_needwakeup |= CRYPTO_SYMQ;
1057 mtx_unlock(&sc->sc_freeqlock);
1060 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1061 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1062 mtx_unlock(&sc->sc_freeqlock);
1064 dmap = q->q_dma; /* Save dma pointer */
1065 bzero(q, sizeof(struct ubsec_q));
1066 bzero(&ctx, sizeof(ctx));
1068 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1070 ses = &sc->sc_sessions[q->q_sesn];
1072 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1073 q->q_src_m = (struct mbuf *)crp->crp_buf;
1074 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1075 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1076 q->q_src_io = (struct uio *)crp->crp_buf;
1077 q->q_dst_io = (struct uio *)crp->crp_buf;
1079 ubsecstats.hst_badflags++;
1081 goto errout; /* XXX we don't handle contiguous blocks! */
1084 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1086 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1087 dmap->d_dma->d_mcr.mcr_flags = 0;
1090 crd1 = crp->crp_desc;
1092 ubsecstats.hst_nodesc++;
1096 crd2 = crd1->crd_next;
1099 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1100 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1103 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1104 crd1->crd_alg == CRYPTO_3DES_CBC) {
1108 ubsecstats.hst_badalg++;
1113 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1114 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1115 (crd2->crd_alg == CRYPTO_DES_CBC ||
1116 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1117 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1120 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1121 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1122 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1123 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1124 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1129 * We cannot order the ubsec as requested
1131 ubsecstats.hst_badalg++;
1138 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1139 ubsec_setup_enckey(ses, enccrd->crd_alg,
1143 encoffset = enccrd->crd_skip;
1144 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1146 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1147 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1149 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1150 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1152 ctx.pc_iv[0] = ses->ses_iv[0];
1153 ctx.pc_iv[1] = ses->ses_iv[1];
1156 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1157 crypto_copyback(crp->crp_flags, crp->crp_buf,
1158 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1161 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1163 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1164 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1166 crypto_copydata(crp->crp_flags, crp->crp_buf,
1167 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1171 ctx.pc_deskey[0] = ses->ses_deskey[0];
1172 ctx.pc_deskey[1] = ses->ses_deskey[1];
1173 ctx.pc_deskey[2] = ses->ses_deskey[2];
1174 ctx.pc_deskey[3] = ses->ses_deskey[3];
1175 ctx.pc_deskey[4] = ses->ses_deskey[4];
1176 ctx.pc_deskey[5] = ses->ses_deskey[5];
1177 SWAP32(ctx.pc_iv[0]);
1178 SWAP32(ctx.pc_iv[1]);
1182 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1183 ubsec_setup_mackey(ses, maccrd->crd_alg,
1184 maccrd->crd_key, maccrd->crd_klen / 8);
1187 macoffset = maccrd->crd_skip;
1189 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1190 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1192 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1194 for (i = 0; i < 5; i++) {
1195 ctx.pc_hminner[i] = ses->ses_hminner[i];
1196 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1198 HTOLE32(ctx.pc_hminner[i]);
1199 HTOLE32(ctx.pc_hmouter[i]);
1203 if (enccrd && maccrd) {
1205 * ubsec cannot handle packets where the end of encryption
1206 * and authentication are not the same, or where the
1207 * encrypted part begins before the authenticated part.
1209 if ((encoffset + enccrd->crd_len) !=
1210 (macoffset + maccrd->crd_len)) {
1211 ubsecstats.hst_lenmismatch++;
1215 if (enccrd->crd_skip < maccrd->crd_skip) {
1216 ubsecstats.hst_skipmismatch++;
1220 sskip = maccrd->crd_skip;
1221 cpskip = dskip = enccrd->crd_skip;
1222 stheend = maccrd->crd_len;
1223 dtheend = enccrd->crd_len;
1224 coffset = enccrd->crd_skip - maccrd->crd_skip;
1225 cpoffset = cpskip + dtheend;
1228 printf("mac: skip %d, len %d, inject %d\n",
1229 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1230 printf("enc: skip %d, len %d, inject %d\n",
1231 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1232 printf("src: skip %d, len %d\n", sskip, stheend);
1233 printf("dst: skip %d, len %d\n", dskip, dtheend);
1234 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1235 coffset, stheend, cpskip, cpoffset);
1239 cpskip = dskip = sskip = macoffset + encoffset;
1240 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1241 cpoffset = cpskip + dtheend;
1244 ctx.pc_offset = htole16(coffset >> 2);
1246 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1247 ubsecstats.hst_nomap++;
1251 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1252 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1253 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1254 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1255 q->q_src_map = NULL;
1256 ubsecstats.hst_noload++;
1260 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1261 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1262 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1263 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1264 q->q_src_map = NULL;
1265 ubsecstats.hst_noload++;
1270 nicealign = ubsec_dmamap_aligned(&q->q_src);
1272 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1276 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1278 for (i = j = 0; i < q->q_src_nsegs; i++) {
1279 struct ubsec_pktbuf *pb;
1280 bus_size_t packl = q->q_src_segs[i].ds_len;
1281 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1283 if (sskip >= packl) {
1292 if (packl > 0xfffc) {
1298 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1300 pb = &dmap->d_dma->d_sbuf[j - 1];
1302 pb->pb_addr = htole32(packp);
1305 if (packl > stheend) {
1306 pb->pb_len = htole32(stheend);
1309 pb->pb_len = htole32(packl);
1313 pb->pb_len = htole32(packl);
1315 if ((i + 1) == q->q_src_nsegs)
1318 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1319 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1323 if (enccrd == NULL && maccrd != NULL) {
1324 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1325 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1326 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1327 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1330 printf("opkt: %x %x %x\n",
1331 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1332 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1333 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1336 if (crp->crp_flags & CRYPTO_F_IOV) {
1338 ubsecstats.hst_iovmisaligned++;
1342 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1344 ubsecstats.hst_nomap++;
1348 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1349 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1350 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1351 q->q_dst_map = NULL;
1352 ubsecstats.hst_noload++;
1356 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1358 q->q_dst = q->q_src;
1361 struct mbuf *m, *top, **mp;
1363 ubsecstats.hst_unaligned++;
1364 totlen = q->q_src_mapsize;
1365 if (totlen >= MINCLSIZE) {
1366 m = m_getcl(M_NOWAIT, MT_DATA,
1367 q->q_src_m->m_flags & M_PKTHDR);
1369 } else if (q->q_src_m->m_flags & M_PKTHDR) {
1370 m = m_gethdr(M_NOWAIT, MT_DATA);
1373 m = m_get(M_NOWAIT, MT_DATA);
1376 if (m && q->q_src_m->m_flags & M_PKTHDR &&
1377 !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) {
1382 ubsecstats.hst_nombuf++;
1383 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1386 m->m_len = len = min(totlen, len);
1391 while (totlen > 0) {
1392 if (totlen >= MINCLSIZE) {
1393 m = m_getcl(M_NOWAIT,
1397 m = m_get(M_NOWAIT, MT_DATA);
1402 ubsecstats.hst_nombuf++;
1403 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1406 m->m_len = len = min(totlen, len);
1412 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1414 if (bus_dmamap_create(sc->sc_dmat,
1415 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1416 ubsecstats.hst_nomap++;
1420 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1421 q->q_dst_map, q->q_dst_m,
1422 ubsec_op_cb, &q->q_dst,
1423 BUS_DMA_NOWAIT) != 0) {
1424 bus_dmamap_destroy(sc->sc_dmat,
1426 q->q_dst_map = NULL;
1427 ubsecstats.hst_noload++;
1433 ubsecstats.hst_badflags++;
1440 printf("dst skip: %d\n", dskip);
1442 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1443 struct ubsec_pktbuf *pb;
1444 bus_size_t packl = q->q_dst_segs[i].ds_len;
1445 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1447 if (dskip >= packl) {
1456 if (packl > 0xfffc) {
1462 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1464 pb = &dmap->d_dma->d_dbuf[j - 1];
1466 pb->pb_addr = htole32(packp);
1469 if (packl > dtheend) {
1470 pb->pb_len = htole32(dtheend);
1473 pb->pb_len = htole32(packl);
1477 pb->pb_len = htole32(packl);
1479 if ((i + 1) == q->q_dst_nsegs) {
1481 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1482 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1486 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1487 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1492 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1493 offsetof(struct ubsec_dmachunk, d_ctx));
1495 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1496 struct ubsec_pktctx_long *ctxl;
1498 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1499 offsetof(struct ubsec_dmachunk, d_ctx));
1501 /* transform small context into long context */
1502 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1503 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1504 ctxl->pc_flags = ctx.pc_flags;
1505 ctxl->pc_offset = ctx.pc_offset;
1506 for (i = 0; i < 6; i++)
1507 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1508 for (i = 0; i < 5; i++)
1509 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1510 for (i = 0; i < 5; i++)
1511 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1512 ctxl->pc_iv[0] = ctx.pc_iv[0];
1513 ctxl->pc_iv[1] = ctx.pc_iv[1];
1515 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1516 offsetof(struct ubsec_dmachunk, d_ctx),
1517 sizeof(struct ubsec_pktctx));
1519 mtx_lock(&sc->sc_mcr1lock);
1520 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1522 ubsecstats.hst_ipackets++;
1523 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1524 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1526 mtx_unlock(&sc->sc_mcr1lock);
1531 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1532 m_freem(q->q_dst_m);
1534 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1535 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1536 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1538 if (q->q_src_map != NULL) {
1539 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1540 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1543 if (q != NULL || err == ERESTART) {
1544 mtx_lock(&sc->sc_freeqlock);
1546 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1547 if (err == ERESTART)
1548 sc->sc_needwakeup |= CRYPTO_SYMQ;
1549 mtx_unlock(&sc->sc_freeqlock);
1551 if (err != ERESTART) {
1552 crp->crp_etype = err;
1559 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1561 struct cryptop *crp = (struct cryptop *)q->q_crp;
1562 struct cryptodesc *crd;
1563 struct ubsec_dma *dmap = q->q_dma;
1565 ubsecstats.hst_opackets++;
1566 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1568 ubsec_dma_sync(&dmap->d_alloc,
1569 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1570 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1571 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1572 BUS_DMASYNC_POSTREAD);
1573 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1574 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1576 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1577 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1578 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1580 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1581 m_freem(q->q_src_m);
1582 crp->crp_buf = (caddr_t)q->q_dst_m;
1585 /* copy out IV for future use */
1586 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1587 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1588 if (crd->crd_alg != CRYPTO_DES_CBC &&
1589 crd->crd_alg != CRYPTO_3DES_CBC)
1591 crypto_copydata(crp->crp_flags, crp->crp_buf,
1592 crd->crd_skip + crd->crd_len - 8, 8,
1593 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1598 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1599 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1600 crd->crd_alg != CRYPTO_SHA1_HMAC)
1602 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1603 sc->sc_sessions[q->q_sesn].ses_mlen,
1604 (caddr_t)dmap->d_dma->d_macbuf);
1607 mtx_lock(&sc->sc_freeqlock);
1608 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1609 mtx_unlock(&sc->sc_freeqlock);
1614 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1616 int i, j, dlen, slen;
1620 sptr = srcm->m_data;
1622 dptr = dstm->m_data;
1626 for (i = 0; i < min(slen, dlen); i++) {
1627 if (j < hoffset || j >= toffset)
1634 srcm = srcm->m_next;
1637 sptr = srcm->m_data;
1641 dstm = dstm->m_next;
1644 dptr = dstm->m_data;
1651 * feed the key generator, must be called at splimp() or higher.
1654 ubsec_feed2(struct ubsec_softc *sc)
1658 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1659 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1661 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1663 ubsec_dma_sync(&q->q_mcr,
1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1665 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1667 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1668 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1670 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1676 * Callback for handling random numbers
1679 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1681 struct cryptkop *krp;
1682 struct ubsec_ctx_keyop *ctx;
1684 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1685 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1687 switch (q->q_type) {
1688 #ifndef UBSEC_NO_RNG
1689 case UBS_CTXOP_RNGBYPASS: {
1690 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1692 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1693 (*sc->sc_harvest)(sc->sc_rndtest,
1694 rng->rng_buf.dma_vaddr,
1695 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1697 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1701 case UBS_CTXOP_MODEXP: {
1702 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1706 rlen = (me->me_modbits + 7) / 8;
1707 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1709 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1710 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1711 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1712 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1715 krp->krp_status = E2BIG;
1717 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1718 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1719 (krp->krp_param[krp->krp_iparams].crp_nbits
1721 bcopy(me->me_C.dma_vaddr,
1722 krp->krp_param[krp->krp_iparams].crp_p,
1723 (me->me_modbits + 7) / 8);
1725 ubsec_kshift_l(me->me_shiftbits,
1726 me->me_C.dma_vaddr, me->me_normbits,
1727 krp->krp_param[krp->krp_iparams].crp_p,
1728 krp->krp_param[krp->krp_iparams].crp_nbits);
1733 /* bzero all potentially sensitive data */
1734 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1735 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1736 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1737 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1739 /* Can't free here, so put us on the free list. */
1740 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1743 case UBS_CTXOP_RSAPRIV: {
1744 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1748 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1749 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1751 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1752 bcopy(rp->rpr_msgout.dma_vaddr,
1753 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1757 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1758 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1759 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1761 /* Can't free here, so put us on the free list. */
1762 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1766 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1767 letoh16(ctx->ctx_op));
1772 #ifndef UBSEC_NO_RNG
1774 ubsec_rng(void *vsc)
1776 struct ubsec_softc *sc = vsc;
1777 struct ubsec_q2_rng *rng = &sc->sc_rng;
1778 struct ubsec_mcr *mcr;
1779 struct ubsec_ctx_rngbypass *ctx;
1781 mtx_lock(&sc->sc_mcr2lock);
1782 if (rng->rng_used) {
1783 mtx_unlock(&sc->sc_mcr2lock);
1787 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1790 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1791 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1793 mcr->mcr_pkts = htole16(1);
1795 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1796 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1797 mcr->mcr_ipktbuf.pb_len = 0;
1798 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1799 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1800 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1802 mcr->mcr_opktbuf.pb_next = 0;
1804 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1805 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1806 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1808 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1810 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1813 ubsecstats.hst_rng++;
1814 mtx_unlock(&sc->sc_mcr2lock);
1820 * Something weird happened, generate our own call back.
1823 mtx_unlock(&sc->sc_mcr2lock);
1824 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1826 #endif /* UBSEC_NO_RNG */
1829 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1831 bus_addr_t *paddr = (bus_addr_t*) arg;
1832 *paddr = segs->ds_addr;
1837 struct ubsec_softc *sc,
1839 struct ubsec_dma_alloc *dma,
1845 /* XXX could specify sc_dmat as parent but that just adds overhead */
1846 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1847 1, 0, /* alignment, bounds */
1848 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1849 BUS_SPACE_MAXADDR, /* highaddr */
1850 NULL, NULL, /* filter, filterarg */
1853 size, /* maxsegsize */
1854 BUS_DMA_ALLOCNOW, /* flags */
1855 NULL, NULL, /* lockfunc, lockarg */
1858 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1859 "bus_dma_tag_create failed; error %u\n", r);
1863 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1864 BUS_DMA_NOWAIT, &dma->dma_map);
1866 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1867 "bus_dmammem_alloc failed; size %ju, error %u\n",
1872 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1876 mapflags | BUS_DMA_NOWAIT);
1878 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1879 "bus_dmamap_load failed; error %u\n", r);
1883 dma->dma_size = size;
1887 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1889 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1891 bus_dma_tag_destroy(dma->dma_tag);
1892 dma->dma_tag = NULL;
1897 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1899 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1900 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1901 bus_dma_tag_destroy(dma->dma_tag);
1905 * Resets the board. Values in the regesters are left as is
1906 * from the reset (i.e. initial values are assigned elsewhere).
1909 ubsec_reset_board(struct ubsec_softc *sc)
1911 volatile u_int32_t ctrl;
1913 ctrl = READ_REG(sc, BS_CTRL);
1914 ctrl |= BS_CTRL_RESET;
1915 WRITE_REG(sc, BS_CTRL, ctrl);
1918 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1924 * Init Broadcom registers
1927 ubsec_init_board(struct ubsec_softc *sc)
1931 ctrl = READ_REG(sc, BS_CTRL);
1932 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1933 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1935 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1936 ctrl |= BS_CTRL_MCR2INT;
1938 ctrl &= ~BS_CTRL_MCR2INT;
1940 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1941 ctrl &= ~BS_CTRL_SWNORM;
1943 WRITE_REG(sc, BS_CTRL, ctrl);
1947 * Init Broadcom PCI registers
1950 ubsec_init_pciregs(device_t dev)
1955 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1956 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1957 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1958 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1959 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1960 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1964 * This will set the cache line size to 1, this will
1965 * force the BCM58xx chip just to do burst read/writes.
1966 * Cache line read/writes are to slow
1968 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1972 * Clean up after a chip crash.
1973 * It is assumed that the caller in splimp()
1976 ubsec_cleanchip(struct ubsec_softc *sc)
1980 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1981 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1982 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1983 ubsec_free_q(sc, q);
1990 * It is assumed that the caller is within splimp().
1993 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
1996 struct cryptop *crp;
2000 npkts = q->q_nstacked_mcrs;
2002 for (i = 0; i < npkts; i++) {
2003 if(q->q_stacked_mcr[i]) {
2004 q2 = q->q_stacked_mcr[i];
2006 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2007 m_freem(q2->q_dst_m);
2009 crp = (struct cryptop *)q2->q_crp;
2011 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2013 crp->crp_etype = EFAULT;
2023 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2024 m_freem(q->q_dst_m);
2026 crp = (struct cryptop *)q->q_crp;
2028 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2030 crp->crp_etype = EFAULT;
2036 * Routine to reset the chip and clean up.
2037 * It is assumed that the caller is in splimp()
2040 ubsec_totalreset(struct ubsec_softc *sc)
2042 ubsec_reset_board(sc);
2043 ubsec_init_board(sc);
2044 ubsec_cleanchip(sc);
2048 ubsec_dmamap_aligned(struct ubsec_operand *op)
2052 for (i = 0; i < op->nsegs; i++) {
2053 if (op->segs[i].ds_addr & 3)
2055 if ((i != (op->nsegs - 1)) &&
2056 (op->segs[i].ds_len & 3))
2063 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2065 switch (q->q_type) {
2066 case UBS_CTXOP_MODEXP: {
2067 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2069 ubsec_dma_free(sc, &me->me_q.q_mcr);
2070 ubsec_dma_free(sc, &me->me_q.q_ctx);
2071 ubsec_dma_free(sc, &me->me_M);
2072 ubsec_dma_free(sc, &me->me_E);
2073 ubsec_dma_free(sc, &me->me_C);
2074 ubsec_dma_free(sc, &me->me_epb);
2078 case UBS_CTXOP_RSAPRIV: {
2079 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2081 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2082 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2083 ubsec_dma_free(sc, &rp->rpr_msgin);
2084 ubsec_dma_free(sc, &rp->rpr_msgout);
2089 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2095 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
2097 struct ubsec_softc *sc = device_get_softc(dev);
2100 if (krp == NULL || krp->krp_callback == NULL)
2103 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2106 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2107 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2111 switch (krp->krp_op) {
2113 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2114 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2116 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2118 case CRK_MOD_EXP_CRT:
2119 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2121 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2123 krp->krp_status = EOPNOTSUPP;
2127 return (0); /* silence compiler */
2131 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2134 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2136 struct ubsec_q2_modexp *me;
2137 struct ubsec_mcr *mcr;
2138 struct ubsec_ctx_modexp *ctx;
2139 struct ubsec_pktbuf *epb;
2141 u_int nbits, normbits, mbits, shiftbits, ebits;
2143 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2148 bzero(me, sizeof *me);
2150 me->me_q.q_type = UBS_CTXOP_MODEXP;
2152 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2155 else if (nbits <= 768)
2157 else if (nbits <= 1024)
2159 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2161 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2168 shiftbits = normbits - nbits;
2170 me->me_modbits = nbits;
2171 me->me_shiftbits = shiftbits;
2172 me->me_normbits = normbits;
2174 /* Sanity check: result bits must be >= true modulus bits. */
2175 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2180 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2181 &me->me_q.q_mcr, 0)) {
2185 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2187 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2188 &me->me_q.q_ctx, 0)) {
2193 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2194 if (mbits > nbits) {
2198 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2202 ubsec_kshift_r(shiftbits,
2203 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2204 me->me_M.dma_vaddr, normbits);
2206 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2210 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2212 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2213 if (ebits > nbits) {
2217 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2221 ubsec_kshift_r(shiftbits,
2222 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2223 me->me_E.dma_vaddr, normbits);
2225 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2230 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2231 epb->pb_addr = htole32(me->me_E.dma_paddr);
2233 epb->pb_len = htole32(normbits / 8);
2242 mcr->mcr_pkts = htole16(1);
2244 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2245 mcr->mcr_reserved = 0;
2246 mcr->mcr_pktlen = 0;
2248 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2249 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2250 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2252 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2253 mcr->mcr_opktbuf.pb_next = 0;
2254 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2257 /* Misaligned output buffer will hang the chip. */
2258 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2259 panic("%s: modexp invalid addr 0x%x\n",
2260 device_get_nameunit(sc->sc_dev),
2261 letoh32(mcr->mcr_opktbuf.pb_addr));
2262 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2263 panic("%s: modexp invalid len 0x%x\n",
2264 device_get_nameunit(sc->sc_dev),
2265 letoh32(mcr->mcr_opktbuf.pb_len));
2268 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2269 bzero(ctx, sizeof(*ctx));
2270 ubsec_kshift_r(shiftbits,
2271 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2272 ctx->me_N, normbits);
2273 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2274 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2275 ctx->me_E_len = htole16(nbits);
2276 ctx->me_N_len = htole16(nbits);
2280 ubsec_dump_mcr(mcr);
2281 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2286 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2289 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2290 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2291 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2292 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2294 /* Enqueue and we're done... */
2295 mtx_lock(&sc->sc_mcr2lock);
2296 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2298 ubsecstats.hst_modexp++;
2299 mtx_unlock(&sc->sc_mcr2lock);
2305 if (me->me_q.q_mcr.dma_tag != NULL)
2306 ubsec_dma_free(sc, &me->me_q.q_mcr);
2307 if (me->me_q.q_ctx.dma_tag != NULL) {
2308 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2309 ubsec_dma_free(sc, &me->me_q.q_ctx);
2311 if (me->me_M.dma_tag != NULL) {
2312 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2313 ubsec_dma_free(sc, &me->me_M);
2315 if (me->me_E.dma_tag != NULL) {
2316 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2317 ubsec_dma_free(sc, &me->me_E);
2319 if (me->me_C.dma_tag != NULL) {
2320 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2321 ubsec_dma_free(sc, &me->me_C);
2323 if (me->me_epb.dma_tag != NULL)
2324 ubsec_dma_free(sc, &me->me_epb);
2327 krp->krp_status = err;
2333 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2336 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2338 struct ubsec_q2_modexp *me;
2339 struct ubsec_mcr *mcr;
2340 struct ubsec_ctx_modexp *ctx;
2341 struct ubsec_pktbuf *epb;
2343 u_int nbits, normbits, mbits, shiftbits, ebits;
2345 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2350 bzero(me, sizeof *me);
2352 me->me_q.q_type = UBS_CTXOP_MODEXP;
2354 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2357 else if (nbits <= 768)
2359 else if (nbits <= 1024)
2361 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2363 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2370 shiftbits = normbits - nbits;
2373 me->me_modbits = nbits;
2374 me->me_shiftbits = shiftbits;
2375 me->me_normbits = normbits;
2377 /* Sanity check: result bits must be >= true modulus bits. */
2378 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2383 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2384 &me->me_q.q_mcr, 0)) {
2388 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2390 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2391 &me->me_q.q_ctx, 0)) {
2396 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2397 if (mbits > nbits) {
2401 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2405 bzero(me->me_M.dma_vaddr, normbits / 8);
2406 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2407 me->me_M.dma_vaddr, (mbits + 7) / 8);
2409 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2413 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2415 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2416 if (ebits > nbits) {
2420 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2424 bzero(me->me_E.dma_vaddr, normbits / 8);
2425 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2426 me->me_E.dma_vaddr, (ebits + 7) / 8);
2428 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2433 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2434 epb->pb_addr = htole32(me->me_E.dma_paddr);
2436 epb->pb_len = htole32((ebits + 7) / 8);
2445 mcr->mcr_pkts = htole16(1);
2447 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2448 mcr->mcr_reserved = 0;
2449 mcr->mcr_pktlen = 0;
2451 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2452 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2453 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2455 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2456 mcr->mcr_opktbuf.pb_next = 0;
2457 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2460 /* Misaligned output buffer will hang the chip. */
2461 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2462 panic("%s: modexp invalid addr 0x%x\n",
2463 device_get_nameunit(sc->sc_dev),
2464 letoh32(mcr->mcr_opktbuf.pb_addr));
2465 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2466 panic("%s: modexp invalid len 0x%x\n",
2467 device_get_nameunit(sc->sc_dev),
2468 letoh32(mcr->mcr_opktbuf.pb_len));
2471 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2472 bzero(ctx, sizeof(*ctx));
2473 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2475 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2476 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2477 ctx->me_E_len = htole16(ebits);
2478 ctx->me_N_len = htole16(nbits);
2482 ubsec_dump_mcr(mcr);
2483 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2488 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2491 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2492 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2493 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2494 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2496 /* Enqueue and we're done... */
2497 mtx_lock(&sc->sc_mcr2lock);
2498 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2500 mtx_unlock(&sc->sc_mcr2lock);
2506 if (me->me_q.q_mcr.dma_tag != NULL)
2507 ubsec_dma_free(sc, &me->me_q.q_mcr);
2508 if (me->me_q.q_ctx.dma_tag != NULL) {
2509 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2510 ubsec_dma_free(sc, &me->me_q.q_ctx);
2512 if (me->me_M.dma_tag != NULL) {
2513 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2514 ubsec_dma_free(sc, &me->me_M);
2516 if (me->me_E.dma_tag != NULL) {
2517 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2518 ubsec_dma_free(sc, &me->me_E);
2520 if (me->me_C.dma_tag != NULL) {
2521 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2522 ubsec_dma_free(sc, &me->me_C);
2524 if (me->me_epb.dma_tag != NULL)
2525 ubsec_dma_free(sc, &me->me_epb);
2528 krp->krp_status = err;
2534 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2536 struct ubsec_q2_rsapriv *rp = NULL;
2537 struct ubsec_mcr *mcr;
2538 struct ubsec_ctx_rsapriv *ctx;
2540 u_int padlen, msglen;
2542 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2543 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2544 if (msglen > padlen)
2549 else if (padlen <= 384)
2551 else if (padlen <= 512)
2553 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2555 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2562 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2567 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2572 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2577 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2580 bzero(rp, sizeof *rp);
2582 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2584 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2585 &rp->rpr_q.q_mcr, 0)) {
2589 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2591 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2592 &rp->rpr_q.q_ctx, 0)) {
2596 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2597 bzero(ctx, sizeof *ctx);
2600 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2601 &ctx->rpr_buf[0 * (padlen / 8)],
2602 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2605 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2606 &ctx->rpr_buf[1 * (padlen / 8)],
2607 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2611 &ctx->rpr_buf[2 * (padlen / 8)],
2612 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2616 &ctx->rpr_buf[3 * (padlen / 8)],
2617 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2620 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2621 &ctx->rpr_buf[4 * (padlen / 8)],
2622 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2624 msglen = padlen * 2;
2626 /* Copy in input message (aligned buffer/length). */
2627 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2628 /* Is this likely? */
2632 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2636 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2637 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2638 rp->rpr_msgin.dma_vaddr,
2639 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2641 /* Prepare space for output message (aligned buffer/length). */
2642 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2643 /* Is this likely? */
2647 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2651 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2653 mcr->mcr_pkts = htole16(1);
2655 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2656 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2657 mcr->mcr_ipktbuf.pb_next = 0;
2658 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2659 mcr->mcr_reserved = 0;
2660 mcr->mcr_pktlen = htole16(msglen);
2661 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2662 mcr->mcr_opktbuf.pb_next = 0;
2663 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2666 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2667 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2668 device_get_nameunit(sc->sc_dev),
2669 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2671 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2672 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2673 device_get_nameunit(sc->sc_dev),
2674 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2678 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2679 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2680 ctx->rpr_q_len = htole16(padlen);
2681 ctx->rpr_p_len = htole16(padlen);
2684 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2687 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2688 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2690 /* Enqueue and we're done... */
2691 mtx_lock(&sc->sc_mcr2lock);
2692 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2694 ubsecstats.hst_modexpcrt++;
2695 mtx_unlock(&sc->sc_mcr2lock);
2700 if (rp->rpr_q.q_mcr.dma_tag != NULL)
2701 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2702 if (rp->rpr_msgin.dma_tag != NULL) {
2703 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2704 ubsec_dma_free(sc, &rp->rpr_msgin);
2706 if (rp->rpr_msgout.dma_tag != NULL) {
2707 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2708 ubsec_dma_free(sc, &rp->rpr_msgout);
2712 krp->krp_status = err;
2719 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2721 printf("addr 0x%x (0x%x) next 0x%x\n",
2722 pb->pb_addr, pb->pb_len, pb->pb_next);
2726 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2728 printf("CTX (0x%x):\n", c->ctx_len);
2729 switch (letoh16(c->ctx_op)) {
2730 case UBS_CTXOP_RNGBYPASS:
2731 case UBS_CTXOP_RNGSHA1:
2733 case UBS_CTXOP_MODEXP:
2735 struct ubsec_ctx_modexp *cx = (void *)c;
2738 printf(" Elen %u, Nlen %u\n",
2739 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2740 len = (cx->me_N_len + 7)/8;
2741 for (i = 0; i < len; i++)
2742 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2747 printf("unknown context: %x\n", c->ctx_op);
2749 printf("END CTX\n");
2753 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2755 volatile struct ubsec_mcr_add *ma;
2759 printf(" pkts: %u, flags 0x%x\n",
2760 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2761 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2762 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2763 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2764 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2765 letoh16(ma->mcr_reserved));
2766 printf(" %d: ipkt ", i);
2767 ubsec_dump_pb(&ma->mcr_ipktbuf);
2768 printf(" %d: opkt ", i);
2769 ubsec_dump_pb(&ma->mcr_opktbuf);
2772 printf("END MCR\n");
2774 #endif /* UBSEC_DEBUG */
2777 * Return the number of significant bits of a big number.
2780 ubsec_ksigbits(struct crparam *cr)
2782 u_int plen = (cr->crp_nbits + 7) / 8;
2783 int i, sig = plen * 8;
2784 u_int8_t c, *p = cr->crp_p;
2786 for (i = plen - 1; i >= 0; i--) {
2789 while ((c & 0x80) == 0) {
2803 u_int8_t *src, u_int srcbits,
2804 u_int8_t *dst, u_int dstbits)
2809 slen = (srcbits + 7) / 8;
2810 dlen = (dstbits + 7) / 8;
2812 for (i = 0; i < slen; i++)
2814 for (i = 0; i < dlen - slen; i++)
2822 dst[di--] = dst[si--];
2829 for (i = dlen - 1; i > 0; i--)
2830 dst[i] = (dst[i] << n) |
2831 (dst[i - 1] >> (8 - n));
2832 dst[0] = dst[0] << n;
2839 u_int8_t *src, u_int srcbits,
2840 u_int8_t *dst, u_int dstbits)
2842 int slen, dlen, i, n;
2844 slen = (srcbits + 7) / 8;
2845 dlen = (dstbits + 7) / 8;
2848 for (i = 0; i < slen; i++)
2849 dst[i] = src[i + n];
2850 for (i = 0; i < dlen - slen; i++)
2855 for (i = 0; i < (dlen - 1); i++)
2856 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2857 dst[dlen - 1] = dst[dlen - 1] >> n;