sys/dev/ubsec/ubsec.c

   1 /*      $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
   5  * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
   6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by Jason L. Wright
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  33  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Effort sponsored in part by the Defense Advanced Research Projects
  37  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  38  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 /*
  45  * uBsec 5[56]01, 58xx hardware crypto accelerator
  46  */
  47
  48 #include "opt_ubsec.h"
  49
  50 #include <sys/param.h>
  51 #include <sys/systm.h>
  52 #include <sys/proc.h>
  53 #include <sys/errno.h>
  54 #include <sys/malloc.h>
  55 #include <sys/kernel.h>
  56 #include <sys/module.h>
  57 #include <sys/mbuf.h>
  58 #include <sys/lock.h>
  59 #include <sys/mutex.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/endian.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/bus.h>
  67 #include <machine/resource.h>
  68 #include <sys/bus.h>
  69 #include <sys/rman.h>
  70
  71 #include <crypto/sha1.h>
  72 #include <opencrypto/cryptodev.h>
  73 #include <opencrypto/cryptosoft.h>
  74 #include <sys/md5.h>
  75 #include <sys/random.h>
  76
  77 #include <dev/pci/pcivar.h>
  78 #include <dev/pci/pcireg.h>
  79
  80 /* grr, #defines for gratuitous incompatibility in queue.h */
  81 #define SIMPLEQ_HEAD            STAILQ_HEAD
  82 #define SIMPLEQ_ENTRY           STAILQ_ENTRY
  83 #define SIMPLEQ_INIT            STAILQ_INIT
  84 #define SIMPLEQ_INSERT_TAIL     STAILQ_INSERT_TAIL
  85 #define SIMPLEQ_EMPTY           STAILQ_EMPTY
  86 #define SIMPLEQ_FIRST           STAILQ_FIRST
  87 #define SIMPLEQ_REMOVE_HEAD     STAILQ_REMOVE_HEAD_UNTIL
  88 #define SIMPLEQ_FOREACH         STAILQ_FOREACH
  89 /* ditto for endian.h */
  90 #define letoh16(x)              le16toh(x)
  91 #define letoh32(x)              le32toh(x)
  92
  93 #ifdef UBSEC_RNDTEST
  94 #include <dev/rndtest/rndtest.h>
  95 #endif
  96 #include <dev/ubsec/ubsecreg.h>
  97 #include <dev/ubsec/ubsecvar.h>
  98
  99 /*
 100  * Prototypes and count for the pci_device structure
 101  */
 102 static  int ubsec_probe(device_t);
 103 static  int ubsec_attach(device_t);
 104 static  int ubsec_detach(device_t);
 105 static  int ubsec_suspend(device_t);
 106 static  int ubsec_resume(device_t);
 107 static  void ubsec_shutdown(device_t);
 108
 109 static device_method_t ubsec_methods[] = {
 110         /* Device interface */
 111         DEVMETHOD(device_probe,         ubsec_probe),
 112         DEVMETHOD(device_attach,        ubsec_attach),
 113         DEVMETHOD(device_detach,        ubsec_detach),
 114         DEVMETHOD(device_suspend,       ubsec_suspend),
 115         DEVMETHOD(device_resume,        ubsec_resume),
 116         DEVMETHOD(device_shutdown,      ubsec_shutdown),
 117
 118         /* bus interface */
 119         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 120         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 121
 122         { 0, 0 }
 123 };
 124 static driver_t ubsec_driver = {
 125         "ubsec",
 126         ubsec_methods,
 127         sizeof (struct ubsec_softc)
 128 };
 129 static devclass_t ubsec_devclass;
 130
 131 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
 132 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
 133 #ifdef UBSEC_RNDTEST
 134 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
 135 #endif
 136
 137 static  void ubsec_intr(void *);
 138 static  int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
 139 static  int ubsec_freesession(void *, u_int64_t);
 140 static  int ubsec_process(void *, struct cryptop *, int);
 141 static  void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
 142 static  void ubsec_feed(struct ubsec_softc *);
 143 static  void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
 144 static  void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
 145 static  int ubsec_feed2(struct ubsec_softc *);
 146 static  void ubsec_rng(void *);
 147 static  int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
 148                              struct ubsec_dma_alloc *, int);
 149 #define ubsec_dma_sync(_dma, _flags) \
 150         bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
 151 static  void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
 152 static  int ubsec_dmamap_aligned(struct ubsec_operand *op);
 153
 154 static  void ubsec_reset_board(struct ubsec_softc *sc);
 155 static  void ubsec_init_board(struct ubsec_softc *sc);
 156 static  void ubsec_init_pciregs(device_t dev);
 157 static  void ubsec_totalreset(struct ubsec_softc *sc);
 158
 159 static  int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
 160
 161 static  int ubsec_kprocess(void*, struct cryptkop *, int);
 162 static  int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
 163 static  int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
 164 static  int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
 165 static  void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
 166 static  int ubsec_ksigbits(struct crparam *);
 167 static  void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 168 static  void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 169
 170 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
 171
 172 #ifdef UBSEC_DEBUG
 173 static  void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
 174 static  void ubsec_dump_mcr(struct ubsec_mcr *);
 175 static  void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
 176
 177 static  int ubsec_debug = 0;
 178 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
 179             0, "control debugging msgs");
 180 #endif
 181
 182 #define READ_REG(sc,r) \
 183         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
 184
 185 #define WRITE_REG(sc,reg,val) \
 186         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
 187
 188 #define SWAP32(x) (x) = htole32(ntohl((x)))
 189 #define HTOLE32(x) (x) = htole32(x)
 190
 191 struct ubsec_stats ubsecstats;
 192 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
 193             ubsec_stats, "driver statistics");
 194
 195 static int
 196 ubsec_probe(device_t dev)
 197 {
 198         if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 199             (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
 200              pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
 201                 return (BUS_PROBE_DEFAULT);
 202         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 203             (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
 204              pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
 205                 return (BUS_PROBE_DEFAULT);
 206         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 207             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
 208              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 209              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
 210              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
 211              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 212              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 213              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
 214              ))
 215                 return (BUS_PROBE_DEFAULT);
 216         return (ENXIO);
 217 }
 218
 219 static const char*
 220 ubsec_partname(struct ubsec_softc *sc)
 221 {
 222         /* XXX sprintf numbers when not decoded */
 223         switch (pci_get_vendor(sc->sc_dev)) {
 224         case PCI_VENDOR_BROADCOM:
 225                 switch (pci_get_device(sc->sc_dev)) {
 226                 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
 227                 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
 228                 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
 229                 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
 230                 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
 231                 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
 232                 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
 233                 }
 234                 return "Broadcom unknown-part";
 235         case PCI_VENDOR_BLUESTEEL:
 236                 switch (pci_get_device(sc->sc_dev)) {
 237                 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
 238                 }
 239                 return "Bluesteel unknown-part";
 240         case PCI_VENDOR_SUN:
 241                 switch (pci_get_device(sc->sc_dev)) {
 242                 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
 243                 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
 244                 }
 245                 return "Sun unknown-part";
 246         }
 247         return "Unknown-vendor unknown-part";
 248 }
 249
 250 static void
 251 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 252 {
 253         random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
 254 }
 255
 256 static int
 257 ubsec_attach(device_t dev)
 258 {
 259         struct ubsec_softc *sc = device_get_softc(dev);
 260         struct ubsec_dma *dmap;
 261         u_int32_t cmd, i;
 262         int rid;
 263
 264         bzero(sc, sizeof (*sc));
 265         sc->sc_dev = dev;
 266
 267         SIMPLEQ_INIT(&sc->sc_queue);
 268         SIMPLEQ_INIT(&sc->sc_qchip);
 269         SIMPLEQ_INIT(&sc->sc_queue2);
 270         SIMPLEQ_INIT(&sc->sc_qchip2);
 271         SIMPLEQ_INIT(&sc->sc_q2free);
 272
 273         /* XXX handle power management */
 274
 275         sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
 276
 277         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 278             pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
 279                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 280
 281         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 282             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 283              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
 284                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 285
 286         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 287             pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
 288                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 289                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 290
 291         if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 292              (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 293               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 294               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
 295             (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 296              (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
 297               pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
 298                 /* NB: the 5821/5822 defines some additional status bits */
 299                 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
 300                     BS_STAT_MCR2_ALLEMPTY;
 301                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 302                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 303         }
 304
 305         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 306         cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
 307         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 308         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 309
 310         if (!(cmd & PCIM_CMD_MEMEN)) {
 311                 device_printf(dev, "failed to enable memory mapping\n");
 312                 goto bad;
 313         }
 314
 315         if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
 316                 device_printf(dev, "failed to enable bus mastering\n");
 317                 goto bad;
 318         }
 319
 320         /*
 321          * Setup memory-mapping of PCI registers.
 322          */
 323         rid = BS_BAR;
 324         sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 325                                            RF_ACTIVE);
 326         if (sc->sc_sr == NULL) {
 327                 device_printf(dev, "cannot map register space\n");
 328                 goto bad;
 329         }
 330         sc->sc_st = rman_get_bustag(sc->sc_sr);
 331         sc->sc_sh = rman_get_bushandle(sc->sc_sr);
 332
 333         /*
 334          * Arrange interrupt line.
 335          */
 336         rid = 0;
 337         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 338                                             RF_SHAREABLE|RF_ACTIVE);
 339         if (sc->sc_irq == NULL) {
 340                 device_printf(dev, "could not map interrupt\n");
 341                 goto bad1;
 342         }
 343         /*
 344          * NB: Network code assumes we are blocked with splimp()
 345          *     so make sure the IRQ is mapped appropriately.
 346          */
 347         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 348                            ubsec_intr, sc, &sc->sc_ih)) {
 349                 device_printf(dev, "could not establish interrupt\n");
 350                 goto bad2;
 351         }
 352
 353         sc->sc_cid = crypto_get_driverid(0);
 354         if (sc->sc_cid < 0) {
 355                 device_printf(dev, "could not get crypto driver id\n");
 356                 goto bad3;
 357         }
 358
 359         /*
 360          * Setup DMA descriptor area.
 361          */
 362         if (bus_dma_tag_create(NULL,                    /* parent */
 363                                1, 0,                    /* alignment, bounds */
 364                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 365                                BUS_SPACE_MAXADDR,       /* highaddr */
 366                                NULL, NULL,              /* filter, filterarg */
 367                                0x3ffff,                 /* maxsize */
 368                                UBS_MAX_SCATTER,         /* nsegments */
 369                                0xffff,                  /* maxsegsize */
 370                                BUS_DMA_ALLOCNOW,        /* flags */
 371                                NULL, NULL,              /* lockfunc, lockarg */
 372                                &sc->sc_dmat)) {
 373                 device_printf(dev, "cannot allocate DMA tag\n");
 374                 goto bad4;
 375         }
 376         SIMPLEQ_INIT(&sc->sc_freequeue);
 377         dmap = sc->sc_dmaa;
 378         for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
 379                 struct ubsec_q *q;
 380
 381                 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
 382                     M_DEVBUF, M_NOWAIT);
 383                 if (q == NULL) {
 384                         device_printf(dev, "cannot allocate queue buffers\n");
 385                         break;
 386                 }
 387
 388                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
 389                     &dmap->d_alloc, 0)) {
 390                         device_printf(dev, "cannot allocate dma buffers\n");
 391                         free(q, M_DEVBUF);
 392                         break;
 393                 }
 394                 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
 395
 396                 q->q_dma = dmap;
 397                 sc->sc_queuea[i] = q;
 398
 399                 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 400         }
 401         mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
 402                 "mcr1 operations", MTX_DEF);
 403         mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
 404                 "mcr1 free q", MTX_DEF);
 405
 406         device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
 407
 408         crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
 409             ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 410         crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
 411              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 412         crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
 413              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 414         crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
 415              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 416
 417         /*
 418          * Reset Broadcom chip
 419          */
 420         ubsec_reset_board(sc);
 421
 422         /*
 423          * Init Broadcom specific PCI settings
 424          */
 425         ubsec_init_pciregs(dev);
 426
 427         /*
 428          * Init Broadcom chip
 429          */
 430         ubsec_init_board(sc);
 431
 432 #ifndef UBSEC_NO_RNG
 433         if (sc->sc_flags & UBS_FLAGS_RNG) {
 434                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 435 #ifdef UBSEC_RNDTEST
 436                 sc->sc_rndtest = rndtest_attach(dev);
 437                 if (sc->sc_rndtest)
 438                         sc->sc_harvest = rndtest_harvest;
 439                 else
 440                         sc->sc_harvest = default_harvest;
 441 #else
 442                 sc->sc_harvest = default_harvest;
 443 #endif
 444
 445                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 446                     &sc->sc_rng.rng_q.q_mcr, 0))
 447                         goto skip_rng;
 448
 449                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
 450                     &sc->sc_rng.rng_q.q_ctx, 0)) {
 451                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 452                         goto skip_rng;
 453                 }
 454
 455                 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
 456                     UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
 457                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 458                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 459                         goto skip_rng;
 460                 }
 461
 462                 if (hz >= 100)
 463                         sc->sc_rnghz = hz / 100;
 464                 else
 465                         sc->sc_rnghz = 1;
 466                 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
 467                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
 468 skip_rng:
 469         ;
 470         }
 471 #endif /* UBSEC_NO_RNG */
 472         mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
 473                 "mcr2 operations", MTX_DEF);
 474
 475         if (sc->sc_flags & UBS_FLAGS_KEY) {
 476                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 477
 478                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
 479                         ubsec_kprocess, sc);
 480 #if 0
 481                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
 482                         ubsec_kprocess, sc);
 483 #endif
 484         }
 485         return (0);
 486 bad4:
 487         crypto_unregister_all(sc->sc_cid);
 488 bad3:
 489         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 490 bad2:
 491         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 492 bad1:
 493         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 494 bad:
 495         return (ENXIO);
 496 }
 497
 498 /*
 499  * Detach a device that successfully probed.
 500  */
 501 static int
 502 ubsec_detach(device_t dev)
 503 {
 504         struct ubsec_softc *sc = device_get_softc(dev);
 505
 506         /* XXX wait/abort active ops */
 507
 508         /* disable interrupts */
 509         WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
 510                 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
 511
 512         callout_stop(&sc->sc_rngto);
 513
 514         crypto_unregister_all(sc->sc_cid);
 515
 516 #ifdef UBSEC_RNDTEST
 517         if (sc->sc_rndtest)
 518                 rndtest_detach(sc->sc_rndtest);
 519 #endif
 520
 521         while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
 522                 struct ubsec_q *q;
 523
 524                 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
 525                 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
 526                 ubsec_dma_free(sc, &q->q_dma->d_alloc);
 527                 free(q, M_DEVBUF);
 528         }
 529         mtx_destroy(&sc->sc_mcr1lock);
 530         mtx_destroy(&sc->sc_freeqlock);
 531 #ifndef UBSEC_NO_RNG
 532         if (sc->sc_flags & UBS_FLAGS_RNG) {
 533                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 534                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 535                 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
 536         }
 537 #endif /* UBSEC_NO_RNG */
 538         mtx_destroy(&sc->sc_mcr2lock);
 539
 540         bus_generic_detach(dev);
 541         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 542         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 543
 544         bus_dma_tag_destroy(sc->sc_dmat);
 545         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 546
 547         return (0);
 548 }
 549
 550 /*
 551  * Stop all chip i/o so that the kernel's probe routines don't
 552  * get confused by errant DMAs when rebooting.
 553  */
 554 static void
 555 ubsec_shutdown(device_t dev)
 556 {
 557 #ifdef notyet
 558         ubsec_stop(device_get_softc(dev));
 559 #endif
 560 }
 561
 562 /*
 563  * Device suspend routine.
 564  */
 565 static int
 566 ubsec_suspend(device_t dev)
 567 {
 568         struct ubsec_softc *sc = device_get_softc(dev);
 569
 570 #ifdef notyet
 571         /* XXX stop the device and save PCI settings */
 572 #endif
 573         sc->sc_suspended = 1;
 574
 575         return (0);
 576 }
 577
 578 static int
 579 ubsec_resume(device_t dev)
 580 {
 581         struct ubsec_softc *sc = device_get_softc(dev);
 582
 583 #ifdef notyet
 584         /* XXX retore PCI settings and start the device */
 585 #endif
 586         sc->sc_suspended = 0;
 587         return (0);
 588 }
 589
 590 /*
 591  * UBSEC Interrupt routine
 592  */
 593 static void
 594 ubsec_intr(void *arg)
 595 {
 596         struct ubsec_softc *sc = arg;
 597         volatile u_int32_t stat;
 598         struct ubsec_q *q;
 599         struct ubsec_dma *dmap;
 600         int npkts = 0, i;
 601
 602         stat = READ_REG(sc, BS_STAT);
 603         stat &= sc->sc_statmask;
 604         if (stat == 0)
 605                 return;
 606
 607         WRITE_REG(sc, BS_STAT, stat);           /* IACK */
 608
 609         /*
 610          * Check to see if we have any packets waiting for us
 611          */
 612         if ((stat & BS_STAT_MCR1_DONE)) {
 613                 mtx_lock(&sc->sc_mcr1lock);
 614                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
 615                         q = SIMPLEQ_FIRST(&sc->sc_qchip);
 616                         dmap = q->q_dma;
 617
 618                         if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
 619                                 break;
 620
 621                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
 622
 623                         npkts = q->q_nstacked_mcrs;
 624                         sc->sc_nqchip -= 1+npkts;
 625                         /*
 626                          * search for further sc_qchip ubsec_q's that share
 627                          * the same MCR, and complete them too, they must be
 628                          * at the top.
 629                          */
 630                         for (i = 0; i < npkts; i++) {
 631                                 if(q->q_stacked_mcr[i]) {
 632                                         ubsec_callback(sc, q->q_stacked_mcr[i]);
 633                                 } else {
 634                                         break;
 635                                 }
 636                         }
 637                         ubsec_callback(sc, q);
 638                 }
 639                 /*
 640                  * Don't send any more packet to chip if there has been
 641                  * a DMAERR.
 642                  */
 643                 if (!(stat & BS_STAT_DMAERR))
 644                         ubsec_feed(sc);
 645                 mtx_unlock(&sc->sc_mcr1lock);
 646         }
 647
 648         /*
 649          * Check to see if we have any key setups/rng's waiting for us
 650          */
 651         if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
 652             (stat & BS_STAT_MCR2_DONE)) {
 653                 struct ubsec_q2 *q2;
 654                 struct ubsec_mcr *mcr;
 655
 656                 mtx_lock(&sc->sc_mcr2lock);
 657                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
 658                         q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
 659
 660                         ubsec_dma_sync(&q2->q_mcr,
 661                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 662
 663                         mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
 664                         if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
 665                                 ubsec_dma_sync(&q2->q_mcr,
 666                                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 667                                 break;
 668                         }
 669                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next);
 670                         ubsec_callback2(sc, q2);
 671                         /*
 672                          * Don't send any more packet to chip if there has been
 673                          * a DMAERR.
 674                          */
 675                         if (!(stat & BS_STAT_DMAERR))
 676                                 ubsec_feed2(sc);
 677                 }
 678                 mtx_unlock(&sc->sc_mcr2lock);
 679         }
 680
 681         /*
 682          * Check to see if we got any DMA Error
 683          */
 684         if (stat & BS_STAT_DMAERR) {
 685 #ifdef UBSEC_DEBUG
 686                 if (ubsec_debug) {
 687                         volatile u_int32_t a = READ_REG(sc, BS_ERR);
 688
 689                         printf("dmaerr %s@%08x\n",
 690                             (a & BS_ERR_READ) ? "read" : "write",
 691                             a & BS_ERR_ADDR);
 692                 }
 693 #endif /* UBSEC_DEBUG */
 694                 ubsecstats.hst_dmaerr++;
 695                 mtx_lock(&sc->sc_mcr1lock);
 696                 ubsec_totalreset(sc);
 697                 ubsec_feed(sc);
 698                 mtx_unlock(&sc->sc_mcr1lock);
 699         }
 700
 701         if (sc->sc_needwakeup) {                /* XXX check high watermark */
 702                 int wakeup;
 703
 704                 mtx_lock(&sc->sc_freeqlock);
 705                 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
 706 #ifdef UBSEC_DEBUG
 707                 if (ubsec_debug)
 708                         device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
 709                                 sc->sc_needwakeup);
 710 #endif /* UBSEC_DEBUG */
 711                 sc->sc_needwakeup &= ~wakeup;
 712                 mtx_unlock(&sc->sc_freeqlock);
 713                 crypto_unblock(sc->sc_cid, wakeup);
 714         }
 715 }
 716
 717 /*
 718  * ubsec_feed() - aggregate and post requests to chip
 719  */
 720 static void
 721 ubsec_feed(struct ubsec_softc *sc)
 722 {
 723         struct ubsec_q *q, *q2;
 724         int npkts, i;
 725         void *v;
 726         u_int32_t stat;
 727
 728         /*
 729          * Decide how many ops to combine in a single MCR.  We cannot
 730          * aggregate more than UBS_MAX_AGGR because this is the number
 731          * of slots defined in the data structure.  Note that
 732          * aggregation only happens if ops are marked batch'able.
 733          * Aggregating ops reduces the number of interrupts to the host
 734          * but also (potentially) increases the latency for processing
 735          * completed ops as we only get an interrupt when all aggregated
 736          * ops have completed.
 737          */
 738         if (sc->sc_nqueue == 0)
 739                 return;
 740         if (sc->sc_nqueue > 1) {
 741                 npkts = 0;
 742                 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
 743                         npkts++;
 744                         if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
 745                                 break;
 746                 }
 747         } else
 748                 npkts = 1;
 749         /*
 750          * Check device status before going any further.
 751          */
 752         if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
 753                 if (stat & BS_STAT_DMAERR) {
 754                         ubsec_totalreset(sc);
 755                         ubsecstats.hst_dmaerr++;
 756                 } else
 757                         ubsecstats.hst_mcr1full++;
 758                 return;
 759         }
 760         if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
 761                 ubsecstats.hst_maxqueue = sc->sc_nqueue;
 762         if (npkts > UBS_MAX_AGGR)
 763                 npkts = UBS_MAX_AGGR;
 764         if (npkts < 2)                          /* special case 1 op */
 765                 goto feed1;
 766
 767         ubsecstats.hst_totbatch += npkts-1;
 768 #ifdef UBSEC_DEBUG
 769         if (ubsec_debug)
 770                 printf("merging %d records\n", npkts);
 771 #endif /* UBSEC_DEBUG */
 772
 773         q = SIMPLEQ_FIRST(&sc->sc_queue);
 774         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
 775         --sc->sc_nqueue;
 776
 777         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 778         if (q->q_dst_map != NULL)
 779                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 780
 781         q->q_nstacked_mcrs = npkts - 1;         /* Number of packets stacked */
 782
 783         for (i = 0; i < q->q_nstacked_mcrs; i++) {
 784                 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
 785                 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
 786                     BUS_DMASYNC_PREWRITE);
 787                 if (q2->q_dst_map != NULL)
 788                         bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
 789                             BUS_DMASYNC_PREREAD);
 790                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next);
 791                 --sc->sc_nqueue;
 792
 793                 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
 794                     sizeof(struct ubsec_mcr_add));
 795                 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
 796                 q->q_stacked_mcr[i] = q2;
 797         }
 798         q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
 799         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 800         sc->sc_nqchip += npkts;
 801         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 802                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 803         ubsec_dma_sync(&q->q_dma->d_alloc,
 804             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 805         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 806             offsetof(struct ubsec_dmachunk, d_mcr));
 807         return;
 808 feed1:
 809         q = SIMPLEQ_FIRST(&sc->sc_queue);
 810
 811         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 812         if (q->q_dst_map != NULL)
 813                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 814         ubsec_dma_sync(&q->q_dma->d_alloc,
 815             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 816
 817         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 818             offsetof(struct ubsec_dmachunk, d_mcr));
 819 #ifdef UBSEC_DEBUG
 820         if (ubsec_debug)
 821                 printf("feed1: q->chip %p %08x stat %08x\n",
 822                       q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
 823                       stat);
 824 #endif /* UBSEC_DEBUG */
 825         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
 826         --sc->sc_nqueue;
 827         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 828         sc->sc_nqchip++;
 829         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 830                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 831         return;
 832 }
 833
 834 static void
 835 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
 836 {
 837
 838         /* Go ahead and compute key in ubsec's byte order */
 839         if (algo == CRYPTO_DES_CBC) {
 840                 bcopy(key, &ses->ses_deskey[0], 8);
 841                 bcopy(key, &ses->ses_deskey[2], 8);
 842                 bcopy(key, &ses->ses_deskey[4], 8);
 843         } else
 844                 bcopy(key, ses->ses_deskey, 24);
 845
 846         SWAP32(ses->ses_deskey[0]);
 847         SWAP32(ses->ses_deskey[1]);
 848         SWAP32(ses->ses_deskey[2]);
 849         SWAP32(ses->ses_deskey[3]);
 850         SWAP32(ses->ses_deskey[4]);
 851         SWAP32(ses->ses_deskey[5]);
 852 }
 853
 854 static void
 855 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
 856 {
 857         MD5_CTX md5ctx;
 858         SHA1_CTX sha1ctx;
 859         int i;
 860
 861         for (i = 0; i < klen; i++)
 862                 key[i] ^= HMAC_IPAD_VAL;
 863
 864         if (algo == CRYPTO_MD5_HMAC) {
 865                 MD5Init(&md5ctx);
 866                 MD5Update(&md5ctx, key, klen);
 867                 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 868                 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
 869         } else {
 870                 SHA1Init(&sha1ctx);
 871                 SHA1Update(&sha1ctx, key, klen);
 872                 SHA1Update(&sha1ctx, hmac_ipad_buffer,
 873                     SHA1_HMAC_BLOCK_LEN - klen);
 874                 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
 875         }
 876
 877         for (i = 0; i < klen; i++)
 878                 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
 879
 880         if (algo == CRYPTO_MD5_HMAC) {
 881                 MD5Init(&md5ctx);
 882                 MD5Update(&md5ctx, key, klen);
 883                 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 884                 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
 885         } else {
 886                 SHA1Init(&sha1ctx);
 887                 SHA1Update(&sha1ctx, key, klen);
 888                 SHA1Update(&sha1ctx, hmac_opad_buffer,
 889                     SHA1_HMAC_BLOCK_LEN - klen);
 890                 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
 891         }
 892
 893         for (i = 0; i < klen; i++)
 894                 key[i] ^= HMAC_OPAD_VAL;
 895 }
 896
 897 /*
 898  * Allocate a new 'session' and return an encoded session id.  'sidp'
 899  * contains our registration id, and should contain an encoded session
 900  * id on successful allocation.
 901  */
 902 static int
 903 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
 904 {
 905         struct cryptoini *c, *encini = NULL, *macini = NULL;
 906         struct ubsec_softc *sc = arg;
 907         struct ubsec_session *ses = NULL;
 908         int sesn;
 909
 910         if (sidp == NULL || cri == NULL || sc == NULL)
 911                 return (EINVAL);
 912
 913         for (c = cri; c != NULL; c = c->cri_next) {
 914                 if (c->cri_alg == CRYPTO_MD5_HMAC ||
 915                     c->cri_alg == CRYPTO_SHA1_HMAC) {
 916                         if (macini)
 917                                 return (EINVAL);
 918                         macini = c;
 919                 } else if (c->cri_alg == CRYPTO_DES_CBC ||
 920                     c->cri_alg == CRYPTO_3DES_CBC) {
 921                         if (encini)
 922                                 return (EINVAL);
 923                         encini = c;
 924                 } else
 925                         return (EINVAL);
 926         }
 927         if (encini == NULL && macini == NULL)
 928                 return (EINVAL);
 929
 930         if (sc->sc_sessions == NULL) {
 931                 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
 932                     sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 933                 if (ses == NULL)
 934                         return (ENOMEM);
 935                 sesn = 0;
 936                 sc->sc_nsessions = 1;
 937         } else {
 938                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
 939                         if (sc->sc_sessions[sesn].ses_used == 0) {
 940                                 ses = &sc->sc_sessions[sesn];
 941                                 break;
 942                         }
 943                 }
 944
 945                 if (ses == NULL) {
 946                         sesn = sc->sc_nsessions;
 947                         ses = (struct ubsec_session *)malloc((sesn + 1) *
 948                             sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 949                         if (ses == NULL)
 950                                 return (ENOMEM);
 951                         bcopy(sc->sc_sessions, ses, sesn *
 952                             sizeof(struct ubsec_session));
 953                         bzero(sc->sc_sessions, sesn *
 954                             sizeof(struct ubsec_session));
 955                         free(sc->sc_sessions, M_DEVBUF);
 956                         sc->sc_sessions = ses;
 957                         ses = &sc->sc_sessions[sesn];
 958                         sc->sc_nsessions++;
 959                 }
 960         }
 961         bzero(ses, sizeof(struct ubsec_session));
 962         ses->ses_used = 1;
 963
 964         if (encini) {
 965                 /* get an IV, network byte order */
 966                 /* XXX may read fewer than requested */
 967                 read_random(ses->ses_iv, sizeof(ses->ses_iv));
 968
 969                 if (encini->cri_key != NULL) {
 970                         ubsec_setup_enckey(ses, encini->cri_alg,
 971                             encini->cri_key);
 972                 }
 973         }
 974
 975         if (macini) {
 976                 ses->ses_mlen = macini->cri_mlen;
 977                 if (ses->ses_mlen == 0) {
 978                         if (macini->cri_alg == CRYPTO_MD5_HMAC)
 979                                 ses->ses_mlen = MD5_HASH_LEN;
 980                         else
 981                                 ses->ses_mlen = SHA1_HASH_LEN;
 982                 }
 983
 984                 if (macini->cri_key != NULL) {
 985                         ubsec_setup_mackey(ses, macini->cri_alg,
 986                             macini->cri_key, macini->cri_klen / 8);
 987                 }
 988         }
 989
 990         *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
 991         return (0);
 992 }
 993
 994 /*
 995  * Deallocate a session.
 996  */
 997 static int
 998 ubsec_freesession(void *arg, u_int64_t tid)
 999 {
1000         struct ubsec_softc *sc = arg;
1001         int session, ret;
1002         u_int32_t sid = CRYPTO_SESID2LID(tid);
1003
1004         if (sc == NULL)
1005                 return (EINVAL);
1006
1007         session = UBSEC_SESSION(sid);
1008         if (session < sc->sc_nsessions) {
1009                 bzero(&sc->sc_sessions[session],
1010                         sizeof(sc->sc_sessions[session]));
1011                 ret = 0;
1012         } else
1013                 ret = EINVAL;
1014
1015         return (ret);
1016 }
1017
1018 static void
1019 ubsec_op_cb(struct ubsec_operand *op, bus_dma_segment_t *seg, int nsegs,
1020     int error)
1021 {
1022
1023         KASSERT(nsegs <= UBS_MAX_SCATTER,
1024                 ("Too many DMA segments returned when mapping operand"));
1025 #ifdef UBSEC_DEBUG
1026         if (ubsec_debug)
1027                 printf("ubsec_op_cb: mapsize %u nsegs %d error=%d\n",
1028                         (u_int)op->mapsize, nsegs, error);
1029 #endif
1030         if (error != 0)
1031                 return;
1032         op->nsegs = nsegs;
1033         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1034 }
1035
1036 static void
1037 ubsec_op_cb1(void *arg, bus_dma_segment_t *seg, int nsegs, int error)
1038 {
1039
1040         ubsec_op_cb(arg, seg, nsegs, error);
1041 }
1042
1043 static void
1044 ubsec_op_cb2(void *arg, bus_dma_segment_t *seg, int nsegs,
1045     bus_size_t mapsize __unused, int error)
1046 {
1047
1048         ubsec_op_cb(arg, seg, nsegs, error);
1049 }
1050
1051 static int
1052 ubsec_process(void *arg, struct cryptop *crp, int hint)
1053 {
1054         struct ubsec_q *q = NULL;
1055         int err = 0, i, j, nicealign;
1056         struct ubsec_softc *sc = arg;
1057         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1058         int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1059         int sskip, dskip, stheend, dtheend;
1060         int16_t coffset;
1061         struct ubsec_session *ses;
1062         struct ubsec_pktctx ctx;
1063         struct ubsec_dma *dmap = NULL;
1064
1065         if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1066                 ubsecstats.hst_invalid++;
1067                 return (EINVAL);
1068         }
1069         if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1070                 ubsecstats.hst_badsession++;
1071                 return (EINVAL);
1072         }
1073
1074         mtx_lock(&sc->sc_freeqlock);
1075         if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1076                 ubsecstats.hst_queuefull++;
1077                 sc->sc_needwakeup |= CRYPTO_SYMQ;
1078                 mtx_unlock(&sc->sc_freeqlock);
1079                 return (ERESTART);
1080         }
1081         q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1082         SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
1083         mtx_unlock(&sc->sc_freeqlock);
1084
1085         dmap = q->q_dma; /* Save dma pointer */
1086         bzero(q, sizeof(struct ubsec_q));
1087         bzero(&ctx, sizeof(ctx));
1088
1089         q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1090         q->q_dma = dmap;
1091         ses = &sc->sc_sessions[q->q_sesn];
1092
1093         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1094                 q->q_src_m = (struct mbuf *)crp->crp_buf;
1095                 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1096         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1097                 q->q_src_io = (struct uio *)crp->crp_buf;
1098                 q->q_dst_io = (struct uio *)crp->crp_buf;
1099         } else {
1100                 q->q_src_buf = (void *)crp->crp_buf;
1101                 q->q_dst_buf = (void *)crp->crp_buf;
1102         }
1103
1104         bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1105
1106         dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1107         dmap->d_dma->d_mcr.mcr_flags = 0;
1108         q->q_crp = crp;
1109         q->q_src.mapsize = crp->crp_ilen;
1110         q->q_dst.mapsize = crp->crp_ilen;
1111
1112         crd1 = crp->crp_desc;
1113         if (crd1 == NULL) {
1114                 ubsecstats.hst_nodesc++;
1115                 err = EINVAL;
1116                 goto errout;
1117         }
1118         crd2 = crd1->crd_next;
1119
1120         if (crd2 == NULL) {
1121                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1122                     crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1123                         maccrd = crd1;
1124                         enccrd = NULL;
1125                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1126                     crd1->crd_alg == CRYPTO_3DES_CBC) {
1127                         maccrd = NULL;
1128                         enccrd = crd1;
1129                 } else {
1130                         ubsecstats.hst_badalg++;
1131                         err = EINVAL;
1132                         goto errout;
1133                 }
1134         } else {
1135                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1136                     crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1137                     (crd2->crd_alg == CRYPTO_DES_CBC ||
1138                         crd2->crd_alg == CRYPTO_3DES_CBC) &&
1139                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1140                         maccrd = crd1;
1141                         enccrd = crd2;
1142                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1143                     crd1->crd_alg == CRYPTO_3DES_CBC) &&
1144                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1145                         crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1146                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
1147                         enccrd = crd1;
1148                         maccrd = crd2;
1149                 } else {
1150                         /*
1151                          * We cannot order the ubsec as requested
1152                          */
1153                         ubsecstats.hst_badalg++;
1154                         err = EINVAL;
1155                         goto errout;
1156                 }
1157         }
1158
1159         if (enccrd) {
1160                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1161                         ubsec_setup_enckey(ses, enccrd->crd_alg,
1162                             enccrd->crd_key);
1163                 }
1164
1165                 encoffset = enccrd->crd_skip;
1166                 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1167
1168                 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1169                         q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1170
1171                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1172                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1173                         else {
1174                                 ctx.pc_iv[0] = ses->ses_iv[0];
1175                                 ctx.pc_iv[1] = ses->ses_iv[1];
1176                         }
1177
1178                         if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1179                                 crypto_copyback(crp->crp_flags, crp->crp_buf,
1180                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1181                         }
1182                 } else {
1183                         ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1184
1185                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1186                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1187                         else {
1188                                 crypto_copydata(crp->crp_flags, crp->crp_buf,
1189                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1190                         }
1191                 }
1192
1193                 ctx.pc_deskey[0] = ses->ses_deskey[0];
1194                 ctx.pc_deskey[1] = ses->ses_deskey[1];
1195                 ctx.pc_deskey[2] = ses->ses_deskey[2];
1196                 ctx.pc_deskey[3] = ses->ses_deskey[3];
1197                 ctx.pc_deskey[4] = ses->ses_deskey[4];
1198                 ctx.pc_deskey[5] = ses->ses_deskey[5];
1199                 SWAP32(ctx.pc_iv[0]);
1200                 SWAP32(ctx.pc_iv[1]);
1201         }
1202
1203         if (maccrd) {
1204                 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1205                         ubsec_setup_mackey(ses, maccrd->crd_alg,
1206                             maccrd->crd_key, maccrd->crd_klen / 8);
1207                 }
1208
1209                 macoffset = maccrd->crd_skip;
1210
1211                 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1212                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1213                 else
1214                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1215
1216                 for (i = 0; i < 5; i++) {
1217                         ctx.pc_hminner[i] = ses->ses_hminner[i];
1218                         ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1219
1220                         HTOLE32(ctx.pc_hminner[i]);
1221                         HTOLE32(ctx.pc_hmouter[i]);
1222                 }
1223         }
1224
1225         if (enccrd && maccrd) {
1226                 /*
1227                  * ubsec cannot handle packets where the end of encryption
1228                  * and authentication are not the same, or where the
1229                  * encrypted part begins before the authenticated part.
1230                  */
1231                 if ((encoffset + enccrd->crd_len) !=
1232                     (macoffset + maccrd->crd_len)) {
1233                         ubsecstats.hst_lenmismatch++;
1234                         err = EINVAL;
1235                         goto errout;
1236                 }
1237                 if (enccrd->crd_skip < maccrd->crd_skip) {
1238                         ubsecstats.hst_skipmismatch++;
1239                         err = EINVAL;
1240                         goto errout;
1241                 }
1242                 sskip = maccrd->crd_skip;
1243                 cpskip = dskip = enccrd->crd_skip;
1244                 stheend = maccrd->crd_len;
1245                 dtheend = enccrd->crd_len;
1246                 coffset = enccrd->crd_skip - maccrd->crd_skip;
1247                 cpoffset = cpskip + dtheend;
1248 #ifdef UBSEC_DEBUG
1249                 if (ubsec_debug) {
1250                         printf("mac: skip %d, len %d, inject %d\n",
1251                             maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1252                         printf("enc: skip %d, len %d, inject %d\n",
1253                             enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1254                         printf("src: skip %d, len %d\n", sskip, stheend);
1255                         printf("dst: skip %d, len %d\n", dskip, dtheend);
1256                         printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1257                             coffset, stheend, cpskip, cpoffset);
1258                 }
1259 #endif
1260         } else {
1261                 cpskip = dskip = sskip = macoffset + encoffset;
1262                 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1263                 cpoffset = cpskip + dtheend;
1264                 coffset = 0;
1265         }
1266         ctx.pc_offset = htole16(coffset >> 2);
1267
1268         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1269                 ubsecstats.hst_nomap++;
1270                 err = ENOMEM;
1271                 goto errout;
1272         }
1273         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1274                 err = bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1275                     q->q_src_m, ubsec_op_cb2, &q->q_src, BUS_DMA_NOWAIT);
1276         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1277                 err = bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1278                     q->q_src_io, ubsec_op_cb2, &q->q_src, BUS_DMA_NOWAIT);
1279         } else {
1280                 err = bus_dmamap_load(sc->sc_dmat, q->q_src_map, q->q_src_buf,
1281                     crp->crp_ilen, ubsec_op_cb1, &q->q_src, BUS_DMA_NOWAIT);
1282         }
1283         if (err != 0) {
1284                 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1285                 q->q_src_map = NULL;
1286                 ubsecstats.hst_noload++;
1287                 err = ENOMEM;
1288                 goto errout;
1289         }
1290         nicealign = ubsec_dmamap_aligned(&q->q_src);
1291
1292         dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1293
1294 #ifdef UBSEC_DEBUG
1295         if (ubsec_debug)
1296                 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1297 #endif
1298         for (i = j = 0; i < q->q_src_nsegs; i++) {
1299                 struct ubsec_pktbuf *pb;
1300                 bus_size_t packl = q->q_src_segs[i].ds_len;
1301                 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1302
1303                 if (sskip >= packl) {
1304                         sskip -= packl;
1305                         continue;
1306                 }
1307
1308                 packl -= sskip;
1309                 packp += sskip;
1310                 sskip = 0;
1311
1312                 if (packl > 0xfffc) {
1313                         err = EIO;
1314                         goto errout;
1315                 }
1316
1317                 if (j == 0)
1318                         pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1319                 else
1320                         pb = &dmap->d_dma->d_sbuf[j - 1];
1321
1322                 pb->pb_addr = htole32(packp);
1323
1324                 if (stheend) {
1325                         if (packl > stheend) {
1326                                 pb->pb_len = htole32(stheend);
1327                                 stheend = 0;
1328                         } else {
1329                                 pb->pb_len = htole32(packl);
1330                                 stheend -= packl;
1331                         }
1332                 } else
1333                         pb->pb_len = htole32(packl);
1334
1335                 if ((i + 1) == q->q_src_nsegs)
1336                         pb->pb_next = 0;
1337                 else
1338                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1339                             offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1340                 j++;
1341         }
1342
1343         if (enccrd == NULL && maccrd != NULL) {
1344                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1345                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1346                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1347                     offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1348 #ifdef UBSEC_DEBUG
1349                 if (ubsec_debug)
1350                         printf("opkt: %x %x %x\n",
1351                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1352                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1353                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1354 #endif
1355         } else {
1356                 if (crp->crp_flags & CRYPTO_F_IOV) {
1357                         if (!nicealign) {
1358                                 ubsecstats.hst_iovmisaligned++;
1359                                 err = EINVAL;
1360                                 goto errout;
1361                         }
1362                         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1363                              &q->q_dst_map)) {
1364                                 ubsecstats.hst_nomap++;
1365                                 err = ENOMEM;
1366                                 goto errout;
1367                         }
1368                         if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1369                             q->q_dst_io, ubsec_op_cb2, &q->q_dst,
1370                             BUS_DMA_NOWAIT) != 0) {
1371                                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1372                                 q->q_dst_map = NULL;
1373                                 ubsecstats.hst_noload++;
1374                                 err = ENOMEM;
1375                                 goto errout;
1376                         }
1377                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1378                         if (nicealign) {
1379                                 q->q_dst = q->q_src;
1380                         } else {
1381                                 int totlen, len;
1382                                 struct mbuf *m, *top, **mp;
1383
1384                                 ubsecstats.hst_unaligned++;
1385                                 totlen = q->q_src_mapsize;
1386                                 if (totlen >= MINCLSIZE) {
1387                                         m = m_getcl(M_DONTWAIT, MT_DATA,
1388                                             q->q_src_m->m_flags & M_PKTHDR);
1389                                         len = MCLBYTES;
1390                                 } else if (q->q_src_m->m_flags & M_PKTHDR) {
1391                                         m = m_gethdr(M_DONTWAIT, MT_DATA);
1392                                         len = MHLEN;
1393                                 } else {
1394                                         m = m_get(M_DONTWAIT, MT_DATA);
1395                                         len = MLEN;
1396                                 }
1397                                 if (m && q->q_src_m->m_flags & M_PKTHDR &&
1398                                     !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) {
1399                                         m_free(m);
1400                                         m = NULL;
1401                                 }
1402                                 if (m == NULL) {
1403                                         ubsecstats.hst_nombuf++;
1404                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
1405                                         goto errout;
1406                                 }
1407                                 m->m_len = len = min(totlen, len);
1408                                 totlen -= len;
1409                                 top = m;
1410                                 mp = &top;
1411
1412                                 while (totlen > 0) {
1413                                         if (totlen >= MINCLSIZE) {
1414                                                 m = m_getcl(M_DONTWAIT,
1415                                                     MT_DATA, 0);
1416                                                 len = MCLBYTES;
1417                                         } else {
1418                                                 m = m_get(M_DONTWAIT, MT_DATA);
1419                                                 len = MLEN;
1420                                         }
1421                                         if (m == NULL) {
1422                                                 m_freem(top);
1423                                                 ubsecstats.hst_nombuf++;
1424                                                 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1425                                                 goto errout;
1426                                         }
1427                                         m->m_len = len = min(totlen, len);
1428                                         totlen -= len;
1429                                         *mp = m;
1430                                         mp = &m->m_next;
1431                                 }
1432                                 q->q_dst_m = top;
1433                                 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1434                                     cpskip, cpoffset);
1435                                 if (bus_dmamap_create(sc->sc_dmat,
1436                                     BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1437                                         ubsecstats.hst_nomap++;
1438                                         err = ENOMEM;
1439                                         goto errout;
1440                                 }
1441                                 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1442                                     q->q_dst_map, q->q_dst_m,
1443                                     ubsec_op_cb2, &q->q_dst,
1444                                     BUS_DMA_NOWAIT) != 0) {
1445                                         bus_dmamap_destroy(sc->sc_dmat,
1446                                         q->q_dst_map);
1447                                         q->q_dst_map = NULL;
1448                                         ubsecstats.hst_noload++;
1449                                         err = ENOMEM;
1450                                         goto errout;
1451                                 }
1452                         }
1453                 } else {
1454                         KASSERT(nicealign, ("no nicealign"));
1455                         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1456                              &q->q_dst_map)) {
1457                                 ubsecstats.hst_nomap++;
1458                                 err = ENOMEM;
1459                                 goto errout;
1460                         }
1461                         if (bus_dmamap_load(sc->sc_dmat, q->q_dst_map,
1462                             q->q_dst_buf, crp->crp_ilen, ubsec_op_cb1,
1463                             &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1464                                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1465                                 q->q_dst_map = NULL;
1466                                 ubsecstats.hst_noload++;
1467                                 err = ENOMEM;
1468                                 goto errout;
1469                         }
1470                 }
1471
1472 #ifdef UBSEC_DEBUG
1473                 if (ubsec_debug)
1474                         printf("dst skip: %d\n", dskip);
1475 #endif
1476                 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1477                         struct ubsec_pktbuf *pb;
1478                         bus_size_t packl = q->q_dst_segs[i].ds_len;
1479                         bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1480
1481                         if (dskip >= packl) {
1482                                 dskip -= packl;
1483                                 continue;
1484                         }
1485
1486                         packl -= dskip;
1487                         packp += dskip;
1488                         dskip = 0;
1489
1490                         if (packl > 0xfffc) {
1491                                 err = EIO;
1492                                 goto errout;
1493                         }
1494
1495                         if (j == 0)
1496                                 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1497                         else
1498                                 pb = &dmap->d_dma->d_dbuf[j - 1];
1499
1500                         pb->pb_addr = htole32(packp);
1501
1502                         if (dtheend) {
1503                                 if (packl > dtheend) {
1504                                         pb->pb_len = htole32(dtheend);
1505                                         dtheend = 0;
1506                                 } else {
1507                                         pb->pb_len = htole32(packl);
1508                                         dtheend -= packl;
1509                                 }
1510                         } else
1511                                 pb->pb_len = htole32(packl);
1512
1513                         if ((i + 1) == q->q_dst_nsegs) {
1514                                 if (maccrd)
1515                                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1516                                             offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1517                                 else
1518                                         pb->pb_next = 0;
1519                         } else
1520                                 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1521                                     offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1522                         j++;
1523                 }
1524         }
1525
1526         dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1527             offsetof(struct ubsec_dmachunk, d_ctx));
1528
1529         if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1530                 struct ubsec_pktctx_long *ctxl;
1531
1532                 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1533                     offsetof(struct ubsec_dmachunk, d_ctx));
1534
1535                 /* transform small context into long context */
1536                 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1537                 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1538                 ctxl->pc_flags = ctx.pc_flags;
1539                 ctxl->pc_offset = ctx.pc_offset;
1540                 for (i = 0; i < 6; i++)
1541                         ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1542                 for (i = 0; i < 5; i++)
1543                         ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1544                 for (i = 0; i < 5; i++)
1545                         ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1546                 ctxl->pc_iv[0] = ctx.pc_iv[0];
1547                 ctxl->pc_iv[1] = ctx.pc_iv[1];
1548         } else
1549                 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1550                     offsetof(struct ubsec_dmachunk, d_ctx),
1551                     sizeof(struct ubsec_pktctx));
1552
1553         mtx_lock(&sc->sc_mcr1lock);
1554         SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1555         sc->sc_nqueue++;
1556         ubsecstats.hst_ipackets++;
1557         ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1558         if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1559                 ubsec_feed(sc);
1560         mtx_unlock(&sc->sc_mcr1lock);
1561         return (0);
1562
1563 errout:
1564         if (q != NULL) {
1565                 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1566                         m_freem(q->q_dst_m);
1567
1568                 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1569                         bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1570                         bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1571                 }
1572                 if (q->q_src_map != NULL) {
1573                         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1574                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1575                 }
1576         }
1577         if (q != NULL || err == ERESTART) {
1578                 mtx_lock(&sc->sc_freeqlock);
1579                 if (q != NULL)
1580                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1581                 if (err == ERESTART)
1582                         sc->sc_needwakeup |= CRYPTO_SYMQ;
1583                 mtx_unlock(&sc->sc_freeqlock);
1584         }
1585         if (err != ERESTART) {
1586                 crp->crp_etype = err;
1587                 crypto_done(crp);
1588         }
1589         return (err);
1590 }
1591
1592 static void
1593 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1594 {
1595         struct cryptop *crp = (struct cryptop *)q->q_crp;
1596         struct cryptodesc *crd;
1597         struct ubsec_dma *dmap = q->q_dma;
1598
1599         ubsecstats.hst_opackets++;
1600         ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1601
1602         ubsec_dma_sync(&dmap->d_alloc,
1603             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1604         if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1605                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1606                     BUS_DMASYNC_POSTREAD);
1607                 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1608                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1609         }
1610         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1611         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1612         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1613
1614         if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1615                 m_freem(q->q_src_m);
1616                 crp->crp_buf = (caddr_t)q->q_dst_m;
1617         }
1618
1619         /* copy out IV for future use */
1620         if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1621                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1622                         if (crd->crd_alg != CRYPTO_DES_CBC &&
1623                             crd->crd_alg != CRYPTO_3DES_CBC)
1624                                 continue;
1625                         crypto_copydata(crp->crp_flags, crp->crp_buf,
1626                             crd->crd_skip + crd->crd_len - 8, 8,
1627                             (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1628                         break;
1629                 }
1630         }
1631
1632         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1633                 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1634                     crd->crd_alg != CRYPTO_SHA1_HMAC)
1635                         continue;
1636                 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1637                     sc->sc_sessions[q->q_sesn].ses_mlen,
1638                     (caddr_t)dmap->d_dma->d_macbuf);
1639                 break;
1640         }
1641         mtx_lock(&sc->sc_freeqlock);
1642         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1643         mtx_unlock(&sc->sc_freeqlock);
1644         crypto_done(crp);
1645 }
1646
1647 static void
1648 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1649 {
1650         int i, j, dlen, slen;
1651         caddr_t dptr, sptr;
1652
1653         j = 0;
1654         sptr = srcm->m_data;
1655         slen = srcm->m_len;
1656         dptr = dstm->m_data;
1657         dlen = dstm->m_len;
1658
1659         while (1) {
1660                 for (i = 0; i < min(slen, dlen); i++) {
1661                         if (j < hoffset || j >= toffset)
1662                                 *dptr++ = *sptr++;
1663                         slen--;
1664                         dlen--;
1665                         j++;
1666                 }
1667                 if (slen == 0) {
1668                         srcm = srcm->m_next;
1669                         if (srcm == NULL)
1670                                 return;
1671                         sptr = srcm->m_data;
1672                         slen = srcm->m_len;
1673                 }
1674                 if (dlen == 0) {
1675                         dstm = dstm->m_next;
1676                         if (dstm == NULL)
1677                                 return;
1678                         dptr = dstm->m_data;
1679                         dlen = dstm->m_len;
1680                 }
1681         }
1682 }
1683
1684 /*
1685  * feed the key generator, must be called at splimp() or higher.
1686  */
1687 static int
1688 ubsec_feed2(struct ubsec_softc *sc)
1689 {
1690         struct ubsec_q2 *q;
1691
1692         while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1693                 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1694                         break;
1695                 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1696
1697                 ubsec_dma_sync(&q->q_mcr,
1698                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1699                 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1700
1701                 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1702                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next);
1703                 --sc->sc_nqueue2;
1704                 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1705         }
1706         return (0);
1707 }
1708
1709 /*
1710  * Callback for handling random numbers
1711  */
1712 static void
1713 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1714 {
1715         struct cryptkop *krp;
1716         struct ubsec_ctx_keyop *ctx;
1717
1718         ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1719         ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1720
1721         switch (q->q_type) {
1722 #ifndef UBSEC_NO_RNG
1723         case UBS_CTXOP_RNGBYPASS: {
1724                 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1725
1726                 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1727                 (*sc->sc_harvest)(sc->sc_rndtest,
1728                         rng->rng_buf.dma_vaddr,
1729                         UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1730                 rng->rng_used = 0;
1731                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1732                 break;
1733         }
1734 #endif
1735         case UBS_CTXOP_MODEXP: {
1736                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1737                 u_int rlen, clen;
1738
1739                 krp = me->me_krp;
1740                 rlen = (me->me_modbits + 7) / 8;
1741                 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1742
1743                 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1744                 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1745                 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1746                 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1747
1748                 if (clen < rlen)
1749                         krp->krp_status = E2BIG;
1750                 else {
1751                         if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1752                                 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1753                                     (krp->krp_param[krp->krp_iparams].crp_nbits
1754                                         + 7) / 8);
1755                                 bcopy(me->me_C.dma_vaddr,
1756                                     krp->krp_param[krp->krp_iparams].crp_p,
1757                                     (me->me_modbits + 7) / 8);
1758                         } else
1759                                 ubsec_kshift_l(me->me_shiftbits,
1760                                     me->me_C.dma_vaddr, me->me_normbits,
1761                                     krp->krp_param[krp->krp_iparams].crp_p,
1762                                     krp->krp_param[krp->krp_iparams].crp_nbits);
1763                 }
1764
1765                 crypto_kdone(krp);
1766
1767                 /* bzero all potentially sensitive data */
1768                 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1769                 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1770                 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1771                 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1772
1773                 /* Can't free here, so put us on the free list. */
1774                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1775                 break;
1776         }
1777         case UBS_CTXOP_RSAPRIV: {
1778                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1779                 u_int len;
1780
1781                 krp = rp->rpr_krp;
1782                 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1783                 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1784
1785                 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1786                 bcopy(rp->rpr_msgout.dma_vaddr,
1787                     krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1788
1789                 crypto_kdone(krp);
1790
1791                 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1792                 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1793                 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1794
1795                 /* Can't free here, so put us on the free list. */
1796                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1797                 break;
1798         }
1799         default:
1800                 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1801                     letoh16(ctx->ctx_op));
1802                 break;
1803         }
1804 }
1805
1806 #ifndef UBSEC_NO_RNG
1807 static void
1808 ubsec_rng(void *vsc)
1809 {
1810         struct ubsec_softc *sc = vsc;
1811         struct ubsec_q2_rng *rng = &sc->sc_rng;
1812         struct ubsec_mcr *mcr;
1813         struct ubsec_ctx_rngbypass *ctx;
1814
1815         mtx_lock(&sc->sc_mcr2lock);
1816         if (rng->rng_used) {
1817                 mtx_unlock(&sc->sc_mcr2lock);
1818                 return;
1819         }
1820         sc->sc_nqueue2++;
1821         if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1822                 goto out;
1823
1824         mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1825         ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1826
1827         mcr->mcr_pkts = htole16(1);
1828         mcr->mcr_flags = 0;
1829         mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1830         mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1831         mcr->mcr_ipktbuf.pb_len = 0;
1832         mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1833         mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1834         mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1835             UBS_PKTBUF_LEN);
1836         mcr->mcr_opktbuf.pb_next = 0;
1837
1838         ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1839         ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1840         rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1841
1842         ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1843
1844         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1845         rng->rng_used = 1;
1846         ubsec_feed2(sc);
1847         ubsecstats.hst_rng++;
1848         mtx_unlock(&sc->sc_mcr2lock);
1849
1850         return;
1851
1852 out:
1853         /*
1854          * Something weird happened, generate our own call back.
1855          */
1856         sc->sc_nqueue2--;
1857         mtx_unlock(&sc->sc_mcr2lock);
1858         callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1859 }
1860 #endif /* UBSEC_NO_RNG */
1861
1862 static void
1863 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1864 {
1865         bus_addr_t *paddr = (bus_addr_t*) arg;
1866         *paddr = segs->ds_addr;
1867 }
1868
1869 static int
1870 ubsec_dma_malloc(
1871         struct ubsec_softc *sc,
1872         bus_size_t size,
1873         struct ubsec_dma_alloc *dma,
1874         int mapflags
1875 )
1876 {
1877         int r;
1878
1879         /* XXX could specify sc_dmat as parent but that just adds overhead */
1880         r = bus_dma_tag_create(NULL,                    /* parent */
1881                                1, 0,                    /* alignment, bounds */
1882                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1883                                BUS_SPACE_MAXADDR,       /* highaddr */
1884                                NULL, NULL,              /* filter, filterarg */
1885                                size,                    /* maxsize */
1886                                1,                       /* nsegments */
1887                                size,                    /* maxsegsize */
1888                                BUS_DMA_ALLOCNOW,        /* flags */
1889                                NULL, NULL,              /* lockfunc, lockarg */
1890                                &dma->dma_tag);
1891         if (r != 0) {
1892                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1893                         "bus_dma_tag_create failed; error %u\n", r);
1894                 goto fail_0;
1895         }
1896
1897         r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1898         if (r != 0) {
1899                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1900                         "bus_dmamap_create failed; error %u\n", r);
1901                 goto fail_1;
1902         }
1903
1904         r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1905                              BUS_DMA_NOWAIT, &dma->dma_map);
1906         if (r != 0) {
1907                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1908                         "bus_dmammem_alloc failed; size %zu, error %u\n",
1909                         size, r);
1910                 goto fail_2;
1911         }
1912
1913         r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1914                             size,
1915                             ubsec_dmamap_cb,
1916                             &dma->dma_paddr,
1917                             mapflags | BUS_DMA_NOWAIT);
1918         if (r != 0) {
1919                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1920                         "bus_dmamap_load failed; error %u\n", r);
1921                 goto fail_3;
1922         }
1923
1924         dma->dma_size = size;
1925         return (0);
1926
1927 fail_3:
1928         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1929 fail_2:
1930         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1931 fail_1:
1932         bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1933         bus_dma_tag_destroy(dma->dma_tag);
1934 fail_0:
1935         dma->dma_map = NULL;
1936         dma->dma_tag = NULL;
1937         return (r);
1938 }
1939
1940 static void
1941 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1942 {
1943         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1944         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1945         bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1946         bus_dma_tag_destroy(dma->dma_tag);
1947 }
1948
1949 /*
1950  * Resets the board.  Values in the regesters are left as is
1951  * from the reset (i.e. initial values are assigned elsewhere).
1952  */
1953 static void
1954 ubsec_reset_board(struct ubsec_softc *sc)
1955 {
1956     volatile u_int32_t ctrl;
1957
1958     ctrl = READ_REG(sc, BS_CTRL);
1959     ctrl |= BS_CTRL_RESET;
1960     WRITE_REG(sc, BS_CTRL, ctrl);
1961
1962     /*
1963      * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1964      */
1965     DELAY(10);
1966 }
1967
1968 /*
1969  * Init Broadcom registers
1970  */
1971 static void
1972 ubsec_init_board(struct ubsec_softc *sc)
1973 {
1974         u_int32_t ctrl;
1975
1976         ctrl = READ_REG(sc, BS_CTRL);
1977         ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1978         ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1979
1980         if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1981                 ctrl |= BS_CTRL_MCR2INT;
1982         else
1983                 ctrl &= ~BS_CTRL_MCR2INT;
1984
1985         if (sc->sc_flags & UBS_FLAGS_HWNORM)
1986                 ctrl &= ~BS_CTRL_SWNORM;
1987
1988         WRITE_REG(sc, BS_CTRL, ctrl);
1989 }
1990
1991 /*
1992  * Init Broadcom PCI registers
1993  */
1994 static void
1995 ubsec_init_pciregs(device_t dev)
1996 {
1997 #if 0
1998         u_int32_t misc;
1999
2000         misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
2001         misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
2002             | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
2003         misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
2004             | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
2005         pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
2006 #endif
2007
2008         /*
2009          * This will set the cache line size to 1, this will
2010          * force the BCM58xx chip just to do burst read/writes.
2011          * Cache line read/writes are to slow
2012          */
2013         pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
2014 }
2015
2016 /*
2017  * Clean up after a chip crash.
2018  * It is assumed that the caller in splimp()
2019  */
2020 static void
2021 ubsec_cleanchip(struct ubsec_softc *sc)
2022 {
2023         struct ubsec_q *q;
2024
2025         while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2026                 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2027                 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
2028                 ubsec_free_q(sc, q);
2029         }
2030         sc->sc_nqchip = 0;
2031 }
2032
2033 /*
2034  * free a ubsec_q
2035  * It is assumed that the caller is within splimp().
2036  */
2037 static int
2038 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2039 {
2040         struct ubsec_q *q2;
2041         struct cryptop *crp;
2042         int npkts;
2043         int i;
2044
2045         npkts = q->q_nstacked_mcrs;
2046
2047         for (i = 0; i < npkts; i++) {
2048                 if(q->q_stacked_mcr[i]) {
2049                         q2 = q->q_stacked_mcr[i];
2050
2051                         if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2052                                 m_freem(q2->q_dst_m);
2053
2054                         crp = (struct cryptop *)q2->q_crp;
2055
2056                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2057
2058                         crp->crp_etype = EFAULT;
2059                         crypto_done(crp);
2060                 } else {
2061                         break;
2062                 }
2063         }
2064
2065         /*
2066          * Free header MCR
2067          */
2068         if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2069                 m_freem(q->q_dst_m);
2070
2071         crp = (struct cryptop *)q->q_crp;
2072
2073         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2074
2075         crp->crp_etype = EFAULT;
2076         crypto_done(crp);
2077         return(0);
2078 }
2079
2080 /*
2081  * Routine to reset the chip and clean up.
2082  * It is assumed that the caller is in splimp()
2083  */
2084 static void
2085 ubsec_totalreset(struct ubsec_softc *sc)
2086 {
2087         ubsec_reset_board(sc);
2088         ubsec_init_board(sc);
2089         ubsec_cleanchip(sc);
2090 }
2091
2092 static int
2093 ubsec_dmamap_aligned(struct ubsec_operand *op)
2094 {
2095         int i;
2096
2097         for (i = 0; i < op->nsegs; i++) {
2098                 if (op->segs[i].ds_addr & 3)
2099                         return (0);
2100                 if ((i != (op->nsegs - 1)) &&
2101                     (op->segs[i].ds_len & 3))
2102                         return (0);
2103         }
2104         return (1);
2105 }
2106
2107 static void
2108 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2109 {
2110         switch (q->q_type) {
2111         case UBS_CTXOP_MODEXP: {
2112                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2113
2114                 ubsec_dma_free(sc, &me->me_q.q_mcr);
2115                 ubsec_dma_free(sc, &me->me_q.q_ctx);
2116                 ubsec_dma_free(sc, &me->me_M);
2117                 ubsec_dma_free(sc, &me->me_E);
2118                 ubsec_dma_free(sc, &me->me_C);
2119                 ubsec_dma_free(sc, &me->me_epb);
2120                 free(me, M_DEVBUF);
2121                 break;
2122         }
2123         case UBS_CTXOP_RSAPRIV: {
2124                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2125
2126                 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2127                 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2128                 ubsec_dma_free(sc, &rp->rpr_msgin);
2129                 ubsec_dma_free(sc, &rp->rpr_msgout);
2130                 free(rp, M_DEVBUF);
2131                 break;
2132         }
2133         default:
2134                 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2135                 break;
2136         }
2137 }
2138
2139 static int
2140 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2141 {
2142         struct ubsec_softc *sc = arg;
2143         int r;
2144
2145         if (krp == NULL || krp->krp_callback == NULL)
2146                 return (EINVAL);
2147
2148         while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2149                 struct ubsec_q2 *q;
2150
2151                 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2152                 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next);
2153                 ubsec_kfree(sc, q);
2154         }
2155
2156         switch (krp->krp_op) {
2157         case CRK_MOD_EXP:
2158                 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2159                         r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2160                 else
2161                         r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2162                 break;
2163         case CRK_MOD_EXP_CRT:
2164                 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2165         default:
2166                 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2167                     krp->krp_op);
2168                 krp->krp_status = EOPNOTSUPP;
2169                 crypto_kdone(krp);
2170                 return (0);
2171         }
2172         return (0);                     /* silence compiler */
2173 }
2174
2175 /*
2176  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2177  */
2178 static int
2179 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2180 {
2181         struct ubsec_q2_modexp *me;
2182         struct ubsec_mcr *mcr;
2183         struct ubsec_ctx_modexp *ctx;
2184         struct ubsec_pktbuf *epb;
2185         int err = 0;
2186         u_int nbits, normbits, mbits, shiftbits, ebits;
2187
2188         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2189         if (me == NULL) {
2190                 err = ENOMEM;
2191                 goto errout;
2192         }
2193         bzero(me, sizeof *me);
2194         me->me_krp = krp;
2195         me->me_q.q_type = UBS_CTXOP_MODEXP;
2196
2197         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2198         if (nbits <= 512)
2199                 normbits = 512;
2200         else if (nbits <= 768)
2201                 normbits = 768;
2202         else if (nbits <= 1024)
2203                 normbits = 1024;
2204         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2205                 normbits = 1536;
2206         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2207                 normbits = 2048;
2208         else {
2209                 err = E2BIG;
2210                 goto errout;
2211         }
2212
2213         shiftbits = normbits - nbits;
2214
2215         me->me_modbits = nbits;
2216         me->me_shiftbits = shiftbits;
2217         me->me_normbits = normbits;
2218
2219         /* Sanity check: result bits must be >= true modulus bits. */
2220         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2221                 err = ERANGE;
2222                 goto errout;
2223         }
2224
2225         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2226             &me->me_q.q_mcr, 0)) {
2227                 err = ENOMEM;
2228                 goto errout;
2229         }
2230         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2231
2232         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2233             &me->me_q.q_ctx, 0)) {
2234                 err = ENOMEM;
2235                 goto errout;
2236         }
2237
2238         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2239         if (mbits > nbits) {
2240                 err = E2BIG;
2241                 goto errout;
2242         }
2243         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2244                 err = ENOMEM;
2245                 goto errout;
2246         }
2247         ubsec_kshift_r(shiftbits,
2248             krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2249             me->me_M.dma_vaddr, normbits);
2250
2251         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2252                 err = ENOMEM;
2253                 goto errout;
2254         }
2255         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2256
2257         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2258         if (ebits > nbits) {
2259                 err = E2BIG;
2260                 goto errout;
2261         }
2262         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2263                 err = ENOMEM;
2264                 goto errout;
2265         }
2266         ubsec_kshift_r(shiftbits,
2267             krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2268             me->me_E.dma_vaddr, normbits);
2269
2270         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2271             &me->me_epb, 0)) {
2272                 err = ENOMEM;
2273                 goto errout;
2274         }
2275         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2276         epb->pb_addr = htole32(me->me_E.dma_paddr);
2277         epb->pb_next = 0;
2278         epb->pb_len = htole32(normbits / 8);
2279
2280 #ifdef UBSEC_DEBUG
2281         if (ubsec_debug) {
2282                 printf("Epb ");
2283                 ubsec_dump_pb(epb);
2284         }
2285 #endif
2286
2287         mcr->mcr_pkts = htole16(1);
2288         mcr->mcr_flags = 0;
2289         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2290         mcr->mcr_reserved = 0;
2291         mcr->mcr_pktlen = 0;
2292
2293         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2294         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2295         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2296
2297         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2298         mcr->mcr_opktbuf.pb_next = 0;
2299         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2300
2301 #ifdef DIAGNOSTIC
2302         /* Misaligned output buffer will hang the chip. */
2303         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2304                 panic("%s: modexp invalid addr 0x%x\n",
2305                     device_get_nameunit(sc->sc_dev),
2306                     letoh32(mcr->mcr_opktbuf.pb_addr));
2307         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2308                 panic("%s: modexp invalid len 0x%x\n",
2309                     device_get_nameunit(sc->sc_dev),
2310                     letoh32(mcr->mcr_opktbuf.pb_len));
2311 #endif
2312
2313         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2314         bzero(ctx, sizeof(*ctx));
2315         ubsec_kshift_r(shiftbits,
2316             krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2317             ctx->me_N, normbits);
2318         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2319         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2320         ctx->me_E_len = htole16(nbits);
2321         ctx->me_N_len = htole16(nbits);
2322
2323 #ifdef UBSEC_DEBUG
2324         if (ubsec_debug) {
2325                 ubsec_dump_mcr(mcr);
2326                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2327         }
2328 #endif
2329
2330         /*
2331          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2332          * everything else.
2333          */
2334         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2335         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2336         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2337         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2338
2339         /* Enqueue and we're done... */
2340         mtx_lock(&sc->sc_mcr2lock);
2341         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2342         ubsec_feed2(sc);
2343         ubsecstats.hst_modexp++;
2344         mtx_unlock(&sc->sc_mcr2lock);
2345
2346         return (0);
2347
2348 errout:
2349         if (me != NULL) {
2350                 if (me->me_q.q_mcr.dma_map != NULL)
2351                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2352                 if (me->me_q.q_ctx.dma_map != NULL) {
2353                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2354                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2355                 }
2356                 if (me->me_M.dma_map != NULL) {
2357                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2358                         ubsec_dma_free(sc, &me->me_M);
2359                 }
2360                 if (me->me_E.dma_map != NULL) {
2361                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2362                         ubsec_dma_free(sc, &me->me_E);
2363                 }
2364                 if (me->me_C.dma_map != NULL) {
2365                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2366                         ubsec_dma_free(sc, &me->me_C);
2367                 }
2368                 if (me->me_epb.dma_map != NULL)
2369                         ubsec_dma_free(sc, &me->me_epb);
2370                 free(me, M_DEVBUF);
2371         }
2372         krp->krp_status = err;
2373         crypto_kdone(krp);
2374         return (0);
2375 }
2376
2377 /*
2378  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2379  */
2380 static int
2381 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2382 {
2383         struct ubsec_q2_modexp *me;
2384         struct ubsec_mcr *mcr;
2385         struct ubsec_ctx_modexp *ctx;
2386         struct ubsec_pktbuf *epb;
2387         int err = 0;
2388         u_int nbits, normbits, mbits, shiftbits, ebits;
2389
2390         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2391         if (me == NULL) {
2392                 err = ENOMEM;
2393                 goto errout;
2394         }
2395         bzero(me, sizeof *me);
2396         me->me_krp = krp;
2397         me->me_q.q_type = UBS_CTXOP_MODEXP;
2398
2399         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2400         if (nbits <= 512)
2401                 normbits = 512;
2402         else if (nbits <= 768)
2403                 normbits = 768;
2404         else if (nbits <= 1024)
2405                 normbits = 1024;
2406         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2407                 normbits = 1536;
2408         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2409                 normbits = 2048;
2410         else {
2411                 err = E2BIG;
2412                 goto errout;
2413         }
2414
2415         shiftbits = normbits - nbits;
2416
2417         /* XXX ??? */
2418         me->me_modbits = nbits;
2419         me->me_shiftbits = shiftbits;
2420         me->me_normbits = normbits;
2421
2422         /* Sanity check: result bits must be >= true modulus bits. */
2423         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2424                 err = ERANGE;
2425                 goto errout;
2426         }
2427
2428         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2429             &me->me_q.q_mcr, 0)) {
2430                 err = ENOMEM;
2431                 goto errout;
2432         }
2433         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2434
2435         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2436             &me->me_q.q_ctx, 0)) {
2437                 err = ENOMEM;
2438                 goto errout;
2439         }
2440
2441         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2442         if (mbits > nbits) {
2443                 err = E2BIG;
2444                 goto errout;
2445         }
2446         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2447                 err = ENOMEM;
2448                 goto errout;
2449         }
2450         bzero(me->me_M.dma_vaddr, normbits / 8);
2451         bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2452             me->me_M.dma_vaddr, (mbits + 7) / 8);
2453
2454         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2455                 err = ENOMEM;
2456                 goto errout;
2457         }
2458         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2459
2460         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2461         if (ebits > nbits) {
2462                 err = E2BIG;
2463                 goto errout;
2464         }
2465         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2466                 err = ENOMEM;
2467                 goto errout;
2468         }
2469         bzero(me->me_E.dma_vaddr, normbits / 8);
2470         bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2471             me->me_E.dma_vaddr, (ebits + 7) / 8);
2472
2473         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2474             &me->me_epb, 0)) {
2475                 err = ENOMEM;
2476                 goto errout;
2477         }
2478         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2479         epb->pb_addr = htole32(me->me_E.dma_paddr);
2480         epb->pb_next = 0;
2481         epb->pb_len = htole32((ebits + 7) / 8);
2482
2483 #ifdef UBSEC_DEBUG
2484         if (ubsec_debug) {
2485                 printf("Epb ");
2486                 ubsec_dump_pb(epb);
2487         }
2488 #endif
2489
2490         mcr->mcr_pkts = htole16(1);
2491         mcr->mcr_flags = 0;
2492         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2493         mcr->mcr_reserved = 0;
2494         mcr->mcr_pktlen = 0;
2495
2496         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2497         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2498         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2499
2500         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2501         mcr->mcr_opktbuf.pb_next = 0;
2502         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2503
2504 #ifdef DIAGNOSTIC
2505         /* Misaligned output buffer will hang the chip. */
2506         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2507                 panic("%s: modexp invalid addr 0x%x\n",
2508                     device_get_nameunit(sc->sc_dev),
2509                     letoh32(mcr->mcr_opktbuf.pb_addr));
2510         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2511                 panic("%s: modexp invalid len 0x%x\n",
2512                     device_get_nameunit(sc->sc_dev),
2513                     letoh32(mcr->mcr_opktbuf.pb_len));
2514 #endif
2515
2516         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2517         bzero(ctx, sizeof(*ctx));
2518         bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2519             (nbits + 7) / 8);
2520         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2521         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2522         ctx->me_E_len = htole16(ebits);
2523         ctx->me_N_len = htole16(nbits);
2524
2525 #ifdef UBSEC_DEBUG
2526         if (ubsec_debug) {
2527                 ubsec_dump_mcr(mcr);
2528                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2529         }
2530 #endif
2531
2532         /*
2533          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2534          * everything else.
2535          */
2536         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2537         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2538         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2539         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2540
2541         /* Enqueue and we're done... */
2542         mtx_lock(&sc->sc_mcr2lock);
2543         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2544         ubsec_feed2(sc);
2545         mtx_unlock(&sc->sc_mcr2lock);
2546
2547         return (0);
2548
2549 errout:
2550         if (me != NULL) {
2551                 if (me->me_q.q_mcr.dma_map != NULL)
2552                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2553                 if (me->me_q.q_ctx.dma_map != NULL) {
2554                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2555                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2556                 }
2557                 if (me->me_M.dma_map != NULL) {
2558                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2559                         ubsec_dma_free(sc, &me->me_M);
2560                 }
2561                 if (me->me_E.dma_map != NULL) {
2562                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2563                         ubsec_dma_free(sc, &me->me_E);
2564                 }
2565                 if (me->me_C.dma_map != NULL) {
2566                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2567                         ubsec_dma_free(sc, &me->me_C);
2568                 }
2569                 if (me->me_epb.dma_map != NULL)
2570                         ubsec_dma_free(sc, &me->me_epb);
2571                 free(me, M_DEVBUF);
2572         }
2573         krp->krp_status = err;
2574         crypto_kdone(krp);
2575         return (0);
2576 }
2577
2578 static int
2579 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2580 {
2581         struct ubsec_q2_rsapriv *rp = NULL;
2582         struct ubsec_mcr *mcr;
2583         struct ubsec_ctx_rsapriv *ctx;
2584         int err = 0;
2585         u_int padlen, msglen;
2586
2587         msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2588         padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2589         if (msglen > padlen)
2590                 padlen = msglen;
2591
2592         if (padlen <= 256)
2593                 padlen = 256;
2594         else if (padlen <= 384)
2595                 padlen = 384;
2596         else if (padlen <= 512)
2597                 padlen = 512;
2598         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2599                 padlen = 768;
2600         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2601                 padlen = 1024;
2602         else {
2603                 err = E2BIG;
2604                 goto errout;
2605         }
2606
2607         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2608                 err = E2BIG;
2609                 goto errout;
2610         }
2611
2612         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2613                 err = E2BIG;
2614                 goto errout;
2615         }
2616
2617         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2618                 err = E2BIG;
2619                 goto errout;
2620         }
2621
2622         rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2623         if (rp == NULL)
2624                 return (ENOMEM);
2625         bzero(rp, sizeof *rp);
2626         rp->rpr_krp = krp;
2627         rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2628
2629         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2630             &rp->rpr_q.q_mcr, 0)) {
2631                 err = ENOMEM;
2632                 goto errout;
2633         }
2634         mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2635
2636         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2637             &rp->rpr_q.q_ctx, 0)) {
2638                 err = ENOMEM;
2639                 goto errout;
2640         }
2641         ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2642         bzero(ctx, sizeof *ctx);
2643
2644         /* Copy in p */
2645         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2646             &ctx->rpr_buf[0 * (padlen / 8)],
2647             (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2648
2649         /* Copy in q */
2650         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2651             &ctx->rpr_buf[1 * (padlen / 8)],
2652             (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2653
2654         /* Copy in dp */
2655         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2656             &ctx->rpr_buf[2 * (padlen / 8)],
2657             (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2658
2659         /* Copy in dq */
2660         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2661             &ctx->rpr_buf[3 * (padlen / 8)],
2662             (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2663
2664         /* Copy in pinv */
2665         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2666             &ctx->rpr_buf[4 * (padlen / 8)],
2667             (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2668
2669         msglen = padlen * 2;
2670
2671         /* Copy in input message (aligned buffer/length). */
2672         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2673                 /* Is this likely? */
2674                 err = E2BIG;
2675                 goto errout;
2676         }
2677         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2678                 err = ENOMEM;
2679                 goto errout;
2680         }
2681         bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2682         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2683             rp->rpr_msgin.dma_vaddr,
2684             (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2685
2686         /* Prepare space for output message (aligned buffer/length). */
2687         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2688                 /* Is this likely? */
2689                 err = E2BIG;
2690                 goto errout;
2691         }
2692         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2693                 err = ENOMEM;
2694                 goto errout;
2695         }
2696         bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2697
2698         mcr->mcr_pkts = htole16(1);
2699         mcr->mcr_flags = 0;
2700         mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2701         mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2702         mcr->mcr_ipktbuf.pb_next = 0;
2703         mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2704         mcr->mcr_reserved = 0;
2705         mcr->mcr_pktlen = htole16(msglen);
2706         mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2707         mcr->mcr_opktbuf.pb_next = 0;
2708         mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2709
2710 #ifdef DIAGNOSTIC
2711         if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2712                 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2713                     device_get_nameunit(sc->sc_dev),
2714                     rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2715         }
2716         if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2717                 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2718                     device_get_nameunit(sc->sc_dev),
2719                     rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2720         }
2721 #endif
2722
2723         ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2724         ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2725         ctx->rpr_q_len = htole16(padlen);
2726         ctx->rpr_p_len = htole16(padlen);
2727
2728         /*
2729          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2730          * everything else.
2731          */
2732         ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2733         ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2734
2735         /* Enqueue and we're done... */
2736         mtx_lock(&sc->sc_mcr2lock);
2737         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2738         ubsec_feed2(sc);
2739         ubsecstats.hst_modexpcrt++;
2740         mtx_unlock(&sc->sc_mcr2lock);
2741         return (0);
2742
2743 errout:
2744         if (rp != NULL) {
2745                 if (rp->rpr_q.q_mcr.dma_map != NULL)
2746                         ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2747                 if (rp->rpr_msgin.dma_map != NULL) {
2748                         bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2749                         ubsec_dma_free(sc, &rp->rpr_msgin);
2750                 }
2751                 if (rp->rpr_msgout.dma_map != NULL) {
2752                         bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2753                         ubsec_dma_free(sc, &rp->rpr_msgout);
2754                 }
2755                 free(rp, M_DEVBUF);
2756         }
2757         krp->krp_status = err;
2758         crypto_kdone(krp);
2759         return (0);
2760 }
2761
2762 #ifdef UBSEC_DEBUG
2763 static void
2764 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2765 {
2766         printf("addr 0x%x (0x%x) next 0x%x\n",
2767             pb->pb_addr, pb->pb_len, pb->pb_next);
2768 }
2769
2770 static void
2771 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2772 {
2773         printf("CTX (0x%x):\n", c->ctx_len);
2774         switch (letoh16(c->ctx_op)) {
2775         case UBS_CTXOP_RNGBYPASS:
2776         case UBS_CTXOP_RNGSHA1:
2777                 break;
2778         case UBS_CTXOP_MODEXP:
2779         {
2780                 struct ubsec_ctx_modexp *cx = (void *)c;
2781                 int i, len;
2782
2783                 printf(" Elen %u, Nlen %u\n",
2784                     letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2785                 len = (cx->me_N_len + 7)/8;
2786                 for (i = 0; i < len; i++)
2787                         printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2788                 printf("\n");
2789                 break;
2790         }
2791         default:
2792                 printf("unknown context: %x\n", c->ctx_op);
2793         }
2794         printf("END CTX\n");
2795 }
2796
2797 static void
2798 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2799 {
2800         volatile struct ubsec_mcr_add *ma;
2801         int i;
2802
2803         printf("MCR:\n");
2804         printf(" pkts: %u, flags 0x%x\n",
2805             letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2806         ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2807         for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2808                 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2809                     letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2810                     letoh16(ma->mcr_reserved));
2811                 printf(" %d: ipkt ", i);
2812                 ubsec_dump_pb(&ma->mcr_ipktbuf);
2813                 printf(" %d: opkt ", i);
2814                 ubsec_dump_pb(&ma->mcr_opktbuf);
2815                 ma++;
2816         }
2817         printf("END MCR\n");
2818 }
2819 #endif /* UBSEC_DEBUG */
2820
2821 /*
2822  * Return the number of significant bits of a big number.
2823  */
2824 static int
2825 ubsec_ksigbits(struct crparam *cr)
2826 {
2827         u_int plen = (cr->crp_nbits + 7) / 8;
2828         int i, sig = plen * 8;
2829         u_int8_t c, *p = cr->crp_p;
2830
2831         for (i = plen - 1; i >= 0; i--) {
2832                 c = p[i];
2833                 if (c != 0) {
2834                         while ((c & 0x80) == 0) {
2835                                 sig--;
2836                                 c <<= 1;
2837                         }
2838                         break;
2839                 }
2840                 sig -= 8;
2841         }
2842         return (sig);
2843 }
2844
2845 static void
2846 ubsec_kshift_r(
2847         u_int shiftbits,
2848         u_int8_t *src, u_int srcbits,
2849         u_int8_t *dst, u_int dstbits)
2850 {
2851         u_int slen, dlen;
2852         int i, si, di, n;
2853
2854         slen = (srcbits + 7) / 8;
2855         dlen = (dstbits + 7) / 8;
2856
2857         for (i = 0; i < slen; i++)
2858                 dst[i] = src[i];
2859         for (i = 0; i < dlen - slen; i++)
2860                 dst[slen + i] = 0;
2861
2862         n = shiftbits / 8;
2863         if (n != 0) {
2864                 si = dlen - n - 1;
2865                 di = dlen - 1;
2866                 while (si >= 0)
2867                         dst[di--] = dst[si--];
2868                 while (di >= 0)
2869                         dst[di--] = 0;
2870         }
2871
2872         n = shiftbits % 8;
2873         if (n != 0) {
2874                 for (i = dlen - 1; i > 0; i--)
2875                         dst[i] = (dst[i] << n) |
2876                             (dst[i - 1] >> (8 - n));
2877                 dst[0] = dst[0] << n;
2878         }
2879 }
2880
2881 static void
2882 ubsec_kshift_l(
2883         u_int shiftbits,
2884         u_int8_t *src, u_int srcbits,
2885         u_int8_t *dst, u_int dstbits)
2886 {
2887         int slen, dlen, i, n;
2888
2889         slen = (srcbits + 7) / 8;
2890         dlen = (dstbits + 7) / 8;
2891
2892         n = shiftbits / 8;
2893         for (i = 0; i < slen; i++)
2894                 dst[i] = src[i + n];
2895         for (i = 0; i < dlen - slen; i++)
2896                 dst[slen + i] = 0;
2897
2898         n = shiftbits % 8;
2899         if (n != 0) {
2900                 for (i = 0; i < (dlen - 1); i++)
2901                         dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2902                 dst[dlen - 1] = dst[dlen - 1] >> n;
2903         }
2904 }