sys/dev/ubsec/ubsec.c

   1 /*      $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $       */
   2
   3 /*-
   4  * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
   5  * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
   6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by Jason L. Wright
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  33  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Effort sponsored in part by the Defense Advanced Research Projects
  37  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  38  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 /*
  45  * uBsec 5[56]01, 58xx hardware crypto accelerator
  46  */
  47
  48 #include "opt_ubsec.h"
  49
  50 #include <sys/param.h>
  51 #include <sys/systm.h>
  52 #include <sys/proc.h>
  53 #include <sys/errno.h>
  54 #include <sys/malloc.h>
  55 #include <sys/kernel.h>
  56 #include <sys/module.h>
  57 #include <sys/mbuf.h>
  58 #include <sys/lock.h>
  59 #include <sys/mutex.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/endian.h>
  62
  63 #include <vm/vm.h>
  64 #include <vm/pmap.h>
  65
  66 #include <machine/bus.h>
  67 #include <machine/resource.h>
  68 #include <sys/bus.h>
  69 #include <sys/rman.h>
  70
  71 #include <crypto/sha1.h>
  72 #include <opencrypto/cryptodev.h>
  73 #include <opencrypto/cryptosoft.h>
  74 #include <sys/md5.h>
  75 #include <sys/random.h>
  76
  77 #include <dev/pci/pcivar.h>
  78 #include <dev/pci/pcireg.h>
  79
  80 /* grr, #defines for gratuitous incompatibility in queue.h */
  81 #define SIMPLEQ_HEAD            STAILQ_HEAD
  82 #define SIMPLEQ_ENTRY           STAILQ_ENTRY
  83 #define SIMPLEQ_INIT            STAILQ_INIT
  84 #define SIMPLEQ_INSERT_TAIL     STAILQ_INSERT_TAIL
  85 #define SIMPLEQ_EMPTY           STAILQ_EMPTY
  86 #define SIMPLEQ_FIRST           STAILQ_FIRST
  87 #define SIMPLEQ_REMOVE_HEAD     STAILQ_REMOVE_HEAD_UNTIL
  88 #define SIMPLEQ_FOREACH         STAILQ_FOREACH
  89 /* ditto for endian.h */
  90 #define letoh16(x)              le16toh(x)
  91 #define letoh32(x)              le32toh(x)
  92
  93 #ifdef UBSEC_RNDTEST
  94 #include <dev/rndtest/rndtest.h>
  95 #endif
  96 #include <dev/ubsec/ubsecreg.h>
  97 #include <dev/ubsec/ubsecvar.h>
  98
  99 /*
 100  * Prototypes and count for the pci_device structure
 101  */
 102 static  int ubsec_probe(device_t);
 103 static  int ubsec_attach(device_t);
 104 static  int ubsec_detach(device_t);
 105 static  int ubsec_suspend(device_t);
 106 static  int ubsec_resume(device_t);
 107 static  void ubsec_shutdown(device_t);
 108
 109 static device_method_t ubsec_methods[] = {
 110         /* Device interface */
 111         DEVMETHOD(device_probe,         ubsec_probe),
 112         DEVMETHOD(device_attach,        ubsec_attach),
 113         DEVMETHOD(device_detach,        ubsec_detach),
 114         DEVMETHOD(device_suspend,       ubsec_suspend),
 115         DEVMETHOD(device_resume,        ubsec_resume),
 116         DEVMETHOD(device_shutdown,      ubsec_shutdown),
 117
 118         /* bus interface */
 119         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 120         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 121
 122         { 0, 0 }
 123 };
 124 static driver_t ubsec_driver = {
 125         "ubsec",
 126         ubsec_methods,
 127         sizeof (struct ubsec_softc)
 128 };
 129 static devclass_t ubsec_devclass;
 130
 131 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
 132 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
 133 #ifdef UBSEC_RNDTEST
 134 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
 135 #endif
 136
 137 static  void ubsec_intr(void *);
 138 static  int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
 139 static  int ubsec_freesession(void *, u_int64_t);
 140 static  int ubsec_process(void *, struct cryptop *, int);
 141 static  void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
 142 static  void ubsec_feed(struct ubsec_softc *);
 143 static  void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
 144 static  void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
 145 static  int ubsec_feed2(struct ubsec_softc *);
 146 static  void ubsec_rng(void *);
 147 static  int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
 148                              struct ubsec_dma_alloc *, int);
 149 #define ubsec_dma_sync(_dma, _flags) \
 150         bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
 151 static  void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
 152 static  int ubsec_dmamap_aligned(struct ubsec_operand *op);
 153
 154 static  void ubsec_reset_board(struct ubsec_softc *sc);
 155 static  void ubsec_init_board(struct ubsec_softc *sc);
 156 static  void ubsec_init_pciregs(device_t dev);
 157 static  void ubsec_totalreset(struct ubsec_softc *sc);
 158
 159 static  int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
 160
 161 static  int ubsec_kprocess(void*, struct cryptkop *, int);
 162 static  int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
 163 static  int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
 164 static  int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
 165 static  void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
 166 static  int ubsec_ksigbits(struct crparam *);
 167 static  void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 168 static  void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 169
 170 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
 171
 172 #ifdef UBSEC_DEBUG
 173 static  void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
 174 static  void ubsec_dump_mcr(struct ubsec_mcr *);
 175 static  void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
 176
 177 static  int ubsec_debug = 0;
 178 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
 179             0, "control debugging msgs");
 180 #endif
 181
 182 #define READ_REG(sc,r) \
 183         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
 184
 185 #define WRITE_REG(sc,reg,val) \
 186         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
 187
 188 #define SWAP32(x) (x) = htole32(ntohl((x)))
 189 #define HTOLE32(x) (x) = htole32(x)
 190
 191 struct ubsec_stats ubsecstats;
 192 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
 193             ubsec_stats, "driver statistics");
 194
 195 static int
 196 ubsec_probe(device_t dev)
 197 {
 198         if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 199             (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
 200              pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
 201                 return (BUS_PROBE_DEFAULT);
 202         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 203             (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
 204              pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
 205                 return (BUS_PROBE_DEFAULT);
 206         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 207             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
 208              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 209              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
 210              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
 211              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 212              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 213              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
 214              ))
 215                 return (BUS_PROBE_DEFAULT);
 216         return (ENXIO);
 217 }
 218
 219 static const char*
 220 ubsec_partname(struct ubsec_softc *sc)
 221 {
 222         /* XXX sprintf numbers when not decoded */
 223         switch (pci_get_vendor(sc->sc_dev)) {
 224         case PCI_VENDOR_BROADCOM:
 225                 switch (pci_get_device(sc->sc_dev)) {
 226                 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
 227                 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
 228                 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
 229                 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
 230                 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
 231                 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
 232                 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
 233                 }
 234                 return "Broadcom unknown-part";
 235         case PCI_VENDOR_BLUESTEEL:
 236                 switch (pci_get_device(sc->sc_dev)) {
 237                 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
 238                 }
 239                 return "Bluesteel unknown-part";
 240         case PCI_VENDOR_SUN:
 241                 switch (pci_get_device(sc->sc_dev)) {
 242                 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
 243                 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
 244                 }
 245                 return "Sun unknown-part";
 246         }
 247         return "Unknown-vendor unknown-part";
 248 }
 249
 250 static void
 251 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 252 {
 253         random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
 254 }
 255
 256 static int
 257 ubsec_attach(device_t dev)
 258 {
 259         struct ubsec_softc *sc = device_get_softc(dev);
 260         struct ubsec_dma *dmap;
 261         u_int32_t cmd, i;
 262         int rid;
 263
 264         bzero(sc, sizeof (*sc));
 265         sc->sc_dev = dev;
 266
 267         SIMPLEQ_INIT(&sc->sc_queue);
 268         SIMPLEQ_INIT(&sc->sc_qchip);
 269         SIMPLEQ_INIT(&sc->sc_queue2);
 270         SIMPLEQ_INIT(&sc->sc_qchip2);
 271         SIMPLEQ_INIT(&sc->sc_q2free);
 272
 273         /* XXX handle power management */
 274
 275         sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
 276
 277         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 278             pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
 279                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 280
 281         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 282             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 283              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
 284                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 285
 286         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 287             pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
 288                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 289                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 290
 291         if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 292              (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 293               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 294               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
 295             (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 296              (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
 297               pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
 298                 /* NB: the 5821/5822 defines some additional status bits */
 299                 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
 300                     BS_STAT_MCR2_ALLEMPTY;
 301                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 302                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 303         }
 304
 305         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 306         cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
 307         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
 308         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
 309
 310         if (!(cmd & PCIM_CMD_MEMEN)) {
 311                 device_printf(dev, "failed to enable memory mapping\n");
 312                 goto bad;
 313         }
 314
 315         if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
 316                 device_printf(dev, "failed to enable bus mastering\n");
 317                 goto bad;
 318         }
 319
 320         /*
 321          * Setup memory-mapping of PCI registers.
 322          */
 323         rid = BS_BAR;
 324         sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 325                                            RF_ACTIVE);
 326         if (sc->sc_sr == NULL) {
 327                 device_printf(dev, "cannot map register space\n");
 328                 goto bad;
 329         }
 330         sc->sc_st = rman_get_bustag(sc->sc_sr);
 331         sc->sc_sh = rman_get_bushandle(sc->sc_sr);
 332
 333         /*
 334          * Arrange interrupt line.
 335          */
 336         rid = 0;
 337         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 338                                             RF_SHAREABLE|RF_ACTIVE);
 339         if (sc->sc_irq == NULL) {
 340                 device_printf(dev, "could not map interrupt\n");
 341                 goto bad1;
 342         }
 343         /*
 344          * NB: Network code assumes we are blocked with splimp()
 345          *     so make sure the IRQ is mapped appropriately.
 346          */
 347         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 348                            ubsec_intr, sc, &sc->sc_ih)) {
 349                 device_printf(dev, "could not establish interrupt\n");
 350                 goto bad2;
 351         }
 352
 353         sc->sc_cid = crypto_get_driverid(0);
 354         if (sc->sc_cid < 0) {
 355                 device_printf(dev, "could not get crypto driver id\n");
 356                 goto bad3;
 357         }
 358
 359         /*
 360          * Setup DMA descriptor area.
 361          */
 362         if (bus_dma_tag_create(NULL,                    /* parent */
 363                                1, 0,                    /* alignment, bounds */
 364                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 365                                BUS_SPACE_MAXADDR,       /* highaddr */
 366                                NULL, NULL,              /* filter, filterarg */
 367                                0x3ffff,                 /* maxsize */
 368                                UBS_MAX_SCATTER,         /* nsegments */
 369                                0xffff,                  /* maxsegsize */
 370                                BUS_DMA_ALLOCNOW,        /* flags */
 371                                NULL, NULL,              /* lockfunc, lockarg */
 372                                &sc->sc_dmat)) {
 373                 device_printf(dev, "cannot allocate DMA tag\n");
 374                 goto bad4;
 375         }
 376         SIMPLEQ_INIT(&sc->sc_freequeue);
 377         dmap = sc->sc_dmaa;
 378         for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
 379                 struct ubsec_q *q;
 380
 381                 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
 382                     M_DEVBUF, M_NOWAIT);
 383                 if (q == NULL) {
 384                         device_printf(dev, "cannot allocate queue buffers\n");
 385                         break;
 386                 }
 387
 388                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
 389                     &dmap->d_alloc, 0)) {
 390                         device_printf(dev, "cannot allocate dma buffers\n");
 391                         free(q, M_DEVBUF);
 392                         break;
 393                 }
 394                 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
 395
 396                 q->q_dma = dmap;
 397                 sc->sc_queuea[i] = q;
 398
 399                 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 400         }
 401         mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
 402                 "mcr1 operations", MTX_DEF);
 403         mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
 404                 "mcr1 free q", MTX_DEF);
 405
 406         device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
 407
 408         crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
 409             ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 410         crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
 411              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 412         crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
 413              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 414         crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
 415              ubsec_newsession, ubsec_freesession, ubsec_process, sc);
 416
 417         /*
 418          * Reset Broadcom chip
 419          */
 420         ubsec_reset_board(sc);
 421
 422         /*
 423          * Init Broadcom specific PCI settings
 424          */
 425         ubsec_init_pciregs(dev);
 426
 427         /*
 428          * Init Broadcom chip
 429          */
 430         ubsec_init_board(sc);
 431
 432 #ifndef UBSEC_NO_RNG
 433         if (sc->sc_flags & UBS_FLAGS_RNG) {
 434                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 435 #ifdef UBSEC_RNDTEST
 436                 sc->sc_rndtest = rndtest_attach(dev);
 437                 if (sc->sc_rndtest)
 438                         sc->sc_harvest = rndtest_harvest;
 439                 else
 440                         sc->sc_harvest = default_harvest;
 441 #else
 442                 sc->sc_harvest = default_harvest;
 443 #endif
 444
 445                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 446                     &sc->sc_rng.rng_q.q_mcr, 0))
 447                         goto skip_rng;
 448
 449                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
 450                     &sc->sc_rng.rng_q.q_ctx, 0)) {
 451                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 452                         goto skip_rng;
 453                 }
 454
 455                 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
 456                     UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
 457                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 458                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 459                         goto skip_rng;
 460                 }
 461
 462                 if (hz >= 100)
 463                         sc->sc_rnghz = hz / 100;
 464                 else
 465                         sc->sc_rnghz = 1;
 466                 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
 467                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
 468 skip_rng:
 469         ;
 470         }
 471 #endif /* UBSEC_NO_RNG */
 472         mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
 473                 "mcr2 operations", MTX_DEF);
 474
 475         if (sc->sc_flags & UBS_FLAGS_KEY) {
 476                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 477
 478                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
 479                         ubsec_kprocess, sc);
 480 #if 0
 481                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
 482                         ubsec_kprocess, sc);
 483 #endif
 484         }
 485         return (0);
 486 bad4:
 487         crypto_unregister_all(sc->sc_cid);
 488 bad3:
 489         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 490 bad2:
 491         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 492 bad1:
 493         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 494 bad:
 495         return (ENXIO);
 496 }
 497
 498 /*
 499  * Detach a device that successfully probed.
 500  */
 501 static int
 502 ubsec_detach(device_t dev)
 503 {
 504         struct ubsec_softc *sc = device_get_softc(dev);
 505
 506         /* XXX wait/abort active ops */
 507
 508         /* disable interrupts */
 509         WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
 510                 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
 511
 512         callout_stop(&sc->sc_rngto);
 513
 514         crypto_unregister_all(sc->sc_cid);
 515
 516 #ifdef UBSEC_RNDTEST
 517         if (sc->sc_rndtest)
 518                 rndtest_detach(sc->sc_rndtest);
 519 #endif
 520
 521         while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
 522                 struct ubsec_q *q;
 523
 524                 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
 525                 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
 526                 ubsec_dma_free(sc, &q->q_dma->d_alloc);
 527                 free(q, M_DEVBUF);
 528         }
 529         mtx_destroy(&sc->sc_mcr1lock);
 530         mtx_destroy(&sc->sc_freeqlock);
 531 #ifndef UBSEC_NO_RNG
 532         if (sc->sc_flags & UBS_FLAGS_RNG) {
 533                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 534                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 535                 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
 536         }
 537 #endif /* UBSEC_NO_RNG */
 538         mtx_destroy(&sc->sc_mcr2lock);
 539
 540         bus_generic_detach(dev);
 541         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 542         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 543
 544         bus_dma_tag_destroy(sc->sc_dmat);
 545         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 546
 547         return (0);
 548 }
 549
 550 /*
 551  * Stop all chip i/o so that the kernel's probe routines don't
 552  * get confused by errant DMAs when rebooting.
 553  */
 554 static void
 555 ubsec_shutdown(device_t dev)
 556 {
 557 #ifdef notyet
 558         ubsec_stop(device_get_softc(dev));
 559 #endif
 560 }
 561
 562 /*
 563  * Device suspend routine.
 564  */
 565 static int
 566 ubsec_suspend(device_t dev)
 567 {
 568         struct ubsec_softc *sc = device_get_softc(dev);
 569
 570 #ifdef notyet
 571         /* XXX stop the device and save PCI settings */
 572 #endif
 573         sc->sc_suspended = 1;
 574
 575         return (0);
 576 }
 577
 578 static int
 579 ubsec_resume(device_t dev)
 580 {
 581         struct ubsec_softc *sc = device_get_softc(dev);
 582
 583 #ifdef notyet
 584         /* XXX retore PCI settings and start the device */
 585 #endif
 586         sc->sc_suspended = 0;
 587         return (0);
 588 }
 589
 590 /*
 591  * UBSEC Interrupt routine
 592  */
 593 static void
 594 ubsec_intr(void *arg)
 595 {
 596         struct ubsec_softc *sc = arg;
 597         volatile u_int32_t stat;
 598         struct ubsec_q *q;
 599         struct ubsec_dma *dmap;
 600         int npkts = 0, i;
 601
 602         stat = READ_REG(sc, BS_STAT);
 603         stat &= sc->sc_statmask;
 604         if (stat == 0)
 605                 return;
 606
 607         WRITE_REG(sc, BS_STAT, stat);           /* IACK */
 608
 609         /*
 610          * Check to see if we have any packets waiting for us
 611          */
 612         if ((stat & BS_STAT_MCR1_DONE)) {
 613                 mtx_lock(&sc->sc_mcr1lock);
 614                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
 615                         q = SIMPLEQ_FIRST(&sc->sc_qchip);
 616                         dmap = q->q_dma;
 617
 618                         if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
 619                                 break;
 620
 621                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
 622
 623                         npkts = q->q_nstacked_mcrs;
 624                         sc->sc_nqchip -= 1+npkts;
 625                         /*
 626                          * search for further sc_qchip ubsec_q's that share
 627                          * the same MCR, and complete them too, they must be
 628                          * at the top.
 629                          */
 630                         for (i = 0; i < npkts; i++) {
 631                                 if(q->q_stacked_mcr[i]) {
 632                                         ubsec_callback(sc, q->q_stacked_mcr[i]);
 633                                 } else {
 634                                         break;
 635                                 }
 636                         }
 637                         ubsec_callback(sc, q);
 638                 }
 639                 /*
 640                  * Don't send any more packet to chip if there has been
 641                  * a DMAERR.
 642                  */
 643                 if (!(stat & BS_STAT_DMAERR))
 644                         ubsec_feed(sc);
 645                 mtx_unlock(&sc->sc_mcr1lock);
 646         }
 647
 648         /*
 649          * Check to see if we have any key setups/rng's waiting for us
 650          */
 651         if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
 652             (stat & BS_STAT_MCR2_DONE)) {
 653                 struct ubsec_q2 *q2;
 654                 struct ubsec_mcr *mcr;
 655
 656                 mtx_lock(&sc->sc_mcr2lock);
 657                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
 658                         q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
 659
 660                         ubsec_dma_sync(&q2->q_mcr,
 661                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 662
 663                         mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
 664                         if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
 665                                 ubsec_dma_sync(&q2->q_mcr,
 666                                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 667                                 break;
 668                         }
 669                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next);
 670                         ubsec_callback2(sc, q2);
 671                         /*
 672                          * Don't send any more packet to chip if there has been
 673                          * a DMAERR.
 674                          */
 675                         if (!(stat & BS_STAT_DMAERR))
 676                                 ubsec_feed2(sc);
 677                 }
 678                 mtx_unlock(&sc->sc_mcr2lock);
 679         }
 680
 681         /*
 682          * Check to see if we got any DMA Error
 683          */
 684         if (stat & BS_STAT_DMAERR) {
 685 #ifdef UBSEC_DEBUG
 686                 if (ubsec_debug) {
 687                         volatile u_int32_t a = READ_REG(sc, BS_ERR);
 688
 689                         printf("dmaerr %s@%08x\n",
 690                             (a & BS_ERR_READ) ? "read" : "write",
 691                             a & BS_ERR_ADDR);
 692                 }
 693 #endif /* UBSEC_DEBUG */
 694                 ubsecstats.hst_dmaerr++;
 695                 mtx_lock(&sc->sc_mcr1lock);
 696                 ubsec_totalreset(sc);
 697                 ubsec_feed(sc);
 698                 mtx_unlock(&sc->sc_mcr1lock);
 699         }
 700
 701         if (sc->sc_needwakeup) {                /* XXX check high watermark */
 702                 int wakeup;
 703
 704                 mtx_lock(&sc->sc_freeqlock);
 705                 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
 706 #ifdef UBSEC_DEBUG
 707                 if (ubsec_debug)
 708                         device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
 709                                 sc->sc_needwakeup);
 710 #endif /* UBSEC_DEBUG */
 711                 sc->sc_needwakeup &= ~wakeup;
 712                 mtx_unlock(&sc->sc_freeqlock);
 713                 crypto_unblock(sc->sc_cid, wakeup);
 714         }
 715 }
 716
 717 /*
 718  * ubsec_feed() - aggregate and post requests to chip
 719  */
 720 static void
 721 ubsec_feed(struct ubsec_softc *sc)
 722 {
 723         struct ubsec_q *q, *q2;
 724         int npkts, i;
 725         void *v;
 726         u_int32_t stat;
 727
 728         /*
 729          * Decide how many ops to combine in a single MCR.  We cannot
 730          * aggregate more than UBS_MAX_AGGR because this is the number
 731          * of slots defined in the data structure.  Note that
 732          * aggregation only happens if ops are marked batch'able.
 733          * Aggregating ops reduces the number of interrupts to the host
 734          * but also (potentially) increases the latency for processing
 735          * completed ops as we only get an interrupt when all aggregated
 736          * ops have completed.
 737          */
 738         if (sc->sc_nqueue == 0)
 739                 return;
 740         if (sc->sc_nqueue > 1) {
 741                 npkts = 0;
 742                 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
 743                         npkts++;
 744                         if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
 745                                 break;
 746                 }
 747         } else
 748                 npkts = 1;
 749         /*
 750          * Check device status before going any further.
 751          */
 752         if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
 753                 if (stat & BS_STAT_DMAERR) {
 754                         ubsec_totalreset(sc);
 755                         ubsecstats.hst_dmaerr++;
 756                 } else
 757                         ubsecstats.hst_mcr1full++;
 758                 return;
 759         }
 760         if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
 761                 ubsecstats.hst_maxqueue = sc->sc_nqueue;
 762         if (npkts > UBS_MAX_AGGR)
 763                 npkts = UBS_MAX_AGGR;
 764         if (npkts < 2)                          /* special case 1 op */
 765                 goto feed1;
 766
 767         ubsecstats.hst_totbatch += npkts-1;
 768 #ifdef UBSEC_DEBUG
 769         if (ubsec_debug)
 770                 printf("merging %d records\n", npkts);
 771 #endif /* UBSEC_DEBUG */
 772
 773         q = SIMPLEQ_FIRST(&sc->sc_queue);
 774         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
 775         --sc->sc_nqueue;
 776
 777         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 778         if (q->q_dst_map != NULL)
 779                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 780
 781         q->q_nstacked_mcrs = npkts - 1;         /* Number of packets stacked */
 782
 783         for (i = 0; i < q->q_nstacked_mcrs; i++) {
 784                 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
 785                 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
 786                     BUS_DMASYNC_PREWRITE);
 787                 if (q2->q_dst_map != NULL)
 788                         bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
 789                             BUS_DMASYNC_PREREAD);
 790                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next);
 791                 --sc->sc_nqueue;
 792
 793                 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
 794                     sizeof(struct ubsec_mcr_add));
 795                 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
 796                 q->q_stacked_mcr[i] = q2;
 797         }
 798         q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
 799         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 800         sc->sc_nqchip += npkts;
 801         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 802                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 803         ubsec_dma_sync(&q->q_dma->d_alloc,
 804             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 805         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 806             offsetof(struct ubsec_dmachunk, d_mcr));
 807         return;
 808 feed1:
 809         q = SIMPLEQ_FIRST(&sc->sc_queue);
 810
 811         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 812         if (q->q_dst_map != NULL)
 813                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 814         ubsec_dma_sync(&q->q_dma->d_alloc,
 815             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 816
 817         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 818             offsetof(struct ubsec_dmachunk, d_mcr));
 819 #ifdef UBSEC_DEBUG
 820         if (ubsec_debug)
 821                 printf("feed1: q->chip %p %08x stat %08x\n",
 822                       q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
 823                       stat);
 824 #endif /* UBSEC_DEBUG */
 825         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
 826         --sc->sc_nqueue;
 827         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 828         sc->sc_nqchip++;
 829         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 830                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 831         return;
 832 }
 833
 834 static void
 835 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
 836 {
 837
 838         /* Go ahead and compute key in ubsec's byte order */
 839         if (algo == CRYPTO_DES_CBC) {
 840                 bcopy(key, &ses->ses_deskey[0], 8);
 841                 bcopy(key, &ses->ses_deskey[2], 8);
 842                 bcopy(key, &ses->ses_deskey[4], 8);
 843         } else
 844                 bcopy(key, ses->ses_deskey, 24);
 845
 846         SWAP32(ses->ses_deskey[0]);
 847         SWAP32(ses->ses_deskey[1]);
 848         SWAP32(ses->ses_deskey[2]);
 849         SWAP32(ses->ses_deskey[3]);
 850         SWAP32(ses->ses_deskey[4]);
 851         SWAP32(ses->ses_deskey[5]);
 852 }
 853
 854 static void
 855 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
 856 {
 857         MD5_CTX md5ctx;
 858         SHA1_CTX sha1ctx;
 859         int i;
 860
 861         for (i = 0; i < klen; i++)
 862                 key[i] ^= HMAC_IPAD_VAL;
 863
 864         if (algo == CRYPTO_MD5_HMAC) {
 865                 MD5Init(&md5ctx);
 866                 MD5Update(&md5ctx, key, klen);
 867                 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 868                 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
 869         } else {
 870                 SHA1Init(&sha1ctx);
 871                 SHA1Update(&sha1ctx, key, klen);
 872                 SHA1Update(&sha1ctx, hmac_ipad_buffer,
 873                     SHA1_HMAC_BLOCK_LEN - klen);
 874                 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
 875         }
 876
 877         for (i = 0; i < klen; i++)
 878                 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
 879
 880         if (algo == CRYPTO_MD5_HMAC) {
 881                 MD5Init(&md5ctx);
 882                 MD5Update(&md5ctx, key, klen);
 883                 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 884                 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
 885         } else {
 886                 SHA1Init(&sha1ctx);
 887                 SHA1Update(&sha1ctx, key, klen);
 888                 SHA1Update(&sha1ctx, hmac_opad_buffer,
 889                     SHA1_HMAC_BLOCK_LEN - klen);
 890                 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
 891         }
 892
 893         for (i = 0; i < klen; i++)
 894                 key[i] ^= HMAC_OPAD_VAL;
 895 }
 896
 897 /*
 898  * Allocate a new 'session' and return an encoded session id.  'sidp'
 899  * contains our registration id, and should contain an encoded session
 900  * id on successful allocation.
 901  */
 902 static int
 903 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
 904 {
 905         struct cryptoini *c, *encini = NULL, *macini = NULL;
 906         struct ubsec_softc *sc = arg;
 907         struct ubsec_session *ses = NULL;
 908         int sesn;
 909
 910         if (sidp == NULL || cri == NULL || sc == NULL)
 911                 return (EINVAL);
 912
 913         for (c = cri; c != NULL; c = c->cri_next) {
 914                 if (c->cri_alg == CRYPTO_MD5_HMAC ||
 915                     c->cri_alg == CRYPTO_SHA1_HMAC) {
 916                         if (macini)
 917                                 return (EINVAL);
 918                         macini = c;
 919                 } else if (c->cri_alg == CRYPTO_DES_CBC ||
 920                     c->cri_alg == CRYPTO_3DES_CBC) {
 921                         if (encini)
 922                                 return (EINVAL);
 923                         encini = c;
 924                 } else
 925                         return (EINVAL);
 926         }
 927         if (encini == NULL && macini == NULL)
 928                 return (EINVAL);
 929
 930         if (sc->sc_sessions == NULL) {
 931                 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
 932                     sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 933                 if (ses == NULL)
 934                         return (ENOMEM);
 935                 sesn = 0;
 936                 sc->sc_nsessions = 1;
 937         } else {
 938                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
 939                         if (sc->sc_sessions[sesn].ses_used == 0) {
 940                                 ses = &sc->sc_sessions[sesn];
 941                                 break;
 942                         }
 943                 }
 944
 945                 if (ses == NULL) {
 946                         sesn = sc->sc_nsessions;
 947                         ses = (struct ubsec_session *)malloc((sesn + 1) *
 948                             sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 949                         if (ses == NULL)
 950                                 return (ENOMEM);
 951                         bcopy(sc->sc_sessions, ses, sesn *
 952                             sizeof(struct ubsec_session));
 953                         bzero(sc->sc_sessions, sesn *
 954                             sizeof(struct ubsec_session));
 955                         free(sc->sc_sessions, M_DEVBUF);
 956                         sc->sc_sessions = ses;
 957                         ses = &sc->sc_sessions[sesn];
 958                         sc->sc_nsessions++;
 959                 }
 960         }
 961         bzero(ses, sizeof(struct ubsec_session));
 962         ses->ses_used = 1;
 963
 964         if (encini) {
 965                 /* get an IV, network byte order */
 966                 /* XXX may read fewer than requested */
 967                 read_random(ses->ses_iv, sizeof(ses->ses_iv));
 968
 969                 if (encini->cri_key != NULL) {
 970                         ubsec_setup_enckey(ses, encini->cri_alg,
 971                             encini->cri_key);
 972                 }
 973         }
 974
 975         if (macini) {
 976                 ses->ses_mlen = macini->cri_mlen;
 977                 if (ses->ses_mlen == 0) {
 978                         if (macini->cri_alg == CRYPTO_MD5_HMAC)
 979                                 ses->ses_mlen = MD5_HASH_LEN;
 980                         else
 981                                 ses->ses_mlen = SHA1_HASH_LEN;
 982                 }
 983
 984                 if (macini->cri_key != NULL) {
 985                         ubsec_setup_mackey(ses, macini->cri_alg,
 986                             macini->cri_key, macini->cri_klen / 8);
 987                 }
 988         }
 989
 990         *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
 991         return (0);
 992 }
 993
 994 /*
 995  * Deallocate a session.
 996  */
 997 static int
 998 ubsec_freesession(void *arg, u_int64_t tid)
 999 {
1000         struct ubsec_softc *sc = arg;
1001         int session, ret;
1002         u_int32_t sid = CRYPTO_SESID2LID(tid);
1003
1004         if (sc == NULL)
1005                 return (EINVAL);
1006
1007         session = UBSEC_SESSION(sid);
1008         if (session < sc->sc_nsessions) {
1009                 bzero(&sc->sc_sessions[session],
1010                         sizeof(sc->sc_sessions[session]));
1011                 ret = 0;
1012         } else
1013                 ret = EINVAL;
1014
1015         return (ret);
1016 }
1017
1018 static void
1019 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1020 {
1021         struct ubsec_operand *op = arg;
1022
1023         KASSERT(nsegs <= UBS_MAX_SCATTER,
1024                 ("Too many DMA segments returned when mapping operand"));
1025 #ifdef UBSEC_DEBUG
1026         if (ubsec_debug)
1027                 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1028                         (u_int) mapsize, nsegs, error);
1029 #endif
1030         if (error != 0)
1031                 return;
1032         op->mapsize = mapsize;
1033         op->nsegs = nsegs;
1034         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1035 }
1036
1037 static int
1038 ubsec_process(void *arg, struct cryptop *crp, int hint)
1039 {
1040         struct ubsec_q *q = NULL;
1041         int err = 0, i, j, nicealign;
1042         struct ubsec_softc *sc = arg;
1043         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1044         int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1045         int sskip, dskip, stheend, dtheend;
1046         int16_t coffset;
1047         struct ubsec_session *ses;
1048         struct ubsec_pktctx ctx;
1049         struct ubsec_dma *dmap = NULL;
1050
1051         if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1052                 ubsecstats.hst_invalid++;
1053                 return (EINVAL);
1054         }
1055         if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1056                 ubsecstats.hst_badsession++;
1057                 return (EINVAL);
1058         }
1059
1060         mtx_lock(&sc->sc_freeqlock);
1061         if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1062                 ubsecstats.hst_queuefull++;
1063                 sc->sc_needwakeup |= CRYPTO_SYMQ;
1064                 mtx_unlock(&sc->sc_freeqlock);
1065                 return (ERESTART);
1066         }
1067         q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1068         SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
1069         mtx_unlock(&sc->sc_freeqlock);
1070
1071         dmap = q->q_dma; /* Save dma pointer */
1072         bzero(q, sizeof(struct ubsec_q));
1073         bzero(&ctx, sizeof(ctx));
1074
1075         q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1076         q->q_dma = dmap;
1077         ses = &sc->sc_sessions[q->q_sesn];
1078
1079         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1080                 q->q_src_m = (struct mbuf *)crp->crp_buf;
1081                 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1082         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1083                 q->q_src_io = (struct uio *)crp->crp_buf;
1084                 q->q_dst_io = (struct uio *)crp->crp_buf;
1085         } else {
1086                 ubsecstats.hst_badflags++;
1087                 err = EINVAL;
1088                 goto errout;    /* XXX we don't handle contiguous blocks! */
1089         }
1090
1091         bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1092
1093         dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1094         dmap->d_dma->d_mcr.mcr_flags = 0;
1095         q->q_crp = crp;
1096
1097         crd1 = crp->crp_desc;
1098         if (crd1 == NULL) {
1099                 ubsecstats.hst_nodesc++;
1100                 err = EINVAL;
1101                 goto errout;
1102         }
1103         crd2 = crd1->crd_next;
1104
1105         if (crd2 == NULL) {
1106                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1107                     crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1108                         maccrd = crd1;
1109                         enccrd = NULL;
1110                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1111                     crd1->crd_alg == CRYPTO_3DES_CBC) {
1112                         maccrd = NULL;
1113                         enccrd = crd1;
1114                 } else {
1115                         ubsecstats.hst_badalg++;
1116                         err = EINVAL;
1117                         goto errout;
1118                 }
1119         } else {
1120                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1121                     crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1122                     (crd2->crd_alg == CRYPTO_DES_CBC ||
1123                         crd2->crd_alg == CRYPTO_3DES_CBC) &&
1124                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1125                         maccrd = crd1;
1126                         enccrd = crd2;
1127                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1128                     crd1->crd_alg == CRYPTO_3DES_CBC) &&
1129                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1130                         crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1131                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
1132                         enccrd = crd1;
1133                         maccrd = crd2;
1134                 } else {
1135                         /*
1136                          * We cannot order the ubsec as requested
1137                          */
1138                         ubsecstats.hst_badalg++;
1139                         err = EINVAL;
1140                         goto errout;
1141                 }
1142         }
1143
1144         if (enccrd) {
1145                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1146                         ubsec_setup_enckey(ses, enccrd->crd_alg,
1147                             enccrd->crd_key);
1148                 }
1149
1150                 encoffset = enccrd->crd_skip;
1151                 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1152
1153                 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1154                         q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1155
1156                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1157                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1158                         else {
1159                                 ctx.pc_iv[0] = ses->ses_iv[0];
1160                                 ctx.pc_iv[1] = ses->ses_iv[1];
1161                         }
1162
1163                         if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1164                                 crypto_copyback(crp->crp_flags, crp->crp_buf,
1165                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1166                         }
1167                 } else {
1168                         ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1169
1170                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1171                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1172                         else {
1173                                 crypto_copydata(crp->crp_flags, crp->crp_buf,
1174                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1175                         }
1176                 }
1177
1178                 ctx.pc_deskey[0] = ses->ses_deskey[0];
1179                 ctx.pc_deskey[1] = ses->ses_deskey[1];
1180                 ctx.pc_deskey[2] = ses->ses_deskey[2];
1181                 ctx.pc_deskey[3] = ses->ses_deskey[3];
1182                 ctx.pc_deskey[4] = ses->ses_deskey[4];
1183                 ctx.pc_deskey[5] = ses->ses_deskey[5];
1184                 SWAP32(ctx.pc_iv[0]);
1185                 SWAP32(ctx.pc_iv[1]);
1186         }
1187
1188         if (maccrd) {
1189                 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1190                         ubsec_setup_mackey(ses, maccrd->crd_alg,
1191                             maccrd->crd_key, maccrd->crd_klen / 8);
1192                 }
1193
1194                 macoffset = maccrd->crd_skip;
1195
1196                 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1197                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1198                 else
1199                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1200
1201                 for (i = 0; i < 5; i++) {
1202                         ctx.pc_hminner[i] = ses->ses_hminner[i];
1203                         ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1204
1205                         HTOLE32(ctx.pc_hminner[i]);
1206                         HTOLE32(ctx.pc_hmouter[i]);
1207                 }
1208         }
1209
1210         if (enccrd && maccrd) {
1211                 /*
1212                  * ubsec cannot handle packets where the end of encryption
1213                  * and authentication are not the same, or where the
1214                  * encrypted part begins before the authenticated part.
1215                  */
1216                 if ((encoffset + enccrd->crd_len) !=
1217                     (macoffset + maccrd->crd_len)) {
1218                         ubsecstats.hst_lenmismatch++;
1219                         err = EINVAL;
1220                         goto errout;
1221                 }
1222                 if (enccrd->crd_skip < maccrd->crd_skip) {
1223                         ubsecstats.hst_skipmismatch++;
1224                         err = EINVAL;
1225                         goto errout;
1226                 }
1227                 sskip = maccrd->crd_skip;
1228                 cpskip = dskip = enccrd->crd_skip;
1229                 stheend = maccrd->crd_len;
1230                 dtheend = enccrd->crd_len;
1231                 coffset = enccrd->crd_skip - maccrd->crd_skip;
1232                 cpoffset = cpskip + dtheend;
1233 #ifdef UBSEC_DEBUG
1234                 if (ubsec_debug) {
1235                         printf("mac: skip %d, len %d, inject %d\n",
1236                             maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1237                         printf("enc: skip %d, len %d, inject %d\n",
1238                             enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1239                         printf("src: skip %d, len %d\n", sskip, stheend);
1240                         printf("dst: skip %d, len %d\n", dskip, dtheend);
1241                         printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1242                             coffset, stheend, cpskip, cpoffset);
1243                 }
1244 #endif
1245         } else {
1246                 cpskip = dskip = sskip = macoffset + encoffset;
1247                 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1248                 cpoffset = cpskip + dtheend;
1249                 coffset = 0;
1250         }
1251         ctx.pc_offset = htole16(coffset >> 2);
1252
1253         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1254                 ubsecstats.hst_nomap++;
1255                 err = ENOMEM;
1256                 goto errout;
1257         }
1258         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1259                 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1260                     q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1261                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1262                         q->q_src_map = NULL;
1263                         ubsecstats.hst_noload++;
1264                         err = ENOMEM;
1265                         goto errout;
1266                 }
1267         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1268                 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1269                     q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1270                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1271                         q->q_src_map = NULL;
1272                         ubsecstats.hst_noload++;
1273                         err = ENOMEM;
1274                         goto errout;
1275                 }
1276         }
1277         nicealign = ubsec_dmamap_aligned(&q->q_src);
1278
1279         dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1280
1281 #ifdef UBSEC_DEBUG
1282         if (ubsec_debug)
1283                 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1284 #endif
1285         for (i = j = 0; i < q->q_src_nsegs; i++) {
1286                 struct ubsec_pktbuf *pb;
1287                 bus_size_t packl = q->q_src_segs[i].ds_len;
1288                 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1289
1290                 if (sskip >= packl) {
1291                         sskip -= packl;
1292                         continue;
1293                 }
1294
1295                 packl -= sskip;
1296                 packp += sskip;
1297                 sskip = 0;
1298
1299                 if (packl > 0xfffc) {
1300                         err = EIO;
1301                         goto errout;
1302                 }
1303
1304                 if (j == 0)
1305                         pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1306                 else
1307                         pb = &dmap->d_dma->d_sbuf[j - 1];
1308
1309                 pb->pb_addr = htole32(packp);
1310
1311                 if (stheend) {
1312                         if (packl > stheend) {
1313                                 pb->pb_len = htole32(stheend);
1314                                 stheend = 0;
1315                         } else {
1316                                 pb->pb_len = htole32(packl);
1317                                 stheend -= packl;
1318                         }
1319                 } else
1320                         pb->pb_len = htole32(packl);
1321
1322                 if ((i + 1) == q->q_src_nsegs)
1323                         pb->pb_next = 0;
1324                 else
1325                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1326                             offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1327                 j++;
1328         }
1329
1330         if (enccrd == NULL && maccrd != NULL) {
1331                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1332                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1333                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1334                     offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1335 #ifdef UBSEC_DEBUG
1336                 if (ubsec_debug)
1337                         printf("opkt: %x %x %x\n",
1338                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1339                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1340                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1341 #endif
1342         } else {
1343                 if (crp->crp_flags & CRYPTO_F_IOV) {
1344                         if (!nicealign) {
1345                                 ubsecstats.hst_iovmisaligned++;
1346                                 err = EINVAL;
1347                                 goto errout;
1348                         }
1349                         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1350                              &q->q_dst_map)) {
1351                                 ubsecstats.hst_nomap++;
1352                                 err = ENOMEM;
1353                                 goto errout;
1354                         }
1355                         if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1356                             q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1357                                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1358                                 q->q_dst_map = NULL;
1359                                 ubsecstats.hst_noload++;
1360                                 err = ENOMEM;
1361                                 goto errout;
1362                         }
1363                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1364                         if (nicealign) {
1365                                 q->q_dst = q->q_src;
1366                         } else {
1367                                 int totlen, len;
1368                                 struct mbuf *m, *top, **mp;
1369
1370                                 ubsecstats.hst_unaligned++;
1371                                 totlen = q->q_src_mapsize;
1372                                 if (q->q_src_m->m_flags & M_PKTHDR) {
1373                                         len = MHLEN;
1374                                         MGETHDR(m, M_DONTWAIT, MT_DATA);
1375                                         if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) {
1376                                                 m_free(m);
1377                                                 m = NULL;
1378                                         }
1379                                 } else {
1380                                         len = MLEN;
1381                                         MGET(m, M_DONTWAIT, MT_DATA);
1382                                 }
1383                                 if (m == NULL) {
1384                                         ubsecstats.hst_nombuf++;
1385                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
1386                                         goto errout;
1387                                 }
1388                                 if (totlen >= MINCLSIZE) {
1389                                         MCLGET(m, M_DONTWAIT);
1390                                         if ((m->m_flags & M_EXT) == 0) {
1391                                                 m_free(m);
1392                                                 ubsecstats.hst_nomcl++;
1393                                                 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1394                                                 goto errout;
1395                                         }
1396                                         len = MCLBYTES;
1397                                 }
1398                                 m->m_len = len;
1399                                 top = NULL;
1400                                 mp = &top;
1401
1402                                 while (totlen > 0) {
1403                                         if (top) {
1404                                                 MGET(m, M_DONTWAIT, MT_DATA);
1405                                                 if (m == NULL) {
1406                                                         m_freem(top);
1407                                                         ubsecstats.hst_nombuf++;
1408                                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
1409                                                         goto errout;
1410                                                 }
1411                                                 len = MLEN;
1412                                         }
1413                                         if (top && totlen >= MINCLSIZE) {
1414                                                 MCLGET(m, M_DONTWAIT);
1415                                                 if ((m->m_flags & M_EXT) == 0) {
1416                                                         *mp = m;
1417                                                         m_freem(top);
1418                                                         ubsecstats.hst_nomcl++;
1419                                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
1420                                                         goto errout;
1421                                                 }
1422                                                 len = MCLBYTES;
1423                                         }
1424                                         m->m_len = len = min(totlen, len);
1425                                         totlen -= len;
1426                                         *mp = m;
1427                                         mp = &m->m_next;
1428                                 }
1429                                 q->q_dst_m = top;
1430                                 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1431                                     cpskip, cpoffset);
1432                                 if (bus_dmamap_create(sc->sc_dmat,
1433                                     BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1434                                         ubsecstats.hst_nomap++;
1435                                         err = ENOMEM;
1436                                         goto errout;
1437                                 }
1438                                 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1439                                     q->q_dst_map, q->q_dst_m,
1440                                     ubsec_op_cb, &q->q_dst,
1441                                     BUS_DMA_NOWAIT) != 0) {
1442                                         bus_dmamap_destroy(sc->sc_dmat,
1443                                         q->q_dst_map);
1444                                         q->q_dst_map = NULL;
1445                                         ubsecstats.hst_noload++;
1446                                         err = ENOMEM;
1447                                         goto errout;
1448                                 }
1449                         }
1450                 } else {
1451                         ubsecstats.hst_badflags++;
1452                         err = EINVAL;
1453                         goto errout;
1454                 }
1455
1456 #ifdef UBSEC_DEBUG
1457                 if (ubsec_debug)
1458                         printf("dst skip: %d\n", dskip);
1459 #endif
1460                 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1461                         struct ubsec_pktbuf *pb;
1462                         bus_size_t packl = q->q_dst_segs[i].ds_len;
1463                         bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1464
1465                         if (dskip >= packl) {
1466                                 dskip -= packl;
1467                                 continue;
1468                         }
1469
1470                         packl -= dskip;
1471                         packp += dskip;
1472                         dskip = 0;
1473
1474                         if (packl > 0xfffc) {
1475                                 err = EIO;
1476                                 goto errout;
1477                         }
1478
1479                         if (j == 0)
1480                                 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1481                         else
1482                                 pb = &dmap->d_dma->d_dbuf[j - 1];
1483
1484                         pb->pb_addr = htole32(packp);
1485
1486                         if (dtheend) {
1487                                 if (packl > dtheend) {
1488                                         pb->pb_len = htole32(dtheend);
1489                                         dtheend = 0;
1490                                 } else {
1491                                         pb->pb_len = htole32(packl);
1492                                         dtheend -= packl;
1493                                 }
1494                         } else
1495                                 pb->pb_len = htole32(packl);
1496
1497                         if ((i + 1) == q->q_dst_nsegs) {
1498                                 if (maccrd)
1499                                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1500                                             offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1501                                 else
1502                                         pb->pb_next = 0;
1503                         } else
1504                                 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1505                                     offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1506                         j++;
1507                 }
1508         }
1509
1510         dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1511             offsetof(struct ubsec_dmachunk, d_ctx));
1512
1513         if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1514                 struct ubsec_pktctx_long *ctxl;
1515
1516                 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1517                     offsetof(struct ubsec_dmachunk, d_ctx));
1518
1519                 /* transform small context into long context */
1520                 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1521                 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1522                 ctxl->pc_flags = ctx.pc_flags;
1523                 ctxl->pc_offset = ctx.pc_offset;
1524                 for (i = 0; i < 6; i++)
1525                         ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1526                 for (i = 0; i < 5; i++)
1527                         ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1528                 for (i = 0; i < 5; i++)
1529                         ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1530                 ctxl->pc_iv[0] = ctx.pc_iv[0];
1531                 ctxl->pc_iv[1] = ctx.pc_iv[1];
1532         } else
1533                 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1534                     offsetof(struct ubsec_dmachunk, d_ctx),
1535                     sizeof(struct ubsec_pktctx));
1536
1537         mtx_lock(&sc->sc_mcr1lock);
1538         SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1539         sc->sc_nqueue++;
1540         ubsecstats.hst_ipackets++;
1541         ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1542         if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1543                 ubsec_feed(sc);
1544         mtx_unlock(&sc->sc_mcr1lock);
1545         return (0);
1546
1547 errout:
1548         if (q != NULL) {
1549                 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1550                         m_freem(q->q_dst_m);
1551
1552                 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1553                         bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1554                         bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1555                 }
1556                 if (q->q_src_map != NULL) {
1557                         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1558                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1559                 }
1560         }
1561         if (q != NULL || err == ERESTART) {
1562                 mtx_lock(&sc->sc_freeqlock);
1563                 if (q != NULL)
1564                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1565                 if (err == ERESTART)
1566                         sc->sc_needwakeup |= CRYPTO_SYMQ;
1567                 mtx_unlock(&sc->sc_freeqlock);
1568         }
1569         if (err != ERESTART) {
1570                 crp->crp_etype = err;
1571                 crypto_done(crp);
1572         }
1573         return (err);
1574 }
1575
1576 static void
1577 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1578 {
1579         struct cryptop *crp = (struct cryptop *)q->q_crp;
1580         struct cryptodesc *crd;
1581         struct ubsec_dma *dmap = q->q_dma;
1582
1583         ubsecstats.hst_opackets++;
1584         ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1585
1586         ubsec_dma_sync(&dmap->d_alloc,
1587             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1588         if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1589                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1590                     BUS_DMASYNC_POSTREAD);
1591                 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1592                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1593         }
1594         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1595         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1596         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1597
1598         if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1599                 m_freem(q->q_src_m);
1600                 crp->crp_buf = (caddr_t)q->q_dst_m;
1601         }
1602
1603         /* copy out IV for future use */
1604         if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1605                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1606                         if (crd->crd_alg != CRYPTO_DES_CBC &&
1607                             crd->crd_alg != CRYPTO_3DES_CBC)
1608                                 continue;
1609                         crypto_copydata(crp->crp_flags, crp->crp_buf,
1610                             crd->crd_skip + crd->crd_len - 8, 8,
1611                             (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1612                         break;
1613                 }
1614         }
1615
1616         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1617                 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1618                     crd->crd_alg != CRYPTO_SHA1_HMAC)
1619                         continue;
1620                 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1621                     sc->sc_sessions[q->q_sesn].ses_mlen,
1622                     (caddr_t)dmap->d_dma->d_macbuf);
1623                 break;
1624         }
1625         mtx_lock(&sc->sc_freeqlock);
1626         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1627         mtx_unlock(&sc->sc_freeqlock);
1628         crypto_done(crp);
1629 }
1630
1631 static void
1632 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1633 {
1634         int i, j, dlen, slen;
1635         caddr_t dptr, sptr;
1636
1637         j = 0;
1638         sptr = srcm->m_data;
1639         slen = srcm->m_len;
1640         dptr = dstm->m_data;
1641         dlen = dstm->m_len;
1642
1643         while (1) {
1644                 for (i = 0; i < min(slen, dlen); i++) {
1645                         if (j < hoffset || j >= toffset)
1646                                 *dptr++ = *sptr++;
1647                         slen--;
1648                         dlen--;
1649                         j++;
1650                 }
1651                 if (slen == 0) {
1652                         srcm = srcm->m_next;
1653                         if (srcm == NULL)
1654                                 return;
1655                         sptr = srcm->m_data;
1656                         slen = srcm->m_len;
1657                 }
1658                 if (dlen == 0) {
1659                         dstm = dstm->m_next;
1660                         if (dstm == NULL)
1661                                 return;
1662                         dptr = dstm->m_data;
1663                         dlen = dstm->m_len;
1664                 }
1665         }
1666 }
1667
1668 /*
1669  * feed the key generator, must be called at splimp() or higher.
1670  */
1671 static int
1672 ubsec_feed2(struct ubsec_softc *sc)
1673 {
1674         struct ubsec_q2 *q;
1675
1676         while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1677                 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1678                         break;
1679                 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1680
1681                 ubsec_dma_sync(&q->q_mcr,
1682                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1683                 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1684
1685                 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1686                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next);
1687                 --sc->sc_nqueue2;
1688                 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1689         }
1690         return (0);
1691 }
1692
1693 /*
1694  * Callback for handling random numbers
1695  */
1696 static void
1697 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1698 {
1699         struct cryptkop *krp;
1700         struct ubsec_ctx_keyop *ctx;
1701
1702         ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1703         ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1704
1705         switch (q->q_type) {
1706 #ifndef UBSEC_NO_RNG
1707         case UBS_CTXOP_RNGBYPASS: {
1708                 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1709
1710                 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1711                 (*sc->sc_harvest)(sc->sc_rndtest,
1712                         rng->rng_buf.dma_vaddr,
1713                         UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1714                 rng->rng_used = 0;
1715                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1716                 break;
1717         }
1718 #endif
1719         case UBS_CTXOP_MODEXP: {
1720                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1721                 u_int rlen, clen;
1722
1723                 krp = me->me_krp;
1724                 rlen = (me->me_modbits + 7) / 8;
1725                 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1726
1727                 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1728                 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1729                 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1730                 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1731
1732                 if (clen < rlen)
1733                         krp->krp_status = E2BIG;
1734                 else {
1735                         if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1736                                 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1737                                     (krp->krp_param[krp->krp_iparams].crp_nbits
1738                                         + 7) / 8);
1739                                 bcopy(me->me_C.dma_vaddr,
1740                                     krp->krp_param[krp->krp_iparams].crp_p,
1741                                     (me->me_modbits + 7) / 8);
1742                         } else
1743                                 ubsec_kshift_l(me->me_shiftbits,
1744                                     me->me_C.dma_vaddr, me->me_normbits,
1745                                     krp->krp_param[krp->krp_iparams].crp_p,
1746                                     krp->krp_param[krp->krp_iparams].crp_nbits);
1747                 }
1748
1749                 crypto_kdone(krp);
1750
1751                 /* bzero all potentially sensitive data */
1752                 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1753                 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1754                 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1755                 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1756
1757                 /* Can't free here, so put us on the free list. */
1758                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1759                 break;
1760         }
1761         case UBS_CTXOP_RSAPRIV: {
1762                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1763                 u_int len;
1764
1765                 krp = rp->rpr_krp;
1766                 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1767                 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1768
1769                 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1770                 bcopy(rp->rpr_msgout.dma_vaddr,
1771                     krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1772
1773                 crypto_kdone(krp);
1774
1775                 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1776                 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1777                 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1778
1779                 /* Can't free here, so put us on the free list. */
1780                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1781                 break;
1782         }
1783         default:
1784                 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1785                     letoh16(ctx->ctx_op));
1786                 break;
1787         }
1788 }
1789
1790 #ifndef UBSEC_NO_RNG
1791 static void
1792 ubsec_rng(void *vsc)
1793 {
1794         struct ubsec_softc *sc = vsc;
1795         struct ubsec_q2_rng *rng = &sc->sc_rng;
1796         struct ubsec_mcr *mcr;
1797         struct ubsec_ctx_rngbypass *ctx;
1798
1799         mtx_lock(&sc->sc_mcr2lock);
1800         if (rng->rng_used) {
1801                 mtx_unlock(&sc->sc_mcr2lock);
1802                 return;
1803         }
1804         sc->sc_nqueue2++;
1805         if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1806                 goto out;
1807
1808         mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1809         ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1810
1811         mcr->mcr_pkts = htole16(1);
1812         mcr->mcr_flags = 0;
1813         mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1814         mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1815         mcr->mcr_ipktbuf.pb_len = 0;
1816         mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1817         mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1818         mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1819             UBS_PKTBUF_LEN);
1820         mcr->mcr_opktbuf.pb_next = 0;
1821
1822         ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1823         ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1824         rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1825
1826         ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1827
1828         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1829         rng->rng_used = 1;
1830         ubsec_feed2(sc);
1831         ubsecstats.hst_rng++;
1832         mtx_unlock(&sc->sc_mcr2lock);
1833
1834         return;
1835
1836 out:
1837         /*
1838          * Something weird happened, generate our own call back.
1839          */
1840         sc->sc_nqueue2--;
1841         mtx_unlock(&sc->sc_mcr2lock);
1842         callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1843 }
1844 #endif /* UBSEC_NO_RNG */
1845
1846 static void
1847 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1848 {
1849         bus_addr_t *paddr = (bus_addr_t*) arg;
1850         *paddr = segs->ds_addr;
1851 }
1852
1853 static int
1854 ubsec_dma_malloc(
1855         struct ubsec_softc *sc,
1856         bus_size_t size,
1857         struct ubsec_dma_alloc *dma,
1858         int mapflags
1859 )
1860 {
1861         int r;
1862
1863         /* XXX could specify sc_dmat as parent but that just adds overhead */
1864         r = bus_dma_tag_create(NULL,                    /* parent */
1865                                1, 0,                    /* alignment, bounds */
1866                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1867                                BUS_SPACE_MAXADDR,       /* highaddr */
1868                                NULL, NULL,              /* filter, filterarg */
1869                                size,                    /* maxsize */
1870                                1,                       /* nsegments */
1871                                size,                    /* maxsegsize */
1872                                BUS_DMA_ALLOCNOW,        /* flags */
1873                                NULL, NULL,              /* lockfunc, lockarg */
1874                                &dma->dma_tag);
1875         if (r != 0) {
1876                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1877                         "bus_dma_tag_create failed; error %u\n", r);
1878                 goto fail_0;
1879         }
1880
1881         r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1882         if (r != 0) {
1883                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1884                         "bus_dmamap_create failed; error %u\n", r);
1885                 goto fail_1;
1886         }
1887
1888         r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1889                              BUS_DMA_NOWAIT, &dma->dma_map);
1890         if (r != 0) {
1891                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1892                         "bus_dmammem_alloc failed; size %zu, error %u\n",
1893                         size, r);
1894                 goto fail_2;
1895         }
1896
1897         r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1898                             size,
1899                             ubsec_dmamap_cb,
1900                             &dma->dma_paddr,
1901                             mapflags | BUS_DMA_NOWAIT);
1902         if (r != 0) {
1903                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1904                         "bus_dmamap_load failed; error %u\n", r);
1905                 goto fail_3;
1906         }
1907
1908         dma->dma_size = size;
1909         return (0);
1910
1911 fail_3:
1912         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1913 fail_2:
1914         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1915 fail_1:
1916         bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1917         bus_dma_tag_destroy(dma->dma_tag);
1918 fail_0:
1919         dma->dma_map = NULL;
1920         dma->dma_tag = NULL;
1921         return (r);
1922 }
1923
1924 static void
1925 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1926 {
1927         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1928         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1929         bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1930         bus_dma_tag_destroy(dma->dma_tag);
1931 }
1932
1933 /*
1934  * Resets the board.  Values in the regesters are left as is
1935  * from the reset (i.e. initial values are assigned elsewhere).
1936  */
1937 static void
1938 ubsec_reset_board(struct ubsec_softc *sc)
1939 {
1940     volatile u_int32_t ctrl;
1941
1942     ctrl = READ_REG(sc, BS_CTRL);
1943     ctrl |= BS_CTRL_RESET;
1944     WRITE_REG(sc, BS_CTRL, ctrl);
1945
1946     /*
1947      * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1948      */
1949     DELAY(10);
1950 }
1951
1952 /*
1953  * Init Broadcom registers
1954  */
1955 static void
1956 ubsec_init_board(struct ubsec_softc *sc)
1957 {
1958         u_int32_t ctrl;
1959
1960         ctrl = READ_REG(sc, BS_CTRL);
1961         ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1962         ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1963
1964         if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1965                 ctrl |= BS_CTRL_MCR2INT;
1966         else
1967                 ctrl &= ~BS_CTRL_MCR2INT;
1968
1969         if (sc->sc_flags & UBS_FLAGS_HWNORM)
1970                 ctrl &= ~BS_CTRL_SWNORM;
1971
1972         WRITE_REG(sc, BS_CTRL, ctrl);
1973 }
1974
1975 /*
1976  * Init Broadcom PCI registers
1977  */
1978 static void
1979 ubsec_init_pciregs(device_t dev)
1980 {
1981 #if 0
1982         u_int32_t misc;
1983
1984         misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1985         misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1986             | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1987         misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1988             | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1989         pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1990 #endif
1991
1992         /*
1993          * This will set the cache line size to 1, this will
1994          * force the BCM58xx chip just to do burst read/writes.
1995          * Cache line read/writes are to slow
1996          */
1997         pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1998 }
1999
2000 /*
2001  * Clean up after a chip crash.
2002  * It is assumed that the caller in splimp()
2003  */
2004 static void
2005 ubsec_cleanchip(struct ubsec_softc *sc)
2006 {
2007         struct ubsec_q *q;
2008
2009         while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2010                 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2011                 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
2012                 ubsec_free_q(sc, q);
2013         }
2014         sc->sc_nqchip = 0;
2015 }
2016
2017 /*
2018  * free a ubsec_q
2019  * It is assumed that the caller is within splimp().
2020  */
2021 static int
2022 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2023 {
2024         struct ubsec_q *q2;
2025         struct cryptop *crp;
2026         int npkts;
2027         int i;
2028
2029         npkts = q->q_nstacked_mcrs;
2030
2031         for (i = 0; i < npkts; i++) {
2032                 if(q->q_stacked_mcr[i]) {
2033                         q2 = q->q_stacked_mcr[i];
2034
2035                         if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2036                                 m_freem(q2->q_dst_m);
2037
2038                         crp = (struct cryptop *)q2->q_crp;
2039
2040                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2041
2042                         crp->crp_etype = EFAULT;
2043                         crypto_done(crp);
2044                 } else {
2045                         break;
2046                 }
2047         }
2048
2049         /*
2050          * Free header MCR
2051          */
2052         if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2053                 m_freem(q->q_dst_m);
2054
2055         crp = (struct cryptop *)q->q_crp;
2056
2057         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2058
2059         crp->crp_etype = EFAULT;
2060         crypto_done(crp);
2061         return(0);
2062 }
2063
2064 /*
2065  * Routine to reset the chip and clean up.
2066  * It is assumed that the caller is in splimp()
2067  */
2068 static void
2069 ubsec_totalreset(struct ubsec_softc *sc)
2070 {
2071         ubsec_reset_board(sc);
2072         ubsec_init_board(sc);
2073         ubsec_cleanchip(sc);
2074 }
2075
2076 static int
2077 ubsec_dmamap_aligned(struct ubsec_operand *op)
2078 {
2079         int i;
2080
2081         for (i = 0; i < op->nsegs; i++) {
2082                 if (op->segs[i].ds_addr & 3)
2083                         return (0);
2084                 if ((i != (op->nsegs - 1)) &&
2085                     (op->segs[i].ds_len & 3))
2086                         return (0);
2087         }
2088         return (1);
2089 }
2090
2091 static void
2092 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2093 {
2094         switch (q->q_type) {
2095         case UBS_CTXOP_MODEXP: {
2096                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2097
2098                 ubsec_dma_free(sc, &me->me_q.q_mcr);
2099                 ubsec_dma_free(sc, &me->me_q.q_ctx);
2100                 ubsec_dma_free(sc, &me->me_M);
2101                 ubsec_dma_free(sc, &me->me_E);
2102                 ubsec_dma_free(sc, &me->me_C);
2103                 ubsec_dma_free(sc, &me->me_epb);
2104                 free(me, M_DEVBUF);
2105                 break;
2106         }
2107         case UBS_CTXOP_RSAPRIV: {
2108                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2109
2110                 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2111                 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2112                 ubsec_dma_free(sc, &rp->rpr_msgin);
2113                 ubsec_dma_free(sc, &rp->rpr_msgout);
2114                 free(rp, M_DEVBUF);
2115                 break;
2116         }
2117         default:
2118                 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2119                 break;
2120         }
2121 }
2122
2123 static int
2124 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2125 {
2126         struct ubsec_softc *sc = arg;
2127         int r;
2128
2129         if (krp == NULL || krp->krp_callback == NULL)
2130                 return (EINVAL);
2131
2132         while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2133                 struct ubsec_q2 *q;
2134
2135                 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2136                 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next);
2137                 ubsec_kfree(sc, q);
2138         }
2139
2140         switch (krp->krp_op) {
2141         case CRK_MOD_EXP:
2142                 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2143                         r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2144                 else
2145                         r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2146                 break;
2147         case CRK_MOD_EXP_CRT:
2148                 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2149         default:
2150                 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2151                     krp->krp_op);
2152                 krp->krp_status = EOPNOTSUPP;
2153                 crypto_kdone(krp);
2154                 return (0);
2155         }
2156         return (0);                     /* silence compiler */
2157 }
2158
2159 /*
2160  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2161  */
2162 static int
2163 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2164 {
2165         struct ubsec_q2_modexp *me;
2166         struct ubsec_mcr *mcr;
2167         struct ubsec_ctx_modexp *ctx;
2168         struct ubsec_pktbuf *epb;
2169         int err = 0;
2170         u_int nbits, normbits, mbits, shiftbits, ebits;
2171
2172         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2173         if (me == NULL) {
2174                 err = ENOMEM;
2175                 goto errout;
2176         }
2177         bzero(me, sizeof *me);
2178         me->me_krp = krp;
2179         me->me_q.q_type = UBS_CTXOP_MODEXP;
2180
2181         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2182         if (nbits <= 512)
2183                 normbits = 512;
2184         else if (nbits <= 768)
2185                 normbits = 768;
2186         else if (nbits <= 1024)
2187                 normbits = 1024;
2188         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2189                 normbits = 1536;
2190         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2191                 normbits = 2048;
2192         else {
2193                 err = E2BIG;
2194                 goto errout;
2195         }
2196
2197         shiftbits = normbits - nbits;
2198
2199         me->me_modbits = nbits;
2200         me->me_shiftbits = shiftbits;
2201         me->me_normbits = normbits;
2202
2203         /* Sanity check: result bits must be >= true modulus bits. */
2204         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2205                 err = ERANGE;
2206                 goto errout;
2207         }
2208
2209         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2210             &me->me_q.q_mcr, 0)) {
2211                 err = ENOMEM;
2212                 goto errout;
2213         }
2214         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2215
2216         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2217             &me->me_q.q_ctx, 0)) {
2218                 err = ENOMEM;
2219                 goto errout;
2220         }
2221
2222         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2223         if (mbits > nbits) {
2224                 err = E2BIG;
2225                 goto errout;
2226         }
2227         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2228                 err = ENOMEM;
2229                 goto errout;
2230         }
2231         ubsec_kshift_r(shiftbits,
2232             krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2233             me->me_M.dma_vaddr, normbits);
2234
2235         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2236                 err = ENOMEM;
2237                 goto errout;
2238         }
2239         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2240
2241         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2242         if (ebits > nbits) {
2243                 err = E2BIG;
2244                 goto errout;
2245         }
2246         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2247                 err = ENOMEM;
2248                 goto errout;
2249         }
2250         ubsec_kshift_r(shiftbits,
2251             krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2252             me->me_E.dma_vaddr, normbits);
2253
2254         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2255             &me->me_epb, 0)) {
2256                 err = ENOMEM;
2257                 goto errout;
2258         }
2259         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2260         epb->pb_addr = htole32(me->me_E.dma_paddr);
2261         epb->pb_next = 0;
2262         epb->pb_len = htole32(normbits / 8);
2263
2264 #ifdef UBSEC_DEBUG
2265         if (ubsec_debug) {
2266                 printf("Epb ");
2267                 ubsec_dump_pb(epb);
2268         }
2269 #endif
2270
2271         mcr->mcr_pkts = htole16(1);
2272         mcr->mcr_flags = 0;
2273         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2274         mcr->mcr_reserved = 0;
2275         mcr->mcr_pktlen = 0;
2276
2277         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2278         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2279         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2280
2281         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2282         mcr->mcr_opktbuf.pb_next = 0;
2283         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2284
2285 #ifdef DIAGNOSTIC
2286         /* Misaligned output buffer will hang the chip. */
2287         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2288                 panic("%s: modexp invalid addr 0x%x\n",
2289                     device_get_nameunit(sc->sc_dev),
2290                     letoh32(mcr->mcr_opktbuf.pb_addr));
2291         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2292                 panic("%s: modexp invalid len 0x%x\n",
2293                     device_get_nameunit(sc->sc_dev),
2294                     letoh32(mcr->mcr_opktbuf.pb_len));
2295 #endif
2296
2297         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2298         bzero(ctx, sizeof(*ctx));
2299         ubsec_kshift_r(shiftbits,
2300             krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2301             ctx->me_N, normbits);
2302         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2303         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2304         ctx->me_E_len = htole16(nbits);
2305         ctx->me_N_len = htole16(nbits);
2306
2307 #ifdef UBSEC_DEBUG
2308         if (ubsec_debug) {
2309                 ubsec_dump_mcr(mcr);
2310                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2311         }
2312 #endif
2313
2314         /*
2315          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2316          * everything else.
2317          */
2318         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2319         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2320         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2321         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2322
2323         /* Enqueue and we're done... */
2324         mtx_lock(&sc->sc_mcr2lock);
2325         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2326         ubsec_feed2(sc);
2327         ubsecstats.hst_modexp++;
2328         mtx_unlock(&sc->sc_mcr2lock);
2329
2330         return (0);
2331
2332 errout:
2333         if (me != NULL) {
2334                 if (me->me_q.q_mcr.dma_map != NULL)
2335                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2336                 if (me->me_q.q_ctx.dma_map != NULL) {
2337                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2338                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2339                 }
2340                 if (me->me_M.dma_map != NULL) {
2341                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2342                         ubsec_dma_free(sc, &me->me_M);
2343                 }
2344                 if (me->me_E.dma_map != NULL) {
2345                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2346                         ubsec_dma_free(sc, &me->me_E);
2347                 }
2348                 if (me->me_C.dma_map != NULL) {
2349                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2350                         ubsec_dma_free(sc, &me->me_C);
2351                 }
2352                 if (me->me_epb.dma_map != NULL)
2353                         ubsec_dma_free(sc, &me->me_epb);
2354                 free(me, M_DEVBUF);
2355         }
2356         krp->krp_status = err;
2357         crypto_kdone(krp);
2358         return (0);
2359 }
2360
2361 /*
2362  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2363  */
2364 static int
2365 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2366 {
2367         struct ubsec_q2_modexp *me;
2368         struct ubsec_mcr *mcr;
2369         struct ubsec_ctx_modexp *ctx;
2370         struct ubsec_pktbuf *epb;
2371         int err = 0;
2372         u_int nbits, normbits, mbits, shiftbits, ebits;
2373
2374         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2375         if (me == NULL) {
2376                 err = ENOMEM;
2377                 goto errout;
2378         }
2379         bzero(me, sizeof *me);
2380         me->me_krp = krp;
2381         me->me_q.q_type = UBS_CTXOP_MODEXP;
2382
2383         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2384         if (nbits <= 512)
2385                 normbits = 512;
2386         else if (nbits <= 768)
2387                 normbits = 768;
2388         else if (nbits <= 1024)
2389                 normbits = 1024;
2390         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2391                 normbits = 1536;
2392         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2393                 normbits = 2048;
2394         else {
2395                 err = E2BIG;
2396                 goto errout;
2397         }
2398
2399         shiftbits = normbits - nbits;
2400
2401         /* XXX ??? */
2402         me->me_modbits = nbits;
2403         me->me_shiftbits = shiftbits;
2404         me->me_normbits = normbits;
2405
2406         /* Sanity check: result bits must be >= true modulus bits. */
2407         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2408                 err = ERANGE;
2409                 goto errout;
2410         }
2411
2412         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2413             &me->me_q.q_mcr, 0)) {
2414                 err = ENOMEM;
2415                 goto errout;
2416         }
2417         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2418
2419         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2420             &me->me_q.q_ctx, 0)) {
2421                 err = ENOMEM;
2422                 goto errout;
2423         }
2424
2425         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2426         if (mbits > nbits) {
2427                 err = E2BIG;
2428                 goto errout;
2429         }
2430         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2431                 err = ENOMEM;
2432                 goto errout;
2433         }
2434         bzero(me->me_M.dma_vaddr, normbits / 8);
2435         bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2436             me->me_M.dma_vaddr, (mbits + 7) / 8);
2437
2438         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2439                 err = ENOMEM;
2440                 goto errout;
2441         }
2442         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2443
2444         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2445         if (ebits > nbits) {
2446                 err = E2BIG;
2447                 goto errout;
2448         }
2449         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2450                 err = ENOMEM;
2451                 goto errout;
2452         }
2453         bzero(me->me_E.dma_vaddr, normbits / 8);
2454         bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2455             me->me_E.dma_vaddr, (ebits + 7) / 8);
2456
2457         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2458             &me->me_epb, 0)) {
2459                 err = ENOMEM;
2460                 goto errout;
2461         }
2462         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2463         epb->pb_addr = htole32(me->me_E.dma_paddr);
2464         epb->pb_next = 0;
2465         epb->pb_len = htole32((ebits + 7) / 8);
2466
2467 #ifdef UBSEC_DEBUG
2468         if (ubsec_debug) {
2469                 printf("Epb ");
2470                 ubsec_dump_pb(epb);
2471         }
2472 #endif
2473
2474         mcr->mcr_pkts = htole16(1);
2475         mcr->mcr_flags = 0;
2476         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2477         mcr->mcr_reserved = 0;
2478         mcr->mcr_pktlen = 0;
2479
2480         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2481         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2482         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2483
2484         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2485         mcr->mcr_opktbuf.pb_next = 0;
2486         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2487
2488 #ifdef DIAGNOSTIC
2489         /* Misaligned output buffer will hang the chip. */
2490         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2491                 panic("%s: modexp invalid addr 0x%x\n",
2492                     device_get_nameunit(sc->sc_dev),
2493                     letoh32(mcr->mcr_opktbuf.pb_addr));
2494         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2495                 panic("%s: modexp invalid len 0x%x\n",
2496                     device_get_nameunit(sc->sc_dev),
2497                     letoh32(mcr->mcr_opktbuf.pb_len));
2498 #endif
2499
2500         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2501         bzero(ctx, sizeof(*ctx));
2502         bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2503             (nbits + 7) / 8);
2504         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2505         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2506         ctx->me_E_len = htole16(ebits);
2507         ctx->me_N_len = htole16(nbits);
2508
2509 #ifdef UBSEC_DEBUG
2510         if (ubsec_debug) {
2511                 ubsec_dump_mcr(mcr);
2512                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2513         }
2514 #endif
2515
2516         /*
2517          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2518          * everything else.
2519          */
2520         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2521         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2522         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2523         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2524
2525         /* Enqueue and we're done... */
2526         mtx_lock(&sc->sc_mcr2lock);
2527         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2528         ubsec_feed2(sc);
2529         mtx_unlock(&sc->sc_mcr2lock);
2530
2531         return (0);
2532
2533 errout:
2534         if (me != NULL) {
2535                 if (me->me_q.q_mcr.dma_map != NULL)
2536                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2537                 if (me->me_q.q_ctx.dma_map != NULL) {
2538                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2539                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2540                 }
2541                 if (me->me_M.dma_map != NULL) {
2542                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2543                         ubsec_dma_free(sc, &me->me_M);
2544                 }
2545                 if (me->me_E.dma_map != NULL) {
2546                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2547                         ubsec_dma_free(sc, &me->me_E);
2548                 }
2549                 if (me->me_C.dma_map != NULL) {
2550                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2551                         ubsec_dma_free(sc, &me->me_C);
2552                 }
2553                 if (me->me_epb.dma_map != NULL)
2554                         ubsec_dma_free(sc, &me->me_epb);
2555                 free(me, M_DEVBUF);
2556         }
2557         krp->krp_status = err;
2558         crypto_kdone(krp);
2559         return (0);
2560 }
2561
2562 static int
2563 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2564 {
2565         struct ubsec_q2_rsapriv *rp = NULL;
2566         struct ubsec_mcr *mcr;
2567         struct ubsec_ctx_rsapriv *ctx;
2568         int err = 0;
2569         u_int padlen, msglen;
2570
2571         msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2572         padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2573         if (msglen > padlen)
2574                 padlen = msglen;
2575
2576         if (padlen <= 256)
2577                 padlen = 256;
2578         else if (padlen <= 384)
2579                 padlen = 384;
2580         else if (padlen <= 512)
2581                 padlen = 512;
2582         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2583                 padlen = 768;
2584         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2585                 padlen = 1024;
2586         else {
2587                 err = E2BIG;
2588                 goto errout;
2589         }
2590
2591         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2592                 err = E2BIG;
2593                 goto errout;
2594         }
2595
2596         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2597                 err = E2BIG;
2598                 goto errout;
2599         }
2600
2601         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2602                 err = E2BIG;
2603                 goto errout;
2604         }
2605
2606         rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2607         if (rp == NULL)
2608                 return (ENOMEM);
2609         bzero(rp, sizeof *rp);
2610         rp->rpr_krp = krp;
2611         rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2612
2613         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2614             &rp->rpr_q.q_mcr, 0)) {
2615                 err = ENOMEM;
2616                 goto errout;
2617         }
2618         mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2619
2620         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2621             &rp->rpr_q.q_ctx, 0)) {
2622                 err = ENOMEM;
2623                 goto errout;
2624         }
2625         ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2626         bzero(ctx, sizeof *ctx);
2627
2628         /* Copy in p */
2629         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2630             &ctx->rpr_buf[0 * (padlen / 8)],
2631             (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2632
2633         /* Copy in q */
2634         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2635             &ctx->rpr_buf[1 * (padlen / 8)],
2636             (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2637
2638         /* Copy in dp */
2639         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2640             &ctx->rpr_buf[2 * (padlen / 8)],
2641             (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2642
2643         /* Copy in dq */
2644         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2645             &ctx->rpr_buf[3 * (padlen / 8)],
2646             (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2647
2648         /* Copy in pinv */
2649         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2650             &ctx->rpr_buf[4 * (padlen / 8)],
2651             (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2652
2653         msglen = padlen * 2;
2654
2655         /* Copy in input message (aligned buffer/length). */
2656         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2657                 /* Is this likely? */
2658                 err = E2BIG;
2659                 goto errout;
2660         }
2661         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2662                 err = ENOMEM;
2663                 goto errout;
2664         }
2665         bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2666         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2667             rp->rpr_msgin.dma_vaddr,
2668             (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2669
2670         /* Prepare space for output message (aligned buffer/length). */
2671         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2672                 /* Is this likely? */
2673                 err = E2BIG;
2674                 goto errout;
2675         }
2676         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2677                 err = ENOMEM;
2678                 goto errout;
2679         }
2680         bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2681
2682         mcr->mcr_pkts = htole16(1);
2683         mcr->mcr_flags = 0;
2684         mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2685         mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2686         mcr->mcr_ipktbuf.pb_next = 0;
2687         mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2688         mcr->mcr_reserved = 0;
2689         mcr->mcr_pktlen = htole16(msglen);
2690         mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2691         mcr->mcr_opktbuf.pb_next = 0;
2692         mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2693
2694 #ifdef DIAGNOSTIC
2695         if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2696                 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2697                     device_get_nameunit(sc->sc_dev),
2698                     rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2699         }
2700         if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2701                 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2702                     device_get_nameunit(sc->sc_dev),
2703                     rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2704         }
2705 #endif
2706
2707         ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2708         ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2709         ctx->rpr_q_len = htole16(padlen);
2710         ctx->rpr_p_len = htole16(padlen);
2711
2712         /*
2713          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2714          * everything else.
2715          */
2716         ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2717         ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2718
2719         /* Enqueue and we're done... */
2720         mtx_lock(&sc->sc_mcr2lock);
2721         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2722         ubsec_feed2(sc);
2723         ubsecstats.hst_modexpcrt++;
2724         mtx_unlock(&sc->sc_mcr2lock);
2725         return (0);
2726
2727 errout:
2728         if (rp != NULL) {
2729                 if (rp->rpr_q.q_mcr.dma_map != NULL)
2730                         ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2731                 if (rp->rpr_msgin.dma_map != NULL) {
2732                         bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2733                         ubsec_dma_free(sc, &rp->rpr_msgin);
2734                 }
2735                 if (rp->rpr_msgout.dma_map != NULL) {
2736                         bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2737                         ubsec_dma_free(sc, &rp->rpr_msgout);
2738                 }
2739                 free(rp, M_DEVBUF);
2740         }
2741         krp->krp_status = err;
2742         crypto_kdone(krp);
2743         return (0);
2744 }
2745
2746 #ifdef UBSEC_DEBUG
2747 static void
2748 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2749 {
2750         printf("addr 0x%x (0x%x) next 0x%x\n",
2751             pb->pb_addr, pb->pb_len, pb->pb_next);
2752 }
2753
2754 static void
2755 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2756 {
2757         printf("CTX (0x%x):\n", c->ctx_len);
2758         switch (letoh16(c->ctx_op)) {
2759         case UBS_CTXOP_RNGBYPASS:
2760         case UBS_CTXOP_RNGSHA1:
2761                 break;
2762         case UBS_CTXOP_MODEXP:
2763         {
2764                 struct ubsec_ctx_modexp *cx = (void *)c;
2765                 int i, len;
2766
2767                 printf(" Elen %u, Nlen %u\n",
2768                     letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2769                 len = (cx->me_N_len + 7)/8;
2770                 for (i = 0; i < len; i++)
2771                         printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2772                 printf("\n");
2773                 break;
2774         }
2775         default:
2776                 printf("unknown context: %x\n", c->ctx_op);
2777         }
2778         printf("END CTX\n");
2779 }
2780
2781 static void
2782 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2783 {
2784         volatile struct ubsec_mcr_add *ma;
2785         int i;
2786
2787         printf("MCR:\n");
2788         printf(" pkts: %u, flags 0x%x\n",
2789             letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2790         ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2791         for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2792                 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2793                     letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2794                     letoh16(ma->mcr_reserved));
2795                 printf(" %d: ipkt ", i);
2796                 ubsec_dump_pb(&ma->mcr_ipktbuf);
2797                 printf(" %d: opkt ", i);
2798                 ubsec_dump_pb(&ma->mcr_opktbuf);
2799                 ma++;
2800         }
2801         printf("END MCR\n");
2802 }
2803 #endif /* UBSEC_DEBUG */
2804
2805 /*
2806  * Return the number of significant bits of a big number.
2807  */
2808 static int
2809 ubsec_ksigbits(struct crparam *cr)
2810 {
2811         u_int plen = (cr->crp_nbits + 7) / 8;
2812         int i, sig = plen * 8;
2813         u_int8_t c, *p = cr->crp_p;
2814
2815         for (i = plen - 1; i >= 0; i--) {
2816                 c = p[i];
2817                 if (c != 0) {
2818                         while ((c & 0x80) == 0) {
2819                                 sig--;
2820                                 c <<= 1;
2821                         }
2822                         break;
2823                 }
2824                 sig -= 8;
2825         }
2826         return (sig);
2827 }
2828
2829 static void
2830 ubsec_kshift_r(
2831         u_int shiftbits,
2832         u_int8_t *src, u_int srcbits,
2833         u_int8_t *dst, u_int dstbits)
2834 {
2835         u_int slen, dlen;
2836         int i, si, di, n;
2837
2838         slen = (srcbits + 7) / 8;
2839         dlen = (dstbits + 7) / 8;
2840
2841         for (i = 0; i < slen; i++)
2842                 dst[i] = src[i];
2843         for (i = 0; i < dlen - slen; i++)
2844                 dst[slen + i] = 0;
2845
2846         n = shiftbits / 8;
2847         if (n != 0) {
2848                 si = dlen - n - 1;
2849                 di = dlen - 1;
2850                 while (si >= 0)
2851                         dst[di--] = dst[si--];
2852                 while (di >= 0)
2853                         dst[di--] = 0;
2854         }
2855
2856         n = shiftbits % 8;
2857         if (n != 0) {
2858                 for (i = dlen - 1; i > 0; i--)
2859                         dst[i] = (dst[i] << n) |
2860                             (dst[i - 1] >> (8 - n));
2861                 dst[0] = dst[0] << n;
2862         }
2863 }
2864
2865 static void
2866 ubsec_kshift_l(
2867         u_int shiftbits,
2868         u_int8_t *src, u_int srcbits,
2869         u_int8_t *dst, u_int dstbits)
2870 {
2871         int slen, dlen, i, n;
2872
2873         slen = (srcbits + 7) / 8;
2874         dlen = (dstbits + 7) / 8;
2875
2876         n = shiftbits / 8;
2877         for (i = 0; i < slen; i++)
2878                 dst[i] = src[i + n];
2879         for (i = 0; i < dlen - slen; i++)
2880                 dst[slen + i] = 0;
2881
2882         n = shiftbits % 8;
2883         if (n != 0) {
2884                 for (i = 0; i < (dlen - 1); i++)
2885                         dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2886                 dst[dlen - 1] = dst[dlen - 1] >> n;
2887         }
2888 }