1 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Jason L. Wright
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
36 * Effort sponsored in part by the Defense Advanced Research Projects
37 * Agency (DARPA) and Air Force Research Laboratory, Air Force
38 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 * uBsec 5[56]01, 58xx hardware crypto accelerator
48 #include "opt_ubsec.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/sysctl.h>
61 #include <sys/endian.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
71 #include <crypto/sha1.h>
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/cryptosoft.h>
75 #include <sys/random.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcireg.h>
80 /* grr, #defines for gratuitous incompatibility in queue.h */
81 #define SIMPLEQ_HEAD STAILQ_HEAD
82 #define SIMPLEQ_ENTRY STAILQ_ENTRY
83 #define SIMPLEQ_INIT STAILQ_INIT
84 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
85 #define SIMPLEQ_EMPTY STAILQ_EMPTY
86 #define SIMPLEQ_FIRST STAILQ_FIRST
87 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL
88 #define SIMPLEQ_FOREACH STAILQ_FOREACH
89 /* ditto for endian.h */
90 #define letoh16(x) le16toh(x)
91 #define letoh32(x) le32toh(x)
94 #include <dev/rndtest/rndtest.h>
96 #include <dev/ubsec/ubsecreg.h>
97 #include <dev/ubsec/ubsecvar.h>
100 * Prototypes and count for the pci_device structure
102 static int ubsec_probe(device_t);
103 static int ubsec_attach(device_t);
104 static int ubsec_detach(device_t);
105 static int ubsec_suspend(device_t);
106 static int ubsec_resume(device_t);
107 static void ubsec_shutdown(device_t);
109 static device_method_t ubsec_methods[] = {
110 /* Device interface */
111 DEVMETHOD(device_probe, ubsec_probe),
112 DEVMETHOD(device_attach, ubsec_attach),
113 DEVMETHOD(device_detach, ubsec_detach),
114 DEVMETHOD(device_suspend, ubsec_suspend),
115 DEVMETHOD(device_resume, ubsec_resume),
116 DEVMETHOD(device_shutdown, ubsec_shutdown),
119 DEVMETHOD(bus_print_child, bus_generic_print_child),
120 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
124 static driver_t ubsec_driver = {
127 sizeof (struct ubsec_softc)
129 static devclass_t ubsec_devclass;
131 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
132 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
134 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
137 static void ubsec_intr(void *);
138 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
139 static int ubsec_freesession(void *, u_int64_t);
140 static int ubsec_process(void *, struct cryptop *, int);
141 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
142 static void ubsec_feed(struct ubsec_softc *);
143 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
144 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
145 static int ubsec_feed2(struct ubsec_softc *);
146 static void ubsec_rng(void *);
147 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
148 struct ubsec_dma_alloc *, int);
149 #define ubsec_dma_sync(_dma, _flags) \
150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
151 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
152 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
154 static void ubsec_reset_board(struct ubsec_softc *sc);
155 static void ubsec_init_board(struct ubsec_softc *sc);
156 static void ubsec_init_pciregs(device_t dev);
157 static void ubsec_totalreset(struct ubsec_softc *sc);
159 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
161 static int ubsec_kprocess(void*, struct cryptkop *, int);
162 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
163 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
164 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
165 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
166 static int ubsec_ksigbits(struct crparam *);
167 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
168 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
170 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
173 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
174 static void ubsec_dump_mcr(struct ubsec_mcr *);
175 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
177 static int ubsec_debug = 0;
178 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
179 0, "control debugging msgs");
182 #define READ_REG(sc,r) \
183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
185 #define WRITE_REG(sc,reg,val) \
186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
188 #define SWAP32(x) (x) = htole32(ntohl((x)))
189 #define HTOLE32(x) (x) = htole32(x)
191 struct ubsec_stats ubsecstats;
192 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
193 ubsec_stats, "driver statistics");
196 ubsec_probe(device_t dev)
198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
201 return (BUS_PROBE_DEFAULT);
202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
205 return (BUS_PROBE_DEFAULT);
206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
215 return (BUS_PROBE_DEFAULT);
220 ubsec_partname(struct ubsec_softc *sc)
222 /* XXX sprintf numbers when not decoded */
223 switch (pci_get_vendor(sc->sc_dev)) {
224 case PCI_VENDOR_BROADCOM:
225 switch (pci_get_device(sc->sc_dev)) {
226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
234 return "Broadcom unknown-part";
235 case PCI_VENDOR_BLUESTEEL:
236 switch (pci_get_device(sc->sc_dev)) {
237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
239 return "Bluesteel unknown-part";
241 switch (pci_get_device(sc->sc_dev)) {
242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
245 return "Sun unknown-part";
247 return "Unknown-vendor unknown-part";
251 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE);
257 ubsec_attach(device_t dev)
259 struct ubsec_softc *sc = device_get_softc(dev);
260 struct ubsec_dma *dmap;
264 bzero(sc, sizeof (*sc));
267 SIMPLEQ_INIT(&sc->sc_queue);
268 SIMPLEQ_INIT(&sc->sc_qchip);
269 SIMPLEQ_INIT(&sc->sc_queue2);
270 SIMPLEQ_INIT(&sc->sc_qchip2);
271 SIMPLEQ_INIT(&sc->sc_q2free);
273 /* XXX handle power management */
275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
295 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
298 /* NB: the 5821/5822 defines some additional status bits */
299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
300 BS_STAT_MCR2_ALLEMPTY;
301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
305 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
307 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
308 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
310 if (!(cmd & PCIM_CMD_MEMEN)) {
311 device_printf(dev, "failed to enable memory mapping\n");
315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
316 device_printf(dev, "failed to enable bus mastering\n");
321 * Setup memory-mapping of PCI registers.
324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
326 if (sc->sc_sr == NULL) {
327 device_printf(dev, "cannot map register space\n");
330 sc->sc_st = rman_get_bustag(sc->sc_sr);
331 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
334 * Arrange interrupt line.
337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
338 RF_SHAREABLE|RF_ACTIVE);
339 if (sc->sc_irq == NULL) {
340 device_printf(dev, "could not map interrupt\n");
344 * NB: Network code assumes we are blocked with splimp()
345 * so make sure the IRQ is mapped appropriately.
347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
348 ubsec_intr, sc, &sc->sc_ih)) {
349 device_printf(dev, "could not establish interrupt\n");
353 sc->sc_cid = crypto_get_driverid(0);
354 if (sc->sc_cid < 0) {
355 device_printf(dev, "could not get crypto driver id\n");
360 * Setup DMA descriptor area.
362 if (bus_dma_tag_create(NULL, /* parent */
363 1, 0, /* alignment, bounds */
364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
365 BUS_SPACE_MAXADDR, /* highaddr */
366 NULL, NULL, /* filter, filterarg */
367 0x3ffff, /* maxsize */
368 UBS_MAX_SCATTER, /* nsegments */
369 0xffff, /* maxsegsize */
370 BUS_DMA_ALLOCNOW, /* flags */
371 NULL, NULL, /* lockfunc, lockarg */
373 device_printf(dev, "cannot allocate DMA tag\n");
376 SIMPLEQ_INIT(&sc->sc_freequeue);
378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
384 device_printf(dev, "cannot allocate queue buffers\n");
388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
389 &dmap->d_alloc, 0)) {
390 device_printf(dev, "cannot allocate dma buffers\n");
394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
397 sc->sc_queuea[i] = q;
399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
402 "mcr1 operations", MTX_DEF);
403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
404 "mcr1 free q", MTX_DEF);
406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
409 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
411 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
413 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
415 ubsec_newsession, ubsec_freesession, ubsec_process, sc);
418 * Reset Broadcom chip
420 ubsec_reset_board(sc);
423 * Init Broadcom specific PCI settings
425 ubsec_init_pciregs(dev);
430 ubsec_init_board(sc);
433 if (sc->sc_flags & UBS_FLAGS_RNG) {
434 sc->sc_statmask |= BS_STAT_MCR2_DONE;
436 sc->sc_rndtest = rndtest_attach(dev);
438 sc->sc_harvest = rndtest_harvest;
440 sc->sc_harvest = default_harvest;
442 sc->sc_harvest = default_harvest;
445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
446 &sc->sc_rng.rng_q.q_mcr, 0))
449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
450 &sc->sc_rng.rng_q.q_ctx, 0)) {
451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
463 sc->sc_rnghz = hz / 100;
466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
471 #endif /* UBSEC_NO_RNG */
472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
473 "mcr2 operations", MTX_DEF);
475 if (sc->sc_flags & UBS_FLAGS_KEY) {
476 sc->sc_statmask |= BS_STAT_MCR2_DONE;
478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0,
481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0,
487 crypto_unregister_all(sc->sc_cid);
489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
499 * Detach a device that successfully probed.
502 ubsec_detach(device_t dev)
504 struct ubsec_softc *sc = device_get_softc(dev);
506 /* XXX wait/abort active ops */
508 /* disable interrupts */
509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
512 callout_stop(&sc->sc_rngto);
514 crypto_unregister_all(sc->sc_cid);
518 rndtest_detach(sc->sc_rndtest);
521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
524 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
526 ubsec_dma_free(sc, &q->q_dma->d_alloc);
529 mtx_destroy(&sc->sc_mcr1lock);
530 mtx_destroy(&sc->sc_freeqlock);
532 if (sc->sc_flags & UBS_FLAGS_RNG) {
533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
537 #endif /* UBSEC_NO_RNG */
538 mtx_destroy(&sc->sc_mcr2lock);
540 bus_generic_detach(dev);
541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
544 bus_dma_tag_destroy(sc->sc_dmat);
545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
551 * Stop all chip i/o so that the kernel's probe routines don't
552 * get confused by errant DMAs when rebooting.
555 ubsec_shutdown(device_t dev)
558 ubsec_stop(device_get_softc(dev));
563 * Device suspend routine.
566 ubsec_suspend(device_t dev)
568 struct ubsec_softc *sc = device_get_softc(dev);
571 /* XXX stop the device and save PCI settings */
573 sc->sc_suspended = 1;
579 ubsec_resume(device_t dev)
581 struct ubsec_softc *sc = device_get_softc(dev);
584 /* XXX retore PCI settings and start the device */
586 sc->sc_suspended = 0;
591 * UBSEC Interrupt routine
594 ubsec_intr(void *arg)
596 struct ubsec_softc *sc = arg;
597 volatile u_int32_t stat;
599 struct ubsec_dma *dmap;
602 stat = READ_REG(sc, BS_STAT);
603 stat &= sc->sc_statmask;
607 WRITE_REG(sc, BS_STAT, stat); /* IACK */
610 * Check to see if we have any packets waiting for us
612 if ((stat & BS_STAT_MCR1_DONE)) {
613 mtx_lock(&sc->sc_mcr1lock);
614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
615 q = SIMPLEQ_FIRST(&sc->sc_qchip);
618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
623 npkts = q->q_nstacked_mcrs;
624 sc->sc_nqchip -= 1+npkts;
626 * search for further sc_qchip ubsec_q's that share
627 * the same MCR, and complete them too, they must be
630 for (i = 0; i < npkts; i++) {
631 if(q->q_stacked_mcr[i]) {
632 ubsec_callback(sc, q->q_stacked_mcr[i]);
637 ubsec_callback(sc, q);
640 * Don't send any more packet to chip if there has been
643 if (!(stat & BS_STAT_DMAERR))
645 mtx_unlock(&sc->sc_mcr1lock);
649 * Check to see if we have any key setups/rng's waiting for us
651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
652 (stat & BS_STAT_MCR2_DONE)) {
654 struct ubsec_mcr *mcr;
656 mtx_lock(&sc->sc_mcr2lock);
657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
660 ubsec_dma_sync(&q2->q_mcr,
661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
665 ubsec_dma_sync(&q2->q_mcr,
666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next);
670 ubsec_callback2(sc, q2);
672 * Don't send any more packet to chip if there has been
675 if (!(stat & BS_STAT_DMAERR))
678 mtx_unlock(&sc->sc_mcr2lock);
682 * Check to see if we got any DMA Error
684 if (stat & BS_STAT_DMAERR) {
687 volatile u_int32_t a = READ_REG(sc, BS_ERR);
689 printf("dmaerr %s@%08x\n",
690 (a & BS_ERR_READ) ? "read" : "write",
693 #endif /* UBSEC_DEBUG */
694 ubsecstats.hst_dmaerr++;
695 mtx_lock(&sc->sc_mcr1lock);
696 ubsec_totalreset(sc);
698 mtx_unlock(&sc->sc_mcr1lock);
701 if (sc->sc_needwakeup) { /* XXX check high watermark */
704 mtx_lock(&sc->sc_freeqlock);
705 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
708 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
710 #endif /* UBSEC_DEBUG */
711 sc->sc_needwakeup &= ~wakeup;
712 mtx_unlock(&sc->sc_freeqlock);
713 crypto_unblock(sc->sc_cid, wakeup);
718 * ubsec_feed() - aggregate and post requests to chip
721 ubsec_feed(struct ubsec_softc *sc)
723 struct ubsec_q *q, *q2;
729 * Decide how many ops to combine in a single MCR. We cannot
730 * aggregate more than UBS_MAX_AGGR because this is the number
731 * of slots defined in the data structure. Note that
732 * aggregation only happens if ops are marked batch'able.
733 * Aggregating ops reduces the number of interrupts to the host
734 * but also (potentially) increases the latency for processing
735 * completed ops as we only get an interrupt when all aggregated
736 * ops have completed.
738 if (sc->sc_nqueue == 0)
740 if (sc->sc_nqueue > 1) {
742 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
744 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
750 * Check device status before going any further.
752 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
753 if (stat & BS_STAT_DMAERR) {
754 ubsec_totalreset(sc);
755 ubsecstats.hst_dmaerr++;
757 ubsecstats.hst_mcr1full++;
760 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
761 ubsecstats.hst_maxqueue = sc->sc_nqueue;
762 if (npkts > UBS_MAX_AGGR)
763 npkts = UBS_MAX_AGGR;
764 if (npkts < 2) /* special case 1 op */
767 ubsecstats.hst_totbatch += npkts-1;
770 printf("merging %d records\n", npkts);
771 #endif /* UBSEC_DEBUG */
773 q = SIMPLEQ_FIRST(&sc->sc_queue);
774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
777 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
778 if (q->q_dst_map != NULL)
779 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
781 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
783 for (i = 0; i < q->q_nstacked_mcrs; i++) {
784 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
785 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
786 BUS_DMASYNC_PREWRITE);
787 if (q2->q_dst_map != NULL)
788 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
789 BUS_DMASYNC_PREREAD);
790 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next);
793 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
794 sizeof(struct ubsec_mcr_add));
795 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
796 q->q_stacked_mcr[i] = q2;
798 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
799 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
800 sc->sc_nqchip += npkts;
801 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
802 ubsecstats.hst_maxqchip = sc->sc_nqchip;
803 ubsec_dma_sync(&q->q_dma->d_alloc,
804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
806 offsetof(struct ubsec_dmachunk, d_mcr));
809 q = SIMPLEQ_FIRST(&sc->sc_queue);
811 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
812 if (q->q_dst_map != NULL)
813 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
814 ubsec_dma_sync(&q->q_dma->d_alloc,
815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
817 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
818 offsetof(struct ubsec_dmachunk, d_mcr));
821 printf("feed1: q->chip %p %08x stat %08x\n",
822 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
824 #endif /* UBSEC_DEBUG */
825 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next);
827 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
829 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
830 ubsecstats.hst_maxqchip = sc->sc_nqchip;
835 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
838 /* Go ahead and compute key in ubsec's byte order */
839 if (algo == CRYPTO_DES_CBC) {
840 bcopy(key, &ses->ses_deskey[0], 8);
841 bcopy(key, &ses->ses_deskey[2], 8);
842 bcopy(key, &ses->ses_deskey[4], 8);
844 bcopy(key, ses->ses_deskey, 24);
846 SWAP32(ses->ses_deskey[0]);
847 SWAP32(ses->ses_deskey[1]);
848 SWAP32(ses->ses_deskey[2]);
849 SWAP32(ses->ses_deskey[3]);
850 SWAP32(ses->ses_deskey[4]);
851 SWAP32(ses->ses_deskey[5]);
855 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
861 for (i = 0; i < klen; i++)
862 key[i] ^= HMAC_IPAD_VAL;
864 if (algo == CRYPTO_MD5_HMAC) {
866 MD5Update(&md5ctx, key, klen);
867 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
868 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
871 SHA1Update(&sha1ctx, key, klen);
872 SHA1Update(&sha1ctx, hmac_ipad_buffer,
873 SHA1_HMAC_BLOCK_LEN - klen);
874 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
877 for (i = 0; i < klen; i++)
878 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
880 if (algo == CRYPTO_MD5_HMAC) {
882 MD5Update(&md5ctx, key, klen);
883 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
884 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
887 SHA1Update(&sha1ctx, key, klen);
888 SHA1Update(&sha1ctx, hmac_opad_buffer,
889 SHA1_HMAC_BLOCK_LEN - klen);
890 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
893 for (i = 0; i < klen; i++)
894 key[i] ^= HMAC_OPAD_VAL;
898 * Allocate a new 'session' and return an encoded session id. 'sidp'
899 * contains our registration id, and should contain an encoded session
900 * id on successful allocation.
903 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
905 struct cryptoini *c, *encini = NULL, *macini = NULL;
906 struct ubsec_softc *sc = arg;
907 struct ubsec_session *ses = NULL;
910 if (sidp == NULL || cri == NULL || sc == NULL)
913 for (c = cri; c != NULL; c = c->cri_next) {
914 if (c->cri_alg == CRYPTO_MD5_HMAC ||
915 c->cri_alg == CRYPTO_SHA1_HMAC) {
919 } else if (c->cri_alg == CRYPTO_DES_CBC ||
920 c->cri_alg == CRYPTO_3DES_CBC) {
927 if (encini == NULL && macini == NULL)
930 if (sc->sc_sessions == NULL) {
931 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
932 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
936 sc->sc_nsessions = 1;
938 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
939 if (sc->sc_sessions[sesn].ses_used == 0) {
940 ses = &sc->sc_sessions[sesn];
946 sesn = sc->sc_nsessions;
947 ses = (struct ubsec_session *)malloc((sesn + 1) *
948 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
951 bcopy(sc->sc_sessions, ses, sesn *
952 sizeof(struct ubsec_session));
953 bzero(sc->sc_sessions, sesn *
954 sizeof(struct ubsec_session));
955 free(sc->sc_sessions, M_DEVBUF);
956 sc->sc_sessions = ses;
957 ses = &sc->sc_sessions[sesn];
961 bzero(ses, sizeof(struct ubsec_session));
965 /* get an IV, network byte order */
966 /* XXX may read fewer than requested */
967 read_random(ses->ses_iv, sizeof(ses->ses_iv));
969 if (encini->cri_key != NULL) {
970 ubsec_setup_enckey(ses, encini->cri_alg,
976 ses->ses_mlen = macini->cri_mlen;
977 if (ses->ses_mlen == 0) {
978 if (macini->cri_alg == CRYPTO_MD5_HMAC)
979 ses->ses_mlen = MD5_HASH_LEN;
981 ses->ses_mlen = SHA1_HASH_LEN;
984 if (macini->cri_key != NULL) {
985 ubsec_setup_mackey(ses, macini->cri_alg,
986 macini->cri_key, macini->cri_klen / 8);
990 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
995 * Deallocate a session.
998 ubsec_freesession(void *arg, u_int64_t tid)
1000 struct ubsec_softc *sc = arg;
1002 u_int32_t sid = CRYPTO_SESID2LID(tid);
1007 session = UBSEC_SESSION(sid);
1008 if (session < sc->sc_nsessions) {
1009 bzero(&sc->sc_sessions[session],
1010 sizeof(sc->sc_sessions[session]));
1019 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1021 struct ubsec_operand *op = arg;
1023 KASSERT(nsegs <= UBS_MAX_SCATTER,
1024 ("Too many DMA segments returned when mapping operand"));
1027 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1028 (u_int) mapsize, nsegs, error);
1032 op->mapsize = mapsize;
1034 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1038 ubsec_process(void *arg, struct cryptop *crp, int hint)
1040 struct ubsec_q *q = NULL;
1041 int err = 0, i, j, nicealign;
1042 struct ubsec_softc *sc = arg;
1043 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1044 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1045 int sskip, dskip, stheend, dtheend;
1047 struct ubsec_session *ses;
1048 struct ubsec_pktctx ctx;
1049 struct ubsec_dma *dmap = NULL;
1051 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1052 ubsecstats.hst_invalid++;
1055 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1056 ubsecstats.hst_badsession++;
1060 mtx_lock(&sc->sc_freeqlock);
1061 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1062 ubsecstats.hst_queuefull++;
1063 sc->sc_needwakeup |= CRYPTO_SYMQ;
1064 mtx_unlock(&sc->sc_freeqlock);
1067 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1068 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next);
1069 mtx_unlock(&sc->sc_freeqlock);
1071 dmap = q->q_dma; /* Save dma pointer */
1072 bzero(q, sizeof(struct ubsec_q));
1073 bzero(&ctx, sizeof(ctx));
1075 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1077 ses = &sc->sc_sessions[q->q_sesn];
1079 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1080 q->q_src_m = (struct mbuf *)crp->crp_buf;
1081 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1082 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1083 q->q_src_io = (struct uio *)crp->crp_buf;
1084 q->q_dst_io = (struct uio *)crp->crp_buf;
1086 ubsecstats.hst_badflags++;
1088 goto errout; /* XXX we don't handle contiguous blocks! */
1091 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1093 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1094 dmap->d_dma->d_mcr.mcr_flags = 0;
1097 crd1 = crp->crp_desc;
1099 ubsecstats.hst_nodesc++;
1103 crd2 = crd1->crd_next;
1106 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1107 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1110 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1111 crd1->crd_alg == CRYPTO_3DES_CBC) {
1115 ubsecstats.hst_badalg++;
1120 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1121 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1122 (crd2->crd_alg == CRYPTO_DES_CBC ||
1123 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1124 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1127 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1128 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1129 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1130 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1131 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1136 * We cannot order the ubsec as requested
1138 ubsecstats.hst_badalg++;
1145 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1146 ubsec_setup_enckey(ses, enccrd->crd_alg,
1150 encoffset = enccrd->crd_skip;
1151 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1153 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1154 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1156 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1157 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1159 ctx.pc_iv[0] = ses->ses_iv[0];
1160 ctx.pc_iv[1] = ses->ses_iv[1];
1163 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1164 crypto_copyback(crp->crp_flags, crp->crp_buf,
1165 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1168 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1170 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1171 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1173 crypto_copydata(crp->crp_flags, crp->crp_buf,
1174 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1178 ctx.pc_deskey[0] = ses->ses_deskey[0];
1179 ctx.pc_deskey[1] = ses->ses_deskey[1];
1180 ctx.pc_deskey[2] = ses->ses_deskey[2];
1181 ctx.pc_deskey[3] = ses->ses_deskey[3];
1182 ctx.pc_deskey[4] = ses->ses_deskey[4];
1183 ctx.pc_deskey[5] = ses->ses_deskey[5];
1184 SWAP32(ctx.pc_iv[0]);
1185 SWAP32(ctx.pc_iv[1]);
1189 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1190 ubsec_setup_mackey(ses, maccrd->crd_alg,
1191 maccrd->crd_key, maccrd->crd_klen / 8);
1194 macoffset = maccrd->crd_skip;
1196 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1197 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1199 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1201 for (i = 0; i < 5; i++) {
1202 ctx.pc_hminner[i] = ses->ses_hminner[i];
1203 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1205 HTOLE32(ctx.pc_hminner[i]);
1206 HTOLE32(ctx.pc_hmouter[i]);
1210 if (enccrd && maccrd) {
1212 * ubsec cannot handle packets where the end of encryption
1213 * and authentication are not the same, or where the
1214 * encrypted part begins before the authenticated part.
1216 if ((encoffset + enccrd->crd_len) !=
1217 (macoffset + maccrd->crd_len)) {
1218 ubsecstats.hst_lenmismatch++;
1222 if (enccrd->crd_skip < maccrd->crd_skip) {
1223 ubsecstats.hst_skipmismatch++;
1227 sskip = maccrd->crd_skip;
1228 cpskip = dskip = enccrd->crd_skip;
1229 stheend = maccrd->crd_len;
1230 dtheend = enccrd->crd_len;
1231 coffset = enccrd->crd_skip - maccrd->crd_skip;
1232 cpoffset = cpskip + dtheend;
1235 printf("mac: skip %d, len %d, inject %d\n",
1236 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1237 printf("enc: skip %d, len %d, inject %d\n",
1238 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1239 printf("src: skip %d, len %d\n", sskip, stheend);
1240 printf("dst: skip %d, len %d\n", dskip, dtheend);
1241 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1242 coffset, stheend, cpskip, cpoffset);
1246 cpskip = dskip = sskip = macoffset + encoffset;
1247 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1248 cpoffset = cpskip + dtheend;
1251 ctx.pc_offset = htole16(coffset >> 2);
1253 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1254 ubsecstats.hst_nomap++;
1258 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1259 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1260 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1261 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1262 q->q_src_map = NULL;
1263 ubsecstats.hst_noload++;
1267 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1268 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1269 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1270 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1271 q->q_src_map = NULL;
1272 ubsecstats.hst_noload++;
1277 nicealign = ubsec_dmamap_aligned(&q->q_src);
1279 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1283 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1285 for (i = j = 0; i < q->q_src_nsegs; i++) {
1286 struct ubsec_pktbuf *pb;
1287 bus_size_t packl = q->q_src_segs[i].ds_len;
1288 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1290 if (sskip >= packl) {
1299 if (packl > 0xfffc) {
1305 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1307 pb = &dmap->d_dma->d_sbuf[j - 1];
1309 pb->pb_addr = htole32(packp);
1312 if (packl > stheend) {
1313 pb->pb_len = htole32(stheend);
1316 pb->pb_len = htole32(packl);
1320 pb->pb_len = htole32(packl);
1322 if ((i + 1) == q->q_src_nsegs)
1325 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1326 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1330 if (enccrd == NULL && maccrd != NULL) {
1331 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1332 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1333 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1334 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1337 printf("opkt: %x %x %x\n",
1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1339 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1340 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1343 if (crp->crp_flags & CRYPTO_F_IOV) {
1345 ubsecstats.hst_iovmisaligned++;
1349 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1351 ubsecstats.hst_nomap++;
1355 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1356 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1357 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1358 q->q_dst_map = NULL;
1359 ubsecstats.hst_noload++;
1363 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1365 q->q_dst = q->q_src;
1368 struct mbuf *m, *top, **mp;
1370 ubsecstats.hst_unaligned++;
1371 totlen = q->q_src_mapsize;
1372 if (q->q_src_m->m_flags & M_PKTHDR) {
1374 MGETHDR(m, M_DONTWAIT, MT_DATA);
1375 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) {
1381 MGET(m, M_DONTWAIT, MT_DATA);
1384 ubsecstats.hst_nombuf++;
1385 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1388 if (totlen >= MINCLSIZE) {
1389 MCLGET(m, M_DONTWAIT);
1390 if ((m->m_flags & M_EXT) == 0) {
1392 ubsecstats.hst_nomcl++;
1393 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1402 while (totlen > 0) {
1404 MGET(m, M_DONTWAIT, MT_DATA);
1407 ubsecstats.hst_nombuf++;
1408 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1413 if (top && totlen >= MINCLSIZE) {
1414 MCLGET(m, M_DONTWAIT);
1415 if ((m->m_flags & M_EXT) == 0) {
1418 ubsecstats.hst_nomcl++;
1419 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1424 m->m_len = len = min(totlen, len);
1430 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1432 if (bus_dmamap_create(sc->sc_dmat,
1433 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1434 ubsecstats.hst_nomap++;
1438 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1439 q->q_dst_map, q->q_dst_m,
1440 ubsec_op_cb, &q->q_dst,
1441 BUS_DMA_NOWAIT) != 0) {
1442 bus_dmamap_destroy(sc->sc_dmat,
1444 q->q_dst_map = NULL;
1445 ubsecstats.hst_noload++;
1451 ubsecstats.hst_badflags++;
1458 printf("dst skip: %d\n", dskip);
1460 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1461 struct ubsec_pktbuf *pb;
1462 bus_size_t packl = q->q_dst_segs[i].ds_len;
1463 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1465 if (dskip >= packl) {
1474 if (packl > 0xfffc) {
1480 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1482 pb = &dmap->d_dma->d_dbuf[j - 1];
1484 pb->pb_addr = htole32(packp);
1487 if (packl > dtheend) {
1488 pb->pb_len = htole32(dtheend);
1491 pb->pb_len = htole32(packl);
1495 pb->pb_len = htole32(packl);
1497 if ((i + 1) == q->q_dst_nsegs) {
1499 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1500 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1504 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1505 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1510 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1511 offsetof(struct ubsec_dmachunk, d_ctx));
1513 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1514 struct ubsec_pktctx_long *ctxl;
1516 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1517 offsetof(struct ubsec_dmachunk, d_ctx));
1519 /* transform small context into long context */
1520 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1521 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1522 ctxl->pc_flags = ctx.pc_flags;
1523 ctxl->pc_offset = ctx.pc_offset;
1524 for (i = 0; i < 6; i++)
1525 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1526 for (i = 0; i < 5; i++)
1527 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1528 for (i = 0; i < 5; i++)
1529 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1530 ctxl->pc_iv[0] = ctx.pc_iv[0];
1531 ctxl->pc_iv[1] = ctx.pc_iv[1];
1533 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1534 offsetof(struct ubsec_dmachunk, d_ctx),
1535 sizeof(struct ubsec_pktctx));
1537 mtx_lock(&sc->sc_mcr1lock);
1538 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1540 ubsecstats.hst_ipackets++;
1541 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1542 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1544 mtx_unlock(&sc->sc_mcr1lock);
1549 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1550 m_freem(q->q_dst_m);
1552 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1553 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1554 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1556 if (q->q_src_map != NULL) {
1557 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1558 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1561 if (q != NULL || err == ERESTART) {
1562 mtx_lock(&sc->sc_freeqlock);
1564 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1565 if (err == ERESTART)
1566 sc->sc_needwakeup |= CRYPTO_SYMQ;
1567 mtx_unlock(&sc->sc_freeqlock);
1569 if (err != ERESTART) {
1570 crp->crp_etype = err;
1577 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1579 struct cryptop *crp = (struct cryptop *)q->q_crp;
1580 struct cryptodesc *crd;
1581 struct ubsec_dma *dmap = q->q_dma;
1583 ubsecstats.hst_opackets++;
1584 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1586 ubsec_dma_sync(&dmap->d_alloc,
1587 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1588 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1589 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1590 BUS_DMASYNC_POSTREAD);
1591 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1592 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1594 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1595 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1596 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1598 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1599 m_freem(q->q_src_m);
1600 crp->crp_buf = (caddr_t)q->q_dst_m;
1603 /* copy out IV for future use */
1604 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1605 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1606 if (crd->crd_alg != CRYPTO_DES_CBC &&
1607 crd->crd_alg != CRYPTO_3DES_CBC)
1609 crypto_copydata(crp->crp_flags, crp->crp_buf,
1610 crd->crd_skip + crd->crd_len - 8, 8,
1611 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1616 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1617 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1618 crd->crd_alg != CRYPTO_SHA1_HMAC)
1620 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1621 sc->sc_sessions[q->q_sesn].ses_mlen,
1622 (caddr_t)dmap->d_dma->d_macbuf);
1625 mtx_lock(&sc->sc_freeqlock);
1626 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1627 mtx_unlock(&sc->sc_freeqlock);
1632 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1634 int i, j, dlen, slen;
1638 sptr = srcm->m_data;
1640 dptr = dstm->m_data;
1644 for (i = 0; i < min(slen, dlen); i++) {
1645 if (j < hoffset || j >= toffset)
1652 srcm = srcm->m_next;
1655 sptr = srcm->m_data;
1659 dstm = dstm->m_next;
1662 dptr = dstm->m_data;
1669 * feed the key generator, must be called at splimp() or higher.
1672 ubsec_feed2(struct ubsec_softc *sc)
1676 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1677 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1679 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1681 ubsec_dma_sync(&q->q_mcr,
1682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1683 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1685 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1686 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next);
1688 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1694 * Callback for handling random numbers
1697 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1699 struct cryptkop *krp;
1700 struct ubsec_ctx_keyop *ctx;
1702 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1703 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1705 switch (q->q_type) {
1706 #ifndef UBSEC_NO_RNG
1707 case UBS_CTXOP_RNGBYPASS: {
1708 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1710 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1711 (*sc->sc_harvest)(sc->sc_rndtest,
1712 rng->rng_buf.dma_vaddr,
1713 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1715 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1719 case UBS_CTXOP_MODEXP: {
1720 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1724 rlen = (me->me_modbits + 7) / 8;
1725 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1727 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1728 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1729 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1730 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1733 krp->krp_status = E2BIG;
1735 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1736 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1737 (krp->krp_param[krp->krp_iparams].crp_nbits
1739 bcopy(me->me_C.dma_vaddr,
1740 krp->krp_param[krp->krp_iparams].crp_p,
1741 (me->me_modbits + 7) / 8);
1743 ubsec_kshift_l(me->me_shiftbits,
1744 me->me_C.dma_vaddr, me->me_normbits,
1745 krp->krp_param[krp->krp_iparams].crp_p,
1746 krp->krp_param[krp->krp_iparams].crp_nbits);
1751 /* bzero all potentially sensitive data */
1752 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1753 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1754 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1755 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1757 /* Can't free here, so put us on the free list. */
1758 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1761 case UBS_CTXOP_RSAPRIV: {
1762 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1766 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1767 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1769 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1770 bcopy(rp->rpr_msgout.dma_vaddr,
1771 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1775 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1776 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1777 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1779 /* Can't free here, so put us on the free list. */
1780 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1784 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1785 letoh16(ctx->ctx_op));
1790 #ifndef UBSEC_NO_RNG
1792 ubsec_rng(void *vsc)
1794 struct ubsec_softc *sc = vsc;
1795 struct ubsec_q2_rng *rng = &sc->sc_rng;
1796 struct ubsec_mcr *mcr;
1797 struct ubsec_ctx_rngbypass *ctx;
1799 mtx_lock(&sc->sc_mcr2lock);
1800 if (rng->rng_used) {
1801 mtx_unlock(&sc->sc_mcr2lock);
1805 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1808 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1809 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1811 mcr->mcr_pkts = htole16(1);
1813 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1814 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1815 mcr->mcr_ipktbuf.pb_len = 0;
1816 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1817 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1818 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1820 mcr->mcr_opktbuf.pb_next = 0;
1822 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1823 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1824 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1826 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1828 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1831 ubsecstats.hst_rng++;
1832 mtx_unlock(&sc->sc_mcr2lock);
1838 * Something weird happened, generate our own call back.
1841 mtx_unlock(&sc->sc_mcr2lock);
1842 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1844 #endif /* UBSEC_NO_RNG */
1847 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1849 bus_addr_t *paddr = (bus_addr_t*) arg;
1850 *paddr = segs->ds_addr;
1855 struct ubsec_softc *sc,
1857 struct ubsec_dma_alloc *dma,
1863 /* XXX could specify sc_dmat as parent but that just adds overhead */
1864 r = bus_dma_tag_create(NULL, /* parent */
1865 1, 0, /* alignment, bounds */
1866 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1867 BUS_SPACE_MAXADDR, /* highaddr */
1868 NULL, NULL, /* filter, filterarg */
1871 size, /* maxsegsize */
1872 BUS_DMA_ALLOCNOW, /* flags */
1873 NULL, NULL, /* lockfunc, lockarg */
1876 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1877 "bus_dma_tag_create failed; error %u\n", r);
1881 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1883 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1884 "bus_dmamap_create failed; error %u\n", r);
1888 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1889 BUS_DMA_NOWAIT, &dma->dma_map);
1891 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1892 "bus_dmammem_alloc failed; size %zu, error %u\n",
1897 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1901 mapflags | BUS_DMA_NOWAIT);
1903 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1904 "bus_dmamap_load failed; error %u\n", r);
1908 dma->dma_size = size;
1912 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1914 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1916 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1917 bus_dma_tag_destroy(dma->dma_tag);
1919 dma->dma_map = NULL;
1920 dma->dma_tag = NULL;
1925 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1927 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1928 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1929 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1930 bus_dma_tag_destroy(dma->dma_tag);
1934 * Resets the board. Values in the regesters are left as is
1935 * from the reset (i.e. initial values are assigned elsewhere).
1938 ubsec_reset_board(struct ubsec_softc *sc)
1940 volatile u_int32_t ctrl;
1942 ctrl = READ_REG(sc, BS_CTRL);
1943 ctrl |= BS_CTRL_RESET;
1944 WRITE_REG(sc, BS_CTRL, ctrl);
1947 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1953 * Init Broadcom registers
1956 ubsec_init_board(struct ubsec_softc *sc)
1960 ctrl = READ_REG(sc, BS_CTRL);
1961 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1962 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1964 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1965 ctrl |= BS_CTRL_MCR2INT;
1967 ctrl &= ~BS_CTRL_MCR2INT;
1969 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1970 ctrl &= ~BS_CTRL_SWNORM;
1972 WRITE_REG(sc, BS_CTRL, ctrl);
1976 * Init Broadcom PCI registers
1979 ubsec_init_pciregs(device_t dev)
1984 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1985 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1986 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1987 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1988 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1989 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1993 * This will set the cache line size to 1, this will
1994 * force the BCM58xx chip just to do burst read/writes.
1995 * Cache line read/writes are to slow
1997 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
2001 * Clean up after a chip crash.
2002 * It is assumed that the caller in splimp()
2005 ubsec_cleanchip(struct ubsec_softc *sc)
2009 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2010 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2011 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next);
2012 ubsec_free_q(sc, q);
2019 * It is assumed that the caller is within splimp().
2022 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2025 struct cryptop *crp;
2029 npkts = q->q_nstacked_mcrs;
2031 for (i = 0; i < npkts; i++) {
2032 if(q->q_stacked_mcr[i]) {
2033 q2 = q->q_stacked_mcr[i];
2035 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2036 m_freem(q2->q_dst_m);
2038 crp = (struct cryptop *)q2->q_crp;
2040 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2042 crp->crp_etype = EFAULT;
2052 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2053 m_freem(q->q_dst_m);
2055 crp = (struct cryptop *)q->q_crp;
2057 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2059 crp->crp_etype = EFAULT;
2065 * Routine to reset the chip and clean up.
2066 * It is assumed that the caller is in splimp()
2069 ubsec_totalreset(struct ubsec_softc *sc)
2071 ubsec_reset_board(sc);
2072 ubsec_init_board(sc);
2073 ubsec_cleanchip(sc);
2077 ubsec_dmamap_aligned(struct ubsec_operand *op)
2081 for (i = 0; i < op->nsegs; i++) {
2082 if (op->segs[i].ds_addr & 3)
2084 if ((i != (op->nsegs - 1)) &&
2085 (op->segs[i].ds_len & 3))
2092 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2094 switch (q->q_type) {
2095 case UBS_CTXOP_MODEXP: {
2096 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2098 ubsec_dma_free(sc, &me->me_q.q_mcr);
2099 ubsec_dma_free(sc, &me->me_q.q_ctx);
2100 ubsec_dma_free(sc, &me->me_M);
2101 ubsec_dma_free(sc, &me->me_E);
2102 ubsec_dma_free(sc, &me->me_C);
2103 ubsec_dma_free(sc, &me->me_epb);
2107 case UBS_CTXOP_RSAPRIV: {
2108 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2110 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2111 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2112 ubsec_dma_free(sc, &rp->rpr_msgin);
2113 ubsec_dma_free(sc, &rp->rpr_msgout);
2118 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2124 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2126 struct ubsec_softc *sc = arg;
2129 if (krp == NULL || krp->krp_callback == NULL)
2132 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2135 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2136 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next);
2140 switch (krp->krp_op) {
2142 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2143 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2145 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2147 case CRK_MOD_EXP_CRT:
2148 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2150 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2152 krp->krp_status = EOPNOTSUPP;
2156 return (0); /* silence compiler */
2160 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2163 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2165 struct ubsec_q2_modexp *me;
2166 struct ubsec_mcr *mcr;
2167 struct ubsec_ctx_modexp *ctx;
2168 struct ubsec_pktbuf *epb;
2170 u_int nbits, normbits, mbits, shiftbits, ebits;
2172 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2177 bzero(me, sizeof *me);
2179 me->me_q.q_type = UBS_CTXOP_MODEXP;
2181 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2184 else if (nbits <= 768)
2186 else if (nbits <= 1024)
2188 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2190 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2197 shiftbits = normbits - nbits;
2199 me->me_modbits = nbits;
2200 me->me_shiftbits = shiftbits;
2201 me->me_normbits = normbits;
2203 /* Sanity check: result bits must be >= true modulus bits. */
2204 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2209 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2210 &me->me_q.q_mcr, 0)) {
2214 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2216 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2217 &me->me_q.q_ctx, 0)) {
2222 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2223 if (mbits > nbits) {
2227 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2231 ubsec_kshift_r(shiftbits,
2232 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2233 me->me_M.dma_vaddr, normbits);
2235 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2239 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2241 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2242 if (ebits > nbits) {
2246 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2250 ubsec_kshift_r(shiftbits,
2251 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2252 me->me_E.dma_vaddr, normbits);
2254 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2259 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2260 epb->pb_addr = htole32(me->me_E.dma_paddr);
2262 epb->pb_len = htole32(normbits / 8);
2271 mcr->mcr_pkts = htole16(1);
2273 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2274 mcr->mcr_reserved = 0;
2275 mcr->mcr_pktlen = 0;
2277 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2278 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2279 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2281 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2282 mcr->mcr_opktbuf.pb_next = 0;
2283 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2286 /* Misaligned output buffer will hang the chip. */
2287 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2288 panic("%s: modexp invalid addr 0x%x\n",
2289 device_get_nameunit(sc->sc_dev),
2290 letoh32(mcr->mcr_opktbuf.pb_addr));
2291 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2292 panic("%s: modexp invalid len 0x%x\n",
2293 device_get_nameunit(sc->sc_dev),
2294 letoh32(mcr->mcr_opktbuf.pb_len));
2297 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2298 bzero(ctx, sizeof(*ctx));
2299 ubsec_kshift_r(shiftbits,
2300 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2301 ctx->me_N, normbits);
2302 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2303 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2304 ctx->me_E_len = htole16(nbits);
2305 ctx->me_N_len = htole16(nbits);
2309 ubsec_dump_mcr(mcr);
2310 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2315 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2318 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2319 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2320 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2321 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2323 /* Enqueue and we're done... */
2324 mtx_lock(&sc->sc_mcr2lock);
2325 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2327 ubsecstats.hst_modexp++;
2328 mtx_unlock(&sc->sc_mcr2lock);
2334 if (me->me_q.q_mcr.dma_map != NULL)
2335 ubsec_dma_free(sc, &me->me_q.q_mcr);
2336 if (me->me_q.q_ctx.dma_map != NULL) {
2337 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2338 ubsec_dma_free(sc, &me->me_q.q_ctx);
2340 if (me->me_M.dma_map != NULL) {
2341 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2342 ubsec_dma_free(sc, &me->me_M);
2344 if (me->me_E.dma_map != NULL) {
2345 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2346 ubsec_dma_free(sc, &me->me_E);
2348 if (me->me_C.dma_map != NULL) {
2349 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2350 ubsec_dma_free(sc, &me->me_C);
2352 if (me->me_epb.dma_map != NULL)
2353 ubsec_dma_free(sc, &me->me_epb);
2356 krp->krp_status = err;
2362 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2365 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2367 struct ubsec_q2_modexp *me;
2368 struct ubsec_mcr *mcr;
2369 struct ubsec_ctx_modexp *ctx;
2370 struct ubsec_pktbuf *epb;
2372 u_int nbits, normbits, mbits, shiftbits, ebits;
2374 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2379 bzero(me, sizeof *me);
2381 me->me_q.q_type = UBS_CTXOP_MODEXP;
2383 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2386 else if (nbits <= 768)
2388 else if (nbits <= 1024)
2390 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2392 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2399 shiftbits = normbits - nbits;
2402 me->me_modbits = nbits;
2403 me->me_shiftbits = shiftbits;
2404 me->me_normbits = normbits;
2406 /* Sanity check: result bits must be >= true modulus bits. */
2407 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2412 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2413 &me->me_q.q_mcr, 0)) {
2417 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2419 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2420 &me->me_q.q_ctx, 0)) {
2425 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2426 if (mbits > nbits) {
2430 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2434 bzero(me->me_M.dma_vaddr, normbits / 8);
2435 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2436 me->me_M.dma_vaddr, (mbits + 7) / 8);
2438 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2442 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2444 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2445 if (ebits > nbits) {
2449 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2453 bzero(me->me_E.dma_vaddr, normbits / 8);
2454 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2455 me->me_E.dma_vaddr, (ebits + 7) / 8);
2457 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2462 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2463 epb->pb_addr = htole32(me->me_E.dma_paddr);
2465 epb->pb_len = htole32((ebits + 7) / 8);
2474 mcr->mcr_pkts = htole16(1);
2476 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2477 mcr->mcr_reserved = 0;
2478 mcr->mcr_pktlen = 0;
2480 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2481 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2482 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2484 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2485 mcr->mcr_opktbuf.pb_next = 0;
2486 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2489 /* Misaligned output buffer will hang the chip. */
2490 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2491 panic("%s: modexp invalid addr 0x%x\n",
2492 device_get_nameunit(sc->sc_dev),
2493 letoh32(mcr->mcr_opktbuf.pb_addr));
2494 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2495 panic("%s: modexp invalid len 0x%x\n",
2496 device_get_nameunit(sc->sc_dev),
2497 letoh32(mcr->mcr_opktbuf.pb_len));
2500 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2501 bzero(ctx, sizeof(*ctx));
2502 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2504 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2505 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2506 ctx->me_E_len = htole16(ebits);
2507 ctx->me_N_len = htole16(nbits);
2511 ubsec_dump_mcr(mcr);
2512 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2517 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2520 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2521 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2522 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2523 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2525 /* Enqueue and we're done... */
2526 mtx_lock(&sc->sc_mcr2lock);
2527 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2529 mtx_unlock(&sc->sc_mcr2lock);
2535 if (me->me_q.q_mcr.dma_map != NULL)
2536 ubsec_dma_free(sc, &me->me_q.q_mcr);
2537 if (me->me_q.q_ctx.dma_map != NULL) {
2538 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2539 ubsec_dma_free(sc, &me->me_q.q_ctx);
2541 if (me->me_M.dma_map != NULL) {
2542 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2543 ubsec_dma_free(sc, &me->me_M);
2545 if (me->me_E.dma_map != NULL) {
2546 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2547 ubsec_dma_free(sc, &me->me_E);
2549 if (me->me_C.dma_map != NULL) {
2550 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2551 ubsec_dma_free(sc, &me->me_C);
2553 if (me->me_epb.dma_map != NULL)
2554 ubsec_dma_free(sc, &me->me_epb);
2557 krp->krp_status = err;
2563 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2565 struct ubsec_q2_rsapriv *rp = NULL;
2566 struct ubsec_mcr *mcr;
2567 struct ubsec_ctx_rsapriv *ctx;
2569 u_int padlen, msglen;
2571 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2572 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2573 if (msglen > padlen)
2578 else if (padlen <= 384)
2580 else if (padlen <= 512)
2582 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2584 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2591 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2596 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2601 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2606 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2609 bzero(rp, sizeof *rp);
2611 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2613 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2614 &rp->rpr_q.q_mcr, 0)) {
2618 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2620 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2621 &rp->rpr_q.q_ctx, 0)) {
2625 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2626 bzero(ctx, sizeof *ctx);
2629 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2630 &ctx->rpr_buf[0 * (padlen / 8)],
2631 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2634 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2635 &ctx->rpr_buf[1 * (padlen / 8)],
2636 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2639 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2640 &ctx->rpr_buf[2 * (padlen / 8)],
2641 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2644 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2645 &ctx->rpr_buf[3 * (padlen / 8)],
2646 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2649 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2650 &ctx->rpr_buf[4 * (padlen / 8)],
2651 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2653 msglen = padlen * 2;
2655 /* Copy in input message (aligned buffer/length). */
2656 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2657 /* Is this likely? */
2661 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2665 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2666 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2667 rp->rpr_msgin.dma_vaddr,
2668 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2670 /* Prepare space for output message (aligned buffer/length). */
2671 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2672 /* Is this likely? */
2676 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2680 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2682 mcr->mcr_pkts = htole16(1);
2684 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2685 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2686 mcr->mcr_ipktbuf.pb_next = 0;
2687 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2688 mcr->mcr_reserved = 0;
2689 mcr->mcr_pktlen = htole16(msglen);
2690 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2691 mcr->mcr_opktbuf.pb_next = 0;
2692 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2695 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2696 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2697 device_get_nameunit(sc->sc_dev),
2698 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2700 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2701 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2702 device_get_nameunit(sc->sc_dev),
2703 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2707 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2708 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2709 ctx->rpr_q_len = htole16(padlen);
2710 ctx->rpr_p_len = htole16(padlen);
2713 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2716 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2717 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2719 /* Enqueue and we're done... */
2720 mtx_lock(&sc->sc_mcr2lock);
2721 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2723 ubsecstats.hst_modexpcrt++;
2724 mtx_unlock(&sc->sc_mcr2lock);
2729 if (rp->rpr_q.q_mcr.dma_map != NULL)
2730 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2731 if (rp->rpr_msgin.dma_map != NULL) {
2732 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2733 ubsec_dma_free(sc, &rp->rpr_msgin);
2735 if (rp->rpr_msgout.dma_map != NULL) {
2736 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2737 ubsec_dma_free(sc, &rp->rpr_msgout);
2741 krp->krp_status = err;
2748 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2750 printf("addr 0x%x (0x%x) next 0x%x\n",
2751 pb->pb_addr, pb->pb_len, pb->pb_next);
2755 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2757 printf("CTX (0x%x):\n", c->ctx_len);
2758 switch (letoh16(c->ctx_op)) {
2759 case UBS_CTXOP_RNGBYPASS:
2760 case UBS_CTXOP_RNGSHA1:
2762 case UBS_CTXOP_MODEXP:
2764 struct ubsec_ctx_modexp *cx = (void *)c;
2767 printf(" Elen %u, Nlen %u\n",
2768 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2769 len = (cx->me_N_len + 7)/8;
2770 for (i = 0; i < len; i++)
2771 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2776 printf("unknown context: %x\n", c->ctx_op);
2778 printf("END CTX\n");
2782 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2784 volatile struct ubsec_mcr_add *ma;
2788 printf(" pkts: %u, flags 0x%x\n",
2789 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2790 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2791 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2792 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2793 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2794 letoh16(ma->mcr_reserved));
2795 printf(" %d: ipkt ", i);
2796 ubsec_dump_pb(&ma->mcr_ipktbuf);
2797 printf(" %d: opkt ", i);
2798 ubsec_dump_pb(&ma->mcr_opktbuf);
2801 printf("END MCR\n");
2803 #endif /* UBSEC_DEBUG */
2806 * Return the number of significant bits of a big number.
2809 ubsec_ksigbits(struct crparam *cr)
2811 u_int plen = (cr->crp_nbits + 7) / 8;
2812 int i, sig = plen * 8;
2813 u_int8_t c, *p = cr->crp_p;
2815 for (i = plen - 1; i >= 0; i--) {
2818 while ((c & 0x80) == 0) {
2832 u_int8_t *src, u_int srcbits,
2833 u_int8_t *dst, u_int dstbits)
2838 slen = (srcbits + 7) / 8;
2839 dlen = (dstbits + 7) / 8;
2841 for (i = 0; i < slen; i++)
2843 for (i = 0; i < dlen - slen; i++)
2851 dst[di--] = dst[si--];
2858 for (i = dlen - 1; i > 0; i--)
2859 dst[i] = (dst[i] << n) |
2860 (dst[i - 1] >> (8 - n));
2861 dst[0] = dst[0] << n;
2868 u_int8_t *src, u_int srcbits,
2869 u_int8_t *dst, u_int dstbits)
2871 int slen, dlen, i, n;
2873 slen = (srcbits + 7) / 8;
2874 dlen = (dstbits + 7) / 8;
2877 for (i = 0; i < slen; i++)
2878 dst[i] = src[i + n];
2879 for (i = 0; i < dlen - slen; i++)
2884 for (i = 0; i < (dlen - 1); i++)
2885 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2886 dst[dlen - 1] = dst[dlen - 1] >> n;