sys/dev/ubsec/ubsec.c

   1 /*      $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $       */
   2
   3 /*-
   4  * SPDX-License-Identifier: BSD-4-Clause
   5  *
   6  * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
   7  * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
   8  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   9  *
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *      This product includes software developed by Jason L. Wright
  23  * 4. The name of the author may not be used to endorse or promote products
  24  *    derived from this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  27  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  34  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  35  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  36  * POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Effort sponsored in part by the Defense Advanced Research Projects
  39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  41  */
  42
  43 #include <sys/cdefs.h>
  44 __FBSDID("$FreeBSD$");
  45
  46 /*
  47  * uBsec 5[56]01, 58xx hardware crypto accelerator
  48  */
  49
  50 #include "opt_ubsec.h"
  51
  52 #include <sys/param.h>
  53 #include <sys/systm.h>
  54 #include <sys/proc.h>
  55 #include <sys/errno.h>
  56 #include <sys/malloc.h>
  57 #include <sys/kernel.h>
  58 #include <sys/module.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/lock.h>
  61 #include <sys/mutex.h>
  62 #include <sys/sysctl.h>
  63 #include <sys/endian.h>
  64
  65 #include <vm/vm.h>
  66 #include <vm/pmap.h>
  67
  68 #include <machine/bus.h>
  69 #include <machine/resource.h>
  70 #include <sys/bus.h>
  71 #include <sys/rman.h>
  72
  73 #include <crypto/sha1.h>
  74 #include <opencrypto/cryptodev.h>
  75 #include <opencrypto/cryptosoft.h>
  76 #include <sys/md5.h>
  77 #include <sys/random.h>
  78 #include <sys/kobj.h>
  79
  80 #include "cryptodev_if.h"
  81
  82 #include <dev/pci/pcivar.h>
  83 #include <dev/pci/pcireg.h>
  84
  85 /* grr, #defines for gratuitous incompatibility in queue.h */
  86 #define SIMPLEQ_HEAD            STAILQ_HEAD
  87 #define SIMPLEQ_ENTRY           STAILQ_ENTRY
  88 #define SIMPLEQ_INIT            STAILQ_INIT
  89 #define SIMPLEQ_INSERT_TAIL     STAILQ_INSERT_TAIL
  90 #define SIMPLEQ_EMPTY           STAILQ_EMPTY
  91 #define SIMPLEQ_FIRST           STAILQ_FIRST
  92 #define SIMPLEQ_REMOVE_HEAD     STAILQ_REMOVE_HEAD
  93 #define SIMPLEQ_FOREACH         STAILQ_FOREACH
  94 /* ditto for endian.h */
  95 #define letoh16(x)              le16toh(x)
  96 #define letoh32(x)              le32toh(x)
  97
  98 #ifdef UBSEC_RNDTEST
  99 #include <dev/rndtest/rndtest.h>
 100 #endif
 101 #include <dev/ubsec/ubsecreg.h>
 102 #include <dev/ubsec/ubsecvar.h>
 103
 104 /*
 105  * Prototypes and count for the pci_device structure
 106  */
 107 static  int ubsec_probe(device_t);
 108 static  int ubsec_attach(device_t);
 109 static  int ubsec_detach(device_t);
 110 static  int ubsec_suspend(device_t);
 111 static  int ubsec_resume(device_t);
 112 static  int ubsec_shutdown(device_t);
 113
 114 static  int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
 115 static  int ubsec_freesession(device_t, u_int64_t);
 116 static  int ubsec_process(device_t, struct cryptop *, int);
 117 static  int ubsec_kprocess(device_t, struct cryptkop *, int);
 118
 119 static device_method_t ubsec_methods[] = {
 120         /* Device interface */
 121         DEVMETHOD(device_probe,         ubsec_probe),
 122         DEVMETHOD(device_attach,        ubsec_attach),
 123         DEVMETHOD(device_detach,        ubsec_detach),
 124         DEVMETHOD(device_suspend,       ubsec_suspend),
 125         DEVMETHOD(device_resume,        ubsec_resume),
 126         DEVMETHOD(device_shutdown,      ubsec_shutdown),
 127
 128         /* crypto device methods */
 129         DEVMETHOD(cryptodev_newsession, ubsec_newsession),
 130         DEVMETHOD(cryptodev_freesession,ubsec_freesession),
 131         DEVMETHOD(cryptodev_process,    ubsec_process),
 132         DEVMETHOD(cryptodev_kprocess,   ubsec_kprocess),
 133
 134         DEVMETHOD_END
 135 };
 136 static driver_t ubsec_driver = {
 137         "ubsec",
 138         ubsec_methods,
 139         sizeof (struct ubsec_softc)
 140 };
 141 static devclass_t ubsec_devclass;
 142
 143 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
 144 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
 145 #ifdef UBSEC_RNDTEST
 146 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
 147 #endif
 148
 149 static  void ubsec_intr(void *);
 150 static  void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
 151 static  void ubsec_feed(struct ubsec_softc *);
 152 static  void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
 153 static  void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
 154 static  int ubsec_feed2(struct ubsec_softc *);
 155 static  void ubsec_rng(void *);
 156 static  int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
 157                              struct ubsec_dma_alloc *, int);
 158 #define ubsec_dma_sync(_dma, _flags) \
 159         bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
 160 static  void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
 161 static  int ubsec_dmamap_aligned(struct ubsec_operand *op);
 162
 163 static  void ubsec_reset_board(struct ubsec_softc *sc);
 164 static  void ubsec_init_board(struct ubsec_softc *sc);
 165 static  void ubsec_init_pciregs(device_t dev);
 166 static  void ubsec_totalreset(struct ubsec_softc *sc);
 167
 168 static  int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
 169
 170 static  int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
 171 static  int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
 172 static  int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
 173 static  void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
 174 static  int ubsec_ksigbits(struct crparam *);
 175 static  void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 176 static  void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
 177
 178 static SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0,
 179     "Broadcom driver parameters");
 180
 181 #ifdef UBSEC_DEBUG
 182 static  void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
 183 static  void ubsec_dump_mcr(struct ubsec_mcr *);
 184 static  void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
 185
 186 static  int ubsec_debug = 0;
 187 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
 188             0, "control debugging msgs");
 189 #endif
 190
 191 #define READ_REG(sc,r) \
 192         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
 193
 194 #define WRITE_REG(sc,reg,val) \
 195         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
 196
 197 #define SWAP32(x) (x) = htole32(ntohl((x)))
 198 #define HTOLE32(x) (x) = htole32(x)
 199
 200 struct ubsec_stats ubsecstats;
 201 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
 202             ubsec_stats, "driver statistics");
 203
 204 static int
 205 ubsec_probe(device_t dev)
 206 {
 207         if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 208             (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
 209              pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
 210                 return (BUS_PROBE_DEFAULT);
 211         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 212             (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
 213              pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
 214                 return (BUS_PROBE_DEFAULT);
 215         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 216             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
 217              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 218              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
 219              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
 220              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 221              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 222              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
 223              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
 224              ))
 225                 return (BUS_PROBE_DEFAULT);
 226         return (ENXIO);
 227 }
 228
 229 static const char*
 230 ubsec_partname(struct ubsec_softc *sc)
 231 {
 232         /* XXX sprintf numbers when not decoded */
 233         switch (pci_get_vendor(sc->sc_dev)) {
 234         case PCI_VENDOR_BROADCOM:
 235                 switch (pci_get_device(sc->sc_dev)) {
 236                 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
 237                 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
 238                 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
 239                 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
 240                 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
 241                 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
 242                 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
 243                 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
 244                 }
 245                 return "Broadcom unknown-part";
 246         case PCI_VENDOR_BLUESTEEL:
 247                 switch (pci_get_device(sc->sc_dev)) {
 248                 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
 249                 }
 250                 return "Bluesteel unknown-part";
 251         case PCI_VENDOR_SUN:
 252                 switch (pci_get_device(sc->sc_dev)) {
 253                 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
 254                 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
 255                 }
 256                 return "Sun unknown-part";
 257         }
 258         return "Unknown-vendor unknown-part";
 259 }
 260
 261 static void
 262 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
 263 {
 264         /* MarkM: FIX!! Check that this does not swamp the harvester! */
 265         random_harvest_queue(buf, count, count*NBBY/2, RANDOM_PURE_UBSEC);
 266 }
 267
 268 static int
 269 ubsec_attach(device_t dev)
 270 {
 271         struct ubsec_softc *sc = device_get_softc(dev);
 272         struct ubsec_dma *dmap;
 273         u_int32_t i;
 274         int rid;
 275
 276         bzero(sc, sizeof (*sc));
 277         sc->sc_dev = dev;
 278
 279         SIMPLEQ_INIT(&sc->sc_queue);
 280         SIMPLEQ_INIT(&sc->sc_qchip);
 281         SIMPLEQ_INIT(&sc->sc_queue2);
 282         SIMPLEQ_INIT(&sc->sc_qchip2);
 283         SIMPLEQ_INIT(&sc->sc_q2free);
 284
 285         /* XXX handle power management */
 286
 287         sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
 288
 289         if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
 290             pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
 291                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 292
 293         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 294             (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
 295              pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
 296                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
 297
 298         if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 299             pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
 300                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 301                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 302
 303         if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
 304              (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
 305               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
 306               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
 307               pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
 308             (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
 309              (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
 310               pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
 311                 /* NB: the 5821/5822 defines some additional status bits */
 312                 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
 313                     BS_STAT_MCR2_ALLEMPTY;
 314                 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
 315                     UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
 316         }
 317
 318         pci_enable_busmaster(dev);
 319
 320         /*
 321          * Setup memory-mapping of PCI registers.
 322          */
 323         rid = BS_BAR;
 324         sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 325                                            RF_ACTIVE);
 326         if (sc->sc_sr == NULL) {
 327                 device_printf(dev, "cannot map register space\n");
 328                 goto bad;
 329         }
 330         sc->sc_st = rman_get_bustag(sc->sc_sr);
 331         sc->sc_sh = rman_get_bushandle(sc->sc_sr);
 332
 333         /*
 334          * Arrange interrupt line.
 335          */
 336         rid = 0;
 337         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 338                                             RF_SHAREABLE|RF_ACTIVE);
 339         if (sc->sc_irq == NULL) {
 340                 device_printf(dev, "could not map interrupt\n");
 341                 goto bad1;
 342         }
 343         /*
 344          * NB: Network code assumes we are blocked with splimp()
 345          *     so make sure the IRQ is mapped appropriately.
 346          */
 347         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
 348                            NULL, ubsec_intr, sc, &sc->sc_ih)) {
 349                 device_printf(dev, "could not establish interrupt\n");
 350                 goto bad2;
 351         }
 352
 353         sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
 354         if (sc->sc_cid < 0) {
 355                 device_printf(dev, "could not get crypto driver id\n");
 356                 goto bad3;
 357         }
 358
 359         /*
 360          * Setup DMA descriptor area.
 361          */
 362         if (bus_dma_tag_create(bus_get_dma_tag(dev),    /* parent */
 363                                1, 0,                    /* alignment, bounds */
 364                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
 365                                BUS_SPACE_MAXADDR,       /* highaddr */
 366                                NULL, NULL,              /* filter, filterarg */
 367                                0x3ffff,                 /* maxsize */
 368                                UBS_MAX_SCATTER,         /* nsegments */
 369                                0xffff,                  /* maxsegsize */
 370                                BUS_DMA_ALLOCNOW,        /* flags */
 371                                NULL, NULL,              /* lockfunc, lockarg */
 372                                &sc->sc_dmat)) {
 373                 device_printf(dev, "cannot allocate DMA tag\n");
 374                 goto bad4;
 375         }
 376         SIMPLEQ_INIT(&sc->sc_freequeue);
 377         dmap = sc->sc_dmaa;
 378         for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
 379                 struct ubsec_q *q;
 380
 381                 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
 382                     M_DEVBUF, M_NOWAIT);
 383                 if (q == NULL) {
 384                         device_printf(dev, "cannot allocate queue buffers\n");
 385                         break;
 386                 }
 387
 388                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
 389                     &dmap->d_alloc, 0)) {
 390                         device_printf(dev, "cannot allocate dma buffers\n");
 391                         free(q, M_DEVBUF);
 392                         break;
 393                 }
 394                 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
 395
 396                 q->q_dma = dmap;
 397                 sc->sc_queuea[i] = q;
 398
 399                 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
 400         }
 401         mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev),
 402                 "mcr1 operations", MTX_DEF);
 403         mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev),
 404                 "mcr1 free q", MTX_DEF);
 405
 406         device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
 407
 408         crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
 409         crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
 410         crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
 411         crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
 412
 413         /*
 414          * Reset Broadcom chip
 415          */
 416         ubsec_reset_board(sc);
 417
 418         /*
 419          * Init Broadcom specific PCI settings
 420          */
 421         ubsec_init_pciregs(dev);
 422
 423         /*
 424          * Init Broadcom chip
 425          */
 426         ubsec_init_board(sc);
 427
 428 #ifndef UBSEC_NO_RNG
 429         if (sc->sc_flags & UBS_FLAGS_RNG) {
 430                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 431 #ifdef UBSEC_RNDTEST
 432                 sc->sc_rndtest = rndtest_attach(dev);
 433                 if (sc->sc_rndtest)
 434                         sc->sc_harvest = rndtest_harvest;
 435                 else
 436                         sc->sc_harvest = default_harvest;
 437 #else
 438                 sc->sc_harvest = default_harvest;
 439 #endif
 440
 441                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
 442                     &sc->sc_rng.rng_q.q_mcr, 0))
 443                         goto skip_rng;
 444
 445                 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
 446                     &sc->sc_rng.rng_q.q_ctx, 0)) {
 447                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 448                         goto skip_rng;
 449                 }
 450
 451                 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
 452                     UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
 453                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 454                         ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 455                         goto skip_rng;
 456                 }
 457
 458                 if (hz >= 100)
 459                         sc->sc_rnghz = hz / 100;
 460                 else
 461                         sc->sc_rnghz = 1;
 462                 callout_init(&sc->sc_rngto, 1);
 463                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
 464 skip_rng:
 465         ;
 466         }
 467 #endif /* UBSEC_NO_RNG */
 468         mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev),
 469                 "mcr2 operations", MTX_DEF);
 470
 471         if (sc->sc_flags & UBS_FLAGS_KEY) {
 472                 sc->sc_statmask |= BS_STAT_MCR2_DONE;
 473
 474                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
 475 #if 0
 476                 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
 477 #endif
 478         }
 479         return (0);
 480 bad4:
 481         crypto_unregister_all(sc->sc_cid);
 482 bad3:
 483         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 484 bad2:
 485         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 486 bad1:
 487         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 488 bad:
 489         return (ENXIO);
 490 }
 491
 492 /*
 493  * Detach a device that successfully probed.
 494  */
 495 static int
 496 ubsec_detach(device_t dev)
 497 {
 498         struct ubsec_softc *sc = device_get_softc(dev);
 499
 500         /* XXX wait/abort active ops */
 501
 502         /* disable interrupts */
 503         WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~
 504                 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR));
 505
 506         callout_stop(&sc->sc_rngto);
 507
 508         crypto_unregister_all(sc->sc_cid);
 509
 510 #ifdef UBSEC_RNDTEST
 511         if (sc->sc_rndtest)
 512                 rndtest_detach(sc->sc_rndtest);
 513 #endif
 514
 515         while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
 516                 struct ubsec_q *q;
 517
 518                 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
 519                 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
 520                 ubsec_dma_free(sc, &q->q_dma->d_alloc);
 521                 free(q, M_DEVBUF);
 522         }
 523         mtx_destroy(&sc->sc_mcr1lock);
 524         mtx_destroy(&sc->sc_freeqlock);
 525 #ifndef UBSEC_NO_RNG
 526         if (sc->sc_flags & UBS_FLAGS_RNG) {
 527                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
 528                 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
 529                 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
 530         }
 531 #endif /* UBSEC_NO_RNG */
 532         mtx_destroy(&sc->sc_mcr2lock);
 533
 534         bus_generic_detach(dev);
 535         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 536         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
 537
 538         bus_dma_tag_destroy(sc->sc_dmat);
 539         bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
 540
 541         return (0);
 542 }
 543
 544 /*
 545  * Stop all chip i/o so that the kernel's probe routines don't
 546  * get confused by errant DMAs when rebooting.
 547  */
 548 static int
 549 ubsec_shutdown(device_t dev)
 550 {
 551 #ifdef notyet
 552         ubsec_stop(device_get_softc(dev));
 553 #endif
 554         return (0);
 555 }
 556
 557 /*
 558  * Device suspend routine.
 559  */
 560 static int
 561 ubsec_suspend(device_t dev)
 562 {
 563         struct ubsec_softc *sc = device_get_softc(dev);
 564
 565 #ifdef notyet
 566         /* XXX stop the device and save PCI settings */
 567 #endif
 568         sc->sc_suspended = 1;
 569
 570         return (0);
 571 }
 572
 573 static int
 574 ubsec_resume(device_t dev)
 575 {
 576         struct ubsec_softc *sc = device_get_softc(dev);
 577
 578 #ifdef notyet
 579         /* XXX retore PCI settings and start the device */
 580 #endif
 581         sc->sc_suspended = 0;
 582         return (0);
 583 }
 584
 585 /*
 586  * UBSEC Interrupt routine
 587  */
 588 static void
 589 ubsec_intr(void *arg)
 590 {
 591         struct ubsec_softc *sc = arg;
 592         volatile u_int32_t stat;
 593         struct ubsec_q *q;
 594         struct ubsec_dma *dmap;
 595         int npkts = 0, i;
 596
 597         stat = READ_REG(sc, BS_STAT);
 598         stat &= sc->sc_statmask;
 599         if (stat == 0)
 600                 return;
 601
 602         WRITE_REG(sc, BS_STAT, stat);           /* IACK */
 603
 604         /*
 605          * Check to see if we have any packets waiting for us
 606          */
 607         if ((stat & BS_STAT_MCR1_DONE)) {
 608                 mtx_lock(&sc->sc_mcr1lock);
 609                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
 610                         q = SIMPLEQ_FIRST(&sc->sc_qchip);
 611                         dmap = q->q_dma;
 612
 613                         if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
 614                                 break;
 615
 616                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
 617
 618                         npkts = q->q_nstacked_mcrs;
 619                         sc->sc_nqchip -= 1+npkts;
 620                         /*
 621                          * search for further sc_qchip ubsec_q's that share
 622                          * the same MCR, and complete them too, they must be
 623                          * at the top.
 624                          */
 625                         for (i = 0; i < npkts; i++) {
 626                                 if(q->q_stacked_mcr[i]) {
 627                                         ubsec_callback(sc, q->q_stacked_mcr[i]);
 628                                 } else {
 629                                         break;
 630                                 }
 631                         }
 632                         ubsec_callback(sc, q);
 633                 }
 634                 /*
 635                  * Don't send any more packet to chip if there has been
 636                  * a DMAERR.
 637                  */
 638                 if (!(stat & BS_STAT_DMAERR))
 639                         ubsec_feed(sc);
 640                 mtx_unlock(&sc->sc_mcr1lock);
 641         }
 642
 643         /*
 644          * Check to see if we have any key setups/rng's waiting for us
 645          */
 646         if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
 647             (stat & BS_STAT_MCR2_DONE)) {
 648                 struct ubsec_q2 *q2;
 649                 struct ubsec_mcr *mcr;
 650
 651                 mtx_lock(&sc->sc_mcr2lock);
 652                 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
 653                         q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
 654
 655                         ubsec_dma_sync(&q2->q_mcr,
 656                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 657
 658                         mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
 659                         if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
 660                                 ubsec_dma_sync(&q2->q_mcr,
 661                                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 662                                 break;
 663                         }
 664                         SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
 665                         ubsec_callback2(sc, q2);
 666                         /*
 667                          * Don't send any more packet to chip if there has been
 668                          * a DMAERR.
 669                          */
 670                         if (!(stat & BS_STAT_DMAERR))
 671                                 ubsec_feed2(sc);
 672                 }
 673                 mtx_unlock(&sc->sc_mcr2lock);
 674         }
 675
 676         /*
 677          * Check to see if we got any DMA Error
 678          */
 679         if (stat & BS_STAT_DMAERR) {
 680 #ifdef UBSEC_DEBUG
 681                 if (ubsec_debug) {
 682                         volatile u_int32_t a = READ_REG(sc, BS_ERR);
 683
 684                         printf("dmaerr %s@%08x\n",
 685                             (a & BS_ERR_READ) ? "read" : "write",
 686                             a & BS_ERR_ADDR);
 687                 }
 688 #endif /* UBSEC_DEBUG */
 689                 ubsecstats.hst_dmaerr++;
 690                 mtx_lock(&sc->sc_mcr1lock);
 691                 ubsec_totalreset(sc);
 692                 ubsec_feed(sc);
 693                 mtx_unlock(&sc->sc_mcr1lock);
 694         }
 695
 696         if (sc->sc_needwakeup) {                /* XXX check high watermark */
 697                 int wakeup;
 698
 699                 mtx_lock(&sc->sc_freeqlock);
 700                 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
 701 #ifdef UBSEC_DEBUG
 702                 if (ubsec_debug)
 703                         device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
 704                                 sc->sc_needwakeup);
 705 #endif /* UBSEC_DEBUG */
 706                 sc->sc_needwakeup &= ~wakeup;
 707                 mtx_unlock(&sc->sc_freeqlock);
 708                 crypto_unblock(sc->sc_cid, wakeup);
 709         }
 710 }
 711
 712 /*
 713  * ubsec_feed() - aggregate and post requests to chip
 714  */
 715 static void
 716 ubsec_feed(struct ubsec_softc *sc)
 717 {
 718         struct ubsec_q *q, *q2;
 719         int npkts, i;
 720         void *v;
 721         u_int32_t stat;
 722
 723         /*
 724          * Decide how many ops to combine in a single MCR.  We cannot
 725          * aggregate more than UBS_MAX_AGGR because this is the number
 726          * of slots defined in the data structure.  Note that
 727          * aggregation only happens if ops are marked batch'able.
 728          * Aggregating ops reduces the number of interrupts to the host
 729          * but also (potentially) increases the latency for processing
 730          * completed ops as we only get an interrupt when all aggregated
 731          * ops have completed.
 732          */
 733         if (sc->sc_nqueue == 0)
 734                 return;
 735         if (sc->sc_nqueue > 1) {
 736                 npkts = 0;
 737                 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
 738                         npkts++;
 739                         if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
 740                                 break;
 741                 }
 742         } else
 743                 npkts = 1;
 744         /*
 745          * Check device status before going any further.
 746          */
 747         if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
 748                 if (stat & BS_STAT_DMAERR) {
 749                         ubsec_totalreset(sc);
 750                         ubsecstats.hst_dmaerr++;
 751                 } else
 752                         ubsecstats.hst_mcr1full++;
 753                 return;
 754         }
 755         if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
 756                 ubsecstats.hst_maxqueue = sc->sc_nqueue;
 757         if (npkts > UBS_MAX_AGGR)
 758                 npkts = UBS_MAX_AGGR;
 759         if (npkts < 2)                          /* special case 1 op */
 760                 goto feed1;
 761
 762         ubsecstats.hst_totbatch += npkts-1;
 763 #ifdef UBSEC_DEBUG
 764         if (ubsec_debug)
 765                 printf("merging %d records\n", npkts);
 766 #endif /* UBSEC_DEBUG */
 767
 768         q = SIMPLEQ_FIRST(&sc->sc_queue);
 769         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
 770         --sc->sc_nqueue;
 771
 772         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 773         if (q->q_dst_map != NULL)
 774                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 775
 776         q->q_nstacked_mcrs = npkts - 1;         /* Number of packets stacked */
 777
 778         for (i = 0; i < q->q_nstacked_mcrs; i++) {
 779                 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
 780                 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
 781                     BUS_DMASYNC_PREWRITE);
 782                 if (q2->q_dst_map != NULL)
 783                         bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
 784                             BUS_DMASYNC_PREREAD);
 785                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
 786                 --sc->sc_nqueue;
 787
 788                 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
 789                     sizeof(struct ubsec_mcr_add));
 790                 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
 791                 q->q_stacked_mcr[i] = q2;
 792         }
 793         q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
 794         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 795         sc->sc_nqchip += npkts;
 796         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 797                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 798         ubsec_dma_sync(&q->q_dma->d_alloc,
 799             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 800         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 801             offsetof(struct ubsec_dmachunk, d_mcr));
 802         return;
 803 feed1:
 804         q = SIMPLEQ_FIRST(&sc->sc_queue);
 805
 806         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
 807         if (q->q_dst_map != NULL)
 808                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
 809         ubsec_dma_sync(&q->q_dma->d_alloc,
 810             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 811
 812         WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
 813             offsetof(struct ubsec_dmachunk, d_mcr));
 814 #ifdef UBSEC_DEBUG
 815         if (ubsec_debug)
 816                 printf("feed1: q->chip %p %08x stat %08x\n",
 817                       q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
 818                       stat);
 819 #endif /* UBSEC_DEBUG */
 820         SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
 821         --sc->sc_nqueue;
 822         SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
 823         sc->sc_nqchip++;
 824         if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
 825                 ubsecstats.hst_maxqchip = sc->sc_nqchip;
 826         return;
 827 }
 828
 829 static void
 830 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
 831 {
 832
 833         /* Go ahead and compute key in ubsec's byte order */
 834         if (algo == CRYPTO_DES_CBC) {
 835                 bcopy(key, &ses->ses_deskey[0], 8);
 836                 bcopy(key, &ses->ses_deskey[2], 8);
 837                 bcopy(key, &ses->ses_deskey[4], 8);
 838         } else
 839                 bcopy(key, ses->ses_deskey, 24);
 840
 841         SWAP32(ses->ses_deskey[0]);
 842         SWAP32(ses->ses_deskey[1]);
 843         SWAP32(ses->ses_deskey[2]);
 844         SWAP32(ses->ses_deskey[3]);
 845         SWAP32(ses->ses_deskey[4]);
 846         SWAP32(ses->ses_deskey[5]);
 847 }
 848
 849 static void
 850 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
 851 {
 852         MD5_CTX md5ctx;
 853         SHA1_CTX sha1ctx;
 854         int i;
 855
 856         for (i = 0; i < klen; i++)
 857                 key[i] ^= HMAC_IPAD_VAL;
 858
 859         if (algo == CRYPTO_MD5_HMAC) {
 860                 MD5Init(&md5ctx);
 861                 MD5Update(&md5ctx, key, klen);
 862                 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 863                 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
 864         } else {
 865                 SHA1Init(&sha1ctx);
 866                 SHA1Update(&sha1ctx, key, klen);
 867                 SHA1Update(&sha1ctx, hmac_ipad_buffer,
 868                     SHA1_HMAC_BLOCK_LEN - klen);
 869                 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
 870         }
 871
 872         for (i = 0; i < klen; i++)
 873                 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
 874
 875         if (algo == CRYPTO_MD5_HMAC) {
 876                 MD5Init(&md5ctx);
 877                 MD5Update(&md5ctx, key, klen);
 878                 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
 879                 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
 880         } else {
 881                 SHA1Init(&sha1ctx);
 882                 SHA1Update(&sha1ctx, key, klen);
 883                 SHA1Update(&sha1ctx, hmac_opad_buffer,
 884                     SHA1_HMAC_BLOCK_LEN - klen);
 885                 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
 886         }
 887
 888         for (i = 0; i < klen; i++)
 889                 key[i] ^= HMAC_OPAD_VAL;
 890 }
 891
 892 /*
 893  * Allocate a new 'session' and return an encoded session id.  'sidp'
 894  * contains our registration id, and should contain an encoded session
 895  * id on successful allocation.
 896  */
 897 static int
 898 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
 899 {
 900         struct ubsec_softc *sc = device_get_softc(dev);
 901         struct cryptoini *c, *encini = NULL, *macini = NULL;
 902         struct ubsec_session *ses = NULL;
 903         int sesn;
 904
 905         if (sidp == NULL || cri == NULL || sc == NULL)
 906                 return (EINVAL);
 907
 908         for (c = cri; c != NULL; c = c->cri_next) {
 909                 if (c->cri_alg == CRYPTO_MD5_HMAC ||
 910                     c->cri_alg == CRYPTO_SHA1_HMAC) {
 911                         if (macini)
 912                                 return (EINVAL);
 913                         macini = c;
 914                 } else if (c->cri_alg == CRYPTO_DES_CBC ||
 915                     c->cri_alg == CRYPTO_3DES_CBC) {
 916                         if (encini)
 917                                 return (EINVAL);
 918                         encini = c;
 919                 } else
 920                         return (EINVAL);
 921         }
 922         if (encini == NULL && macini == NULL)
 923                 return (EINVAL);
 924
 925         if (sc->sc_sessions == NULL) {
 926                 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
 927                     sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 928                 if (ses == NULL)
 929                         return (ENOMEM);
 930                 sesn = 0;
 931                 sc->sc_nsessions = 1;
 932         } else {
 933                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
 934                         if (sc->sc_sessions[sesn].ses_used == 0) {
 935                                 ses = &sc->sc_sessions[sesn];
 936                                 break;
 937                         }
 938                 }
 939
 940                 if (ses == NULL) {
 941                         sesn = sc->sc_nsessions;
 942                         ses = (struct ubsec_session *)malloc((sesn + 1) *
 943                             sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
 944                         if (ses == NULL)
 945                                 return (ENOMEM);
 946                         bcopy(sc->sc_sessions, ses, sesn *
 947                             sizeof(struct ubsec_session));
 948                         bzero(sc->sc_sessions, sesn *
 949                             sizeof(struct ubsec_session));
 950                         free(sc->sc_sessions, M_DEVBUF);
 951                         sc->sc_sessions = ses;
 952                         ses = &sc->sc_sessions[sesn];
 953                         sc->sc_nsessions++;
 954                 }
 955         }
 956         bzero(ses, sizeof(struct ubsec_session));
 957         ses->ses_used = 1;
 958
 959         if (encini) {
 960                 /* get an IV, network byte order */
 961                 /* XXX may read fewer than requested */
 962                 read_random(ses->ses_iv, sizeof(ses->ses_iv));
 963
 964                 if (encini->cri_key != NULL) {
 965                         ubsec_setup_enckey(ses, encini->cri_alg,
 966                             encini->cri_key);
 967                 }
 968         }
 969
 970         if (macini) {
 971                 ses->ses_mlen = macini->cri_mlen;
 972                 if (ses->ses_mlen == 0) {
 973                         if (macini->cri_alg == CRYPTO_MD5_HMAC)
 974                                 ses->ses_mlen = MD5_HASH_LEN;
 975                         else
 976                                 ses->ses_mlen = SHA1_HASH_LEN;
 977                 }
 978
 979                 if (macini->cri_key != NULL) {
 980                         ubsec_setup_mackey(ses, macini->cri_alg,
 981                             macini->cri_key, macini->cri_klen / 8);
 982                 }
 983         }
 984
 985         *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
 986         return (0);
 987 }
 988
 989 /*
 990  * Deallocate a session.
 991  */
 992 static int
 993 ubsec_freesession(device_t dev, u_int64_t tid)
 994 {
 995         struct ubsec_softc *sc = device_get_softc(dev);
 996         int session, ret;
 997         u_int32_t sid = CRYPTO_SESID2LID(tid);
 998
 999         if (sc == NULL)
1000                 return (EINVAL);
1001
1002         session = UBSEC_SESSION(sid);
1003         if (session < sc->sc_nsessions) {
1004                 bzero(&sc->sc_sessions[session],
1005                         sizeof(sc->sc_sessions[session]));
1006                 ret = 0;
1007         } else
1008                 ret = EINVAL;
1009
1010         return (ret);
1011 }
1012
1013 static void
1014 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1015 {
1016         struct ubsec_operand *op = arg;
1017
1018         KASSERT(nsegs <= UBS_MAX_SCATTER,
1019                 ("Too many DMA segments returned when mapping operand"));
1020 #ifdef UBSEC_DEBUG
1021         if (ubsec_debug)
1022                 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1023                         (u_int) mapsize, nsegs, error);
1024 #endif
1025         if (error != 0)
1026                 return;
1027         op->mapsize = mapsize;
1028         op->nsegs = nsegs;
1029         bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1030 }
1031
1032 static int
1033 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1034 {
1035         struct ubsec_softc *sc = device_get_softc(dev);
1036         struct ubsec_q *q = NULL;
1037         int err = 0, i, j, nicealign;
1038         struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1039         int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1040         int sskip, dskip, stheend, dtheend;
1041         int16_t coffset;
1042         struct ubsec_session *ses;
1043         struct ubsec_pktctx ctx;
1044         struct ubsec_dma *dmap = NULL;
1045
1046         if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1047                 ubsecstats.hst_invalid++;
1048                 return (EINVAL);
1049         }
1050         if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1051                 ubsecstats.hst_badsession++;
1052                 return (EINVAL);
1053         }
1054
1055         mtx_lock(&sc->sc_freeqlock);
1056         if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1057                 ubsecstats.hst_queuefull++;
1058                 sc->sc_needwakeup |= CRYPTO_SYMQ;
1059                 mtx_unlock(&sc->sc_freeqlock);
1060                 return (ERESTART);
1061         }
1062         q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1063         SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1064         mtx_unlock(&sc->sc_freeqlock);
1065
1066         dmap = q->q_dma; /* Save dma pointer */
1067         bzero(q, sizeof(struct ubsec_q));
1068         bzero(&ctx, sizeof(ctx));
1069
1070         q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1071         q->q_dma = dmap;
1072         ses = &sc->sc_sessions[q->q_sesn];
1073
1074         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1075                 q->q_src_m = (struct mbuf *)crp->crp_buf;
1076                 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1077         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1078                 q->q_src_io = (struct uio *)crp->crp_buf;
1079                 q->q_dst_io = (struct uio *)crp->crp_buf;
1080         } else {
1081                 ubsecstats.hst_badflags++;
1082                 err = EINVAL;
1083                 goto errout;    /* XXX we don't handle contiguous blocks! */
1084         }
1085
1086         bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1087
1088         dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1089         dmap->d_dma->d_mcr.mcr_flags = 0;
1090         q->q_crp = crp;
1091
1092         crd1 = crp->crp_desc;
1093         if (crd1 == NULL) {
1094                 ubsecstats.hst_nodesc++;
1095                 err = EINVAL;
1096                 goto errout;
1097         }
1098         crd2 = crd1->crd_next;
1099
1100         if (crd2 == NULL) {
1101                 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1102                     crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1103                         maccrd = crd1;
1104                         enccrd = NULL;
1105                 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1106                     crd1->crd_alg == CRYPTO_3DES_CBC) {
1107                         maccrd = NULL;
1108                         enccrd = crd1;
1109                 } else {
1110                         ubsecstats.hst_badalg++;
1111                         err = EINVAL;
1112                         goto errout;
1113                 }
1114         } else {
1115                 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1116                     crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1117                     (crd2->crd_alg == CRYPTO_DES_CBC ||
1118                         crd2->crd_alg == CRYPTO_3DES_CBC) &&
1119                     ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1120                         maccrd = crd1;
1121                         enccrd = crd2;
1122                 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1123                     crd1->crd_alg == CRYPTO_3DES_CBC) &&
1124                     (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1125                         crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1126                     (crd1->crd_flags & CRD_F_ENCRYPT)) {
1127                         enccrd = crd1;
1128                         maccrd = crd2;
1129                 } else {
1130                         /*
1131                          * We cannot order the ubsec as requested
1132                          */
1133                         ubsecstats.hst_badalg++;
1134                         err = EINVAL;
1135                         goto errout;
1136                 }
1137         }
1138
1139         if (enccrd) {
1140                 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1141                         ubsec_setup_enckey(ses, enccrd->crd_alg,
1142                             enccrd->crd_key);
1143                 }
1144
1145                 encoffset = enccrd->crd_skip;
1146                 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1147
1148                 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1149                         q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1150
1151                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1152                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1153                         else {
1154                                 ctx.pc_iv[0] = ses->ses_iv[0];
1155                                 ctx.pc_iv[1] = ses->ses_iv[1];
1156                         }
1157
1158                         if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1159                                 crypto_copyback(crp->crp_flags, crp->crp_buf,
1160                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1161                         }
1162                 } else {
1163                         ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1164
1165                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1166                                 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1167                         else {
1168                                 crypto_copydata(crp->crp_flags, crp->crp_buf,
1169                                     enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1170                         }
1171                 }
1172
1173                 ctx.pc_deskey[0] = ses->ses_deskey[0];
1174                 ctx.pc_deskey[1] = ses->ses_deskey[1];
1175                 ctx.pc_deskey[2] = ses->ses_deskey[2];
1176                 ctx.pc_deskey[3] = ses->ses_deskey[3];
1177                 ctx.pc_deskey[4] = ses->ses_deskey[4];
1178                 ctx.pc_deskey[5] = ses->ses_deskey[5];
1179                 SWAP32(ctx.pc_iv[0]);
1180                 SWAP32(ctx.pc_iv[1]);
1181         }
1182
1183         if (maccrd) {
1184                 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1185                         ubsec_setup_mackey(ses, maccrd->crd_alg,
1186                             maccrd->crd_key, maccrd->crd_klen / 8);
1187                 }
1188
1189                 macoffset = maccrd->crd_skip;
1190
1191                 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1192                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1193                 else
1194                         ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1195
1196                 for (i = 0; i < 5; i++) {
1197                         ctx.pc_hminner[i] = ses->ses_hminner[i];
1198                         ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1199
1200                         HTOLE32(ctx.pc_hminner[i]);
1201                         HTOLE32(ctx.pc_hmouter[i]);
1202                 }
1203         }
1204
1205         if (enccrd && maccrd) {
1206                 /*
1207                  * ubsec cannot handle packets where the end of encryption
1208                  * and authentication are not the same, or where the
1209                  * encrypted part begins before the authenticated part.
1210                  */
1211                 if ((encoffset + enccrd->crd_len) !=
1212                     (macoffset + maccrd->crd_len)) {
1213                         ubsecstats.hst_lenmismatch++;
1214                         err = EINVAL;
1215                         goto errout;
1216                 }
1217                 if (enccrd->crd_skip < maccrd->crd_skip) {
1218                         ubsecstats.hst_skipmismatch++;
1219                         err = EINVAL;
1220                         goto errout;
1221                 }
1222                 sskip = maccrd->crd_skip;
1223                 cpskip = dskip = enccrd->crd_skip;
1224                 stheend = maccrd->crd_len;
1225                 dtheend = enccrd->crd_len;
1226                 coffset = enccrd->crd_skip - maccrd->crd_skip;
1227                 cpoffset = cpskip + dtheend;
1228 #ifdef UBSEC_DEBUG
1229                 if (ubsec_debug) {
1230                         printf("mac: skip %d, len %d, inject %d\n",
1231                             maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1232                         printf("enc: skip %d, len %d, inject %d\n",
1233                             enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1234                         printf("src: skip %d, len %d\n", sskip, stheend);
1235                         printf("dst: skip %d, len %d\n", dskip, dtheend);
1236                         printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1237                             coffset, stheend, cpskip, cpoffset);
1238                 }
1239 #endif
1240         } else {
1241                 cpskip = dskip = sskip = macoffset + encoffset;
1242                 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1243                 cpoffset = cpskip + dtheend;
1244                 coffset = 0;
1245         }
1246         ctx.pc_offset = htole16(coffset >> 2);
1247
1248         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1249                 ubsecstats.hst_nomap++;
1250                 err = ENOMEM;
1251                 goto errout;
1252         }
1253         if (crp->crp_flags & CRYPTO_F_IMBUF) {
1254                 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1255                     q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1256                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1257                         q->q_src_map = NULL;
1258                         ubsecstats.hst_noload++;
1259                         err = ENOMEM;
1260                         goto errout;
1261                 }
1262         } else if (crp->crp_flags & CRYPTO_F_IOV) {
1263                 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1264                     q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1265                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1266                         q->q_src_map = NULL;
1267                         ubsecstats.hst_noload++;
1268                         err = ENOMEM;
1269                         goto errout;
1270                 }
1271         }
1272         nicealign = ubsec_dmamap_aligned(&q->q_src);
1273
1274         dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1275
1276 #ifdef UBSEC_DEBUG
1277         if (ubsec_debug)
1278                 printf("src skip: %d nicealign: %u\n", sskip, nicealign);
1279 #endif
1280         for (i = j = 0; i < q->q_src_nsegs; i++) {
1281                 struct ubsec_pktbuf *pb;
1282                 bus_size_t packl = q->q_src_segs[i].ds_len;
1283                 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1284
1285                 if (sskip >= packl) {
1286                         sskip -= packl;
1287                         continue;
1288                 }
1289
1290                 packl -= sskip;
1291                 packp += sskip;
1292                 sskip = 0;
1293
1294                 if (packl > 0xfffc) {
1295                         err = EIO;
1296                         goto errout;
1297                 }
1298
1299                 if (j == 0)
1300                         pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1301                 else
1302                         pb = &dmap->d_dma->d_sbuf[j - 1];
1303
1304                 pb->pb_addr = htole32(packp);
1305
1306                 if (stheend) {
1307                         if (packl > stheend) {
1308                                 pb->pb_len = htole32(stheend);
1309                                 stheend = 0;
1310                         } else {
1311                                 pb->pb_len = htole32(packl);
1312                                 stheend -= packl;
1313                         }
1314                 } else
1315                         pb->pb_len = htole32(packl);
1316
1317                 if ((i + 1) == q->q_src_nsegs)
1318                         pb->pb_next = 0;
1319                 else
1320                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1321                             offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1322                 j++;
1323         }
1324
1325         if (enccrd == NULL && maccrd != NULL) {
1326                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1327                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1328                 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1329                     offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1330 #ifdef UBSEC_DEBUG
1331                 if (ubsec_debug)
1332                         printf("opkt: %x %x %x\n",
1333                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1334                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1335                             dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1336 #endif
1337         } else {
1338                 if (crp->crp_flags & CRYPTO_F_IOV) {
1339                         if (!nicealign) {
1340                                 ubsecstats.hst_iovmisaligned++;
1341                                 err = EINVAL;
1342                                 goto errout;
1343                         }
1344                         if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1345                              &q->q_dst_map)) {
1346                                 ubsecstats.hst_nomap++;
1347                                 err = ENOMEM;
1348                                 goto errout;
1349                         }
1350                         if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1351                             q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1352                                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1353                                 q->q_dst_map = NULL;
1354                                 ubsecstats.hst_noload++;
1355                                 err = ENOMEM;
1356                                 goto errout;
1357                         }
1358                 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1359                         if (nicealign) {
1360                                 q->q_dst = q->q_src;
1361                         } else {
1362                                 int totlen, len;
1363                                 struct mbuf *m, *top, **mp;
1364
1365                                 ubsecstats.hst_unaligned++;
1366                                 totlen = q->q_src_mapsize;
1367                                 if (totlen >= MINCLSIZE) {
1368                                         m = m_getcl(M_NOWAIT, MT_DATA,
1369                                             q->q_src_m->m_flags & M_PKTHDR);
1370                                         len = MCLBYTES;
1371                                 } else if (q->q_src_m->m_flags & M_PKTHDR) {
1372                                         m = m_gethdr(M_NOWAIT, MT_DATA);
1373                                         len = MHLEN;
1374                                 } else {
1375                                         m = m_get(M_NOWAIT, MT_DATA);
1376                                         len = MLEN;
1377                                 }
1378                                 if (m && q->q_src_m->m_flags & M_PKTHDR &&
1379                                     !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) {
1380                                         m_free(m);
1381                                         m = NULL;
1382                                 }
1383                                 if (m == NULL) {
1384                                         ubsecstats.hst_nombuf++;
1385                                         err = sc->sc_nqueue ? ERESTART : ENOMEM;
1386                                         goto errout;
1387                                 }
1388                                 m->m_len = len = min(totlen, len);
1389                                 totlen -= len;
1390                                 top = m;
1391                                 mp = &top;
1392
1393                                 while (totlen > 0) {
1394                                         if (totlen >= MINCLSIZE) {
1395                                                 m = m_getcl(M_NOWAIT,
1396                                                     MT_DATA, 0);
1397                                                 len = MCLBYTES;
1398                                         } else {
1399                                                 m = m_get(M_NOWAIT, MT_DATA);
1400                                                 len = MLEN;
1401                                         }
1402                                         if (m == NULL) {
1403                                                 m_freem(top);
1404                                                 ubsecstats.hst_nombuf++;
1405                                                 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1406                                                 goto errout;
1407                                         }
1408                                         m->m_len = len = min(totlen, len);
1409                                         totlen -= len;
1410                                         *mp = m;
1411                                         mp = &m->m_next;
1412                                 }
1413                                 q->q_dst_m = top;
1414                                 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1415                                     cpskip, cpoffset);
1416                                 if (bus_dmamap_create(sc->sc_dmat,
1417                                     BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1418                                         ubsecstats.hst_nomap++;
1419                                         err = ENOMEM;
1420                                         goto errout;
1421                                 }
1422                                 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1423                                     q->q_dst_map, q->q_dst_m,
1424                                     ubsec_op_cb, &q->q_dst,
1425                                     BUS_DMA_NOWAIT) != 0) {
1426                                         bus_dmamap_destroy(sc->sc_dmat,
1427                                         q->q_dst_map);
1428                                         q->q_dst_map = NULL;
1429                                         ubsecstats.hst_noload++;
1430                                         err = ENOMEM;
1431                                         goto errout;
1432                                 }
1433                         }
1434                 } else {
1435                         ubsecstats.hst_badflags++;
1436                         err = EINVAL;
1437                         goto errout;
1438                 }
1439
1440 #ifdef UBSEC_DEBUG
1441                 if (ubsec_debug)
1442                         printf("dst skip: %d\n", dskip);
1443 #endif
1444                 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1445                         struct ubsec_pktbuf *pb;
1446                         bus_size_t packl = q->q_dst_segs[i].ds_len;
1447                         bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1448
1449                         if (dskip >= packl) {
1450                                 dskip -= packl;
1451                                 continue;
1452                         }
1453
1454                         packl -= dskip;
1455                         packp += dskip;
1456                         dskip = 0;
1457
1458                         if (packl > 0xfffc) {
1459                                 err = EIO;
1460                                 goto errout;
1461                         }
1462
1463                         if (j == 0)
1464                                 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1465                         else
1466                                 pb = &dmap->d_dma->d_dbuf[j - 1];
1467
1468                         pb->pb_addr = htole32(packp);
1469
1470                         if (dtheend) {
1471                                 if (packl > dtheend) {
1472                                         pb->pb_len = htole32(dtheend);
1473                                         dtheend = 0;
1474                                 } else {
1475                                         pb->pb_len = htole32(packl);
1476                                         dtheend -= packl;
1477                                 }
1478                         } else
1479                                 pb->pb_len = htole32(packl);
1480
1481                         if ((i + 1) == q->q_dst_nsegs) {
1482                                 if (maccrd)
1483                                         pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1484                                             offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1485                                 else
1486                                         pb->pb_next = 0;
1487                         } else
1488                                 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1489                                     offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1490                         j++;
1491                 }
1492         }
1493
1494         dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1495             offsetof(struct ubsec_dmachunk, d_ctx));
1496
1497         if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1498                 struct ubsec_pktctx_long *ctxl;
1499
1500                 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1501                     offsetof(struct ubsec_dmachunk, d_ctx));
1502
1503                 /* transform small context into long context */
1504                 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1505                 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1506                 ctxl->pc_flags = ctx.pc_flags;
1507                 ctxl->pc_offset = ctx.pc_offset;
1508                 for (i = 0; i < 6; i++)
1509                         ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1510                 for (i = 0; i < 5; i++)
1511                         ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1512                 for (i = 0; i < 5; i++)
1513                         ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1514                 ctxl->pc_iv[0] = ctx.pc_iv[0];
1515                 ctxl->pc_iv[1] = ctx.pc_iv[1];
1516         } else
1517                 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1518                     offsetof(struct ubsec_dmachunk, d_ctx),
1519                     sizeof(struct ubsec_pktctx));
1520
1521         mtx_lock(&sc->sc_mcr1lock);
1522         SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1523         sc->sc_nqueue++;
1524         ubsecstats.hst_ipackets++;
1525         ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1526         if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1527                 ubsec_feed(sc);
1528         mtx_unlock(&sc->sc_mcr1lock);
1529         return (0);
1530
1531 errout:
1532         if (q != NULL) {
1533                 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1534                         m_freem(q->q_dst_m);
1535
1536                 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1537                         bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1538                         bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1539                 }
1540                 if (q->q_src_map != NULL) {
1541                         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1542                         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1543                 }
1544         }
1545         if (q != NULL || err == ERESTART) {
1546                 mtx_lock(&sc->sc_freeqlock);
1547                 if (q != NULL)
1548                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1549                 if (err == ERESTART)
1550                         sc->sc_needwakeup |= CRYPTO_SYMQ;
1551                 mtx_unlock(&sc->sc_freeqlock);
1552         }
1553         if (err != ERESTART) {
1554                 crp->crp_etype = err;
1555                 crypto_done(crp);
1556         }
1557         return (err);
1558 }
1559
1560 static void
1561 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1562 {
1563         struct cryptop *crp = (struct cryptop *)q->q_crp;
1564         struct cryptodesc *crd;
1565         struct ubsec_dma *dmap = q->q_dma;
1566
1567         ubsecstats.hst_opackets++;
1568         ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1569
1570         ubsec_dma_sync(&dmap->d_alloc,
1571             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1572         if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1573                 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1574                     BUS_DMASYNC_POSTREAD);
1575                 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1576                 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1577         }
1578         bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1579         bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1580         bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1581
1582         if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1583                 m_freem(q->q_src_m);
1584                 crp->crp_buf = (caddr_t)q->q_dst_m;
1585         }
1586
1587         /* copy out IV for future use */
1588         if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1589                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1590                         if (crd->crd_alg != CRYPTO_DES_CBC &&
1591                             crd->crd_alg != CRYPTO_3DES_CBC)
1592                                 continue;
1593                         crypto_copydata(crp->crp_flags, crp->crp_buf,
1594                             crd->crd_skip + crd->crd_len - 8, 8,
1595                             (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1596                         break;
1597                 }
1598         }
1599
1600         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1601                 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1602                     crd->crd_alg != CRYPTO_SHA1_HMAC)
1603                         continue;
1604                 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1605                     sc->sc_sessions[q->q_sesn].ses_mlen,
1606                     (caddr_t)dmap->d_dma->d_macbuf);
1607                 break;
1608         }
1609         mtx_lock(&sc->sc_freeqlock);
1610         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1611         mtx_unlock(&sc->sc_freeqlock);
1612         crypto_done(crp);
1613 }
1614
1615 static void
1616 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1617 {
1618         int i, j, dlen, slen;
1619         caddr_t dptr, sptr;
1620
1621         j = 0;
1622         sptr = srcm->m_data;
1623         slen = srcm->m_len;
1624         dptr = dstm->m_data;
1625         dlen = dstm->m_len;
1626
1627         while (1) {
1628                 for (i = 0; i < min(slen, dlen); i++) {
1629                         if (j < hoffset || j >= toffset)
1630                                 *dptr++ = *sptr++;
1631                         slen--;
1632                         dlen--;
1633                         j++;
1634                 }
1635                 if (slen == 0) {
1636                         srcm = srcm->m_next;
1637                         if (srcm == NULL)
1638                                 return;
1639                         sptr = srcm->m_data;
1640                         slen = srcm->m_len;
1641                 }
1642                 if (dlen == 0) {
1643                         dstm = dstm->m_next;
1644                         if (dstm == NULL)
1645                                 return;
1646                         dptr = dstm->m_data;
1647                         dlen = dstm->m_len;
1648                 }
1649         }
1650 }
1651
1652 /*
1653  * feed the key generator, must be called at splimp() or higher.
1654  */
1655 static int
1656 ubsec_feed2(struct ubsec_softc *sc)
1657 {
1658         struct ubsec_q2 *q;
1659
1660         while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1661                 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1662                         break;
1663                 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1664
1665                 ubsec_dma_sync(&q->q_mcr,
1666                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1667                 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1668
1669                 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1670                 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1671                 --sc->sc_nqueue2;
1672                 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1673         }
1674         return (0);
1675 }
1676
1677 /*
1678  * Callback for handling random numbers
1679  */
1680 static void
1681 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1682 {
1683         struct cryptkop *krp;
1684         struct ubsec_ctx_keyop *ctx;
1685
1686         ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1687         ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1688
1689         switch (q->q_type) {
1690 #ifndef UBSEC_NO_RNG
1691         case UBS_CTXOP_RNGBYPASS: {
1692                 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1693
1694                 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1695                 (*sc->sc_harvest)(sc->sc_rndtest,
1696                         rng->rng_buf.dma_vaddr,
1697                         UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1698                 rng->rng_used = 0;
1699                 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1700                 break;
1701         }
1702 #endif
1703         case UBS_CTXOP_MODEXP: {
1704                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1705                 u_int rlen, clen;
1706
1707                 krp = me->me_krp;
1708                 rlen = (me->me_modbits + 7) / 8;
1709                 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1710
1711                 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1712                 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1713                 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1714                 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1715
1716                 if (clen < rlen)
1717                         krp->krp_status = E2BIG;
1718                 else {
1719                         if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1720                                 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1721                                     (krp->krp_param[krp->krp_iparams].crp_nbits
1722                                         + 7) / 8);
1723                                 bcopy(me->me_C.dma_vaddr,
1724                                     krp->krp_param[krp->krp_iparams].crp_p,
1725                                     (me->me_modbits + 7) / 8);
1726                         } else
1727                                 ubsec_kshift_l(me->me_shiftbits,
1728                                     me->me_C.dma_vaddr, me->me_normbits,
1729                                     krp->krp_param[krp->krp_iparams].crp_p,
1730                                     krp->krp_param[krp->krp_iparams].crp_nbits);
1731                 }
1732
1733                 crypto_kdone(krp);
1734
1735                 /* bzero all potentially sensitive data */
1736                 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1737                 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1738                 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1739                 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1740
1741                 /* Can't free here, so put us on the free list. */
1742                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1743                 break;
1744         }
1745         case UBS_CTXOP_RSAPRIV: {
1746                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1747                 u_int len;
1748
1749                 krp = rp->rpr_krp;
1750                 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1751                 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1752
1753                 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1754                 bcopy(rp->rpr_msgout.dma_vaddr,
1755                     krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1756
1757                 crypto_kdone(krp);
1758
1759                 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1760                 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1761                 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1762
1763                 /* Can't free here, so put us on the free list. */
1764                 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1765                 break;
1766         }
1767         default:
1768                 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1769                     letoh16(ctx->ctx_op));
1770                 break;
1771         }
1772 }
1773
1774 #ifndef UBSEC_NO_RNG
1775 static void
1776 ubsec_rng(void *vsc)
1777 {
1778         struct ubsec_softc *sc = vsc;
1779         struct ubsec_q2_rng *rng = &sc->sc_rng;
1780         struct ubsec_mcr *mcr;
1781         struct ubsec_ctx_rngbypass *ctx;
1782
1783         mtx_lock(&sc->sc_mcr2lock);
1784         if (rng->rng_used) {
1785                 mtx_unlock(&sc->sc_mcr2lock);
1786                 return;
1787         }
1788         sc->sc_nqueue2++;
1789         if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1790                 goto out;
1791
1792         mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1793         ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1794
1795         mcr->mcr_pkts = htole16(1);
1796         mcr->mcr_flags = 0;
1797         mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1798         mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1799         mcr->mcr_ipktbuf.pb_len = 0;
1800         mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1801         mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1802         mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1803             UBS_PKTBUF_LEN);
1804         mcr->mcr_opktbuf.pb_next = 0;
1805
1806         ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1807         ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1808         rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1809
1810         ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1811
1812         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1813         rng->rng_used = 1;
1814         ubsec_feed2(sc);
1815         ubsecstats.hst_rng++;
1816         mtx_unlock(&sc->sc_mcr2lock);
1817
1818         return;
1819
1820 out:
1821         /*
1822          * Something weird happened, generate our own call back.
1823          */
1824         sc->sc_nqueue2--;
1825         mtx_unlock(&sc->sc_mcr2lock);
1826         callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1827 }
1828 #endif /* UBSEC_NO_RNG */
1829
1830 static void
1831 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1832 {
1833         bus_addr_t *paddr = (bus_addr_t*) arg;
1834         *paddr = segs->ds_addr;
1835 }
1836
1837 static int
1838 ubsec_dma_malloc(
1839         struct ubsec_softc *sc,
1840         bus_size_t size,
1841         struct ubsec_dma_alloc *dma,
1842         int mapflags
1843 )
1844 {
1845         int r;
1846
1847         /* XXX could specify sc_dmat as parent but that just adds overhead */
1848         r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),     /* parent */
1849                                1, 0,                    /* alignment, bounds */
1850                                BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1851                                BUS_SPACE_MAXADDR,       /* highaddr */
1852                                NULL, NULL,              /* filter, filterarg */
1853                                size,                    /* maxsize */
1854                                1,                       /* nsegments */
1855                                size,                    /* maxsegsize */
1856                                BUS_DMA_ALLOCNOW,        /* flags */
1857                                NULL, NULL,              /* lockfunc, lockarg */
1858                                &dma->dma_tag);
1859         if (r != 0) {
1860                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1861                         "bus_dma_tag_create failed; error %u\n", r);
1862                 goto fail_1;
1863         }
1864
1865         r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1866                              BUS_DMA_NOWAIT, &dma->dma_map);
1867         if (r != 0) {
1868                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1869                         "bus_dmammem_alloc failed; size %ju, error %u\n",
1870                         (intmax_t)size, r);
1871                 goto fail_2;
1872         }
1873
1874         r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1875                             size,
1876                             ubsec_dmamap_cb,
1877                             &dma->dma_paddr,
1878                             mapflags | BUS_DMA_NOWAIT);
1879         if (r != 0) {
1880                 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1881                         "bus_dmamap_load failed; error %u\n", r);
1882                 goto fail_3;
1883         }
1884
1885         dma->dma_size = size;
1886         return (0);
1887
1888 fail_3:
1889         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1890 fail_2:
1891         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1892 fail_1:
1893         bus_dma_tag_destroy(dma->dma_tag);
1894         dma->dma_tag = NULL;
1895         return (r);
1896 }
1897
1898 static void
1899 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1900 {
1901         bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1902         bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1903         bus_dma_tag_destroy(dma->dma_tag);
1904 }
1905
1906 /*
1907  * Resets the board.  Values in the regesters are left as is
1908  * from the reset (i.e. initial values are assigned elsewhere).
1909  */
1910 static void
1911 ubsec_reset_board(struct ubsec_softc *sc)
1912 {
1913     volatile u_int32_t ctrl;
1914
1915     ctrl = READ_REG(sc, BS_CTRL);
1916     ctrl |= BS_CTRL_RESET;
1917     WRITE_REG(sc, BS_CTRL, ctrl);
1918
1919     /*
1920      * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1921      */
1922     DELAY(10);
1923 }
1924
1925 /*
1926  * Init Broadcom registers
1927  */
1928 static void
1929 ubsec_init_board(struct ubsec_softc *sc)
1930 {
1931         u_int32_t ctrl;
1932
1933         ctrl = READ_REG(sc, BS_CTRL);
1934         ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1935         ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1936
1937         if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1938                 ctrl |= BS_CTRL_MCR2INT;
1939         else
1940                 ctrl &= ~BS_CTRL_MCR2INT;
1941
1942         if (sc->sc_flags & UBS_FLAGS_HWNORM)
1943                 ctrl &= ~BS_CTRL_SWNORM;
1944
1945         WRITE_REG(sc, BS_CTRL, ctrl);
1946 }
1947
1948 /*
1949  * Init Broadcom PCI registers
1950  */
1951 static void
1952 ubsec_init_pciregs(device_t dev)
1953 {
1954 #if 0
1955         u_int32_t misc;
1956
1957         misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1958         misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1959             | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1960         misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1961             | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1962         pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1963 #endif
1964
1965         /*
1966          * This will set the cache line size to 1, this will
1967          * force the BCM58xx chip just to do burst read/writes.
1968          * Cache line read/writes are to slow
1969          */
1970         pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1971 }
1972
1973 /*
1974  * Clean up after a chip crash.
1975  * It is assumed that the caller in splimp()
1976  */
1977 static void
1978 ubsec_cleanchip(struct ubsec_softc *sc)
1979 {
1980         struct ubsec_q *q;
1981
1982         while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1983                 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1984                 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1985                 ubsec_free_q(sc, q);
1986         }
1987         sc->sc_nqchip = 0;
1988 }
1989
1990 /*
1991  * free a ubsec_q
1992  * It is assumed that the caller is within splimp().
1993  */
1994 static int
1995 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
1996 {
1997         struct ubsec_q *q2;
1998         struct cryptop *crp;
1999         int npkts;
2000         int i;
2001
2002         npkts = q->q_nstacked_mcrs;
2003
2004         for (i = 0; i < npkts; i++) {
2005                 if(q->q_stacked_mcr[i]) {
2006                         q2 = q->q_stacked_mcr[i];
2007
2008                         if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2009                                 m_freem(q2->q_dst_m);
2010
2011                         crp = (struct cryptop *)q2->q_crp;
2012
2013                         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2014
2015                         crp->crp_etype = EFAULT;
2016                         crypto_done(crp);
2017                 } else {
2018                         break;
2019                 }
2020         }
2021
2022         /*
2023          * Free header MCR
2024          */
2025         if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2026                 m_freem(q->q_dst_m);
2027
2028         crp = (struct cryptop *)q->q_crp;
2029
2030         SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2031
2032         crp->crp_etype = EFAULT;
2033         crypto_done(crp);
2034         return(0);
2035 }
2036
2037 /*
2038  * Routine to reset the chip and clean up.
2039  * It is assumed that the caller is in splimp()
2040  */
2041 static void
2042 ubsec_totalreset(struct ubsec_softc *sc)
2043 {
2044         ubsec_reset_board(sc);
2045         ubsec_init_board(sc);
2046         ubsec_cleanchip(sc);
2047 }
2048
2049 static int
2050 ubsec_dmamap_aligned(struct ubsec_operand *op)
2051 {
2052         int i;
2053
2054         for (i = 0; i < op->nsegs; i++) {
2055                 if (op->segs[i].ds_addr & 3)
2056                         return (0);
2057                 if ((i != (op->nsegs - 1)) &&
2058                     (op->segs[i].ds_len & 3))
2059                         return (0);
2060         }
2061         return (1);
2062 }
2063
2064 static void
2065 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2066 {
2067         switch (q->q_type) {
2068         case UBS_CTXOP_MODEXP: {
2069                 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2070
2071                 ubsec_dma_free(sc, &me->me_q.q_mcr);
2072                 ubsec_dma_free(sc, &me->me_q.q_ctx);
2073                 ubsec_dma_free(sc, &me->me_M);
2074                 ubsec_dma_free(sc, &me->me_E);
2075                 ubsec_dma_free(sc, &me->me_C);
2076                 ubsec_dma_free(sc, &me->me_epb);
2077                 free(me, M_DEVBUF);
2078                 break;
2079         }
2080         case UBS_CTXOP_RSAPRIV: {
2081                 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2082
2083                 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2084                 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2085                 ubsec_dma_free(sc, &rp->rpr_msgin);
2086                 ubsec_dma_free(sc, &rp->rpr_msgout);
2087                 free(rp, M_DEVBUF);
2088                 break;
2089         }
2090         default:
2091                 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2092                 break;
2093         }
2094 }
2095
2096 static int
2097 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
2098 {
2099         struct ubsec_softc *sc = device_get_softc(dev);
2100         int r;
2101
2102         if (krp == NULL || krp->krp_callback == NULL)
2103                 return (EINVAL);
2104
2105         while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2106                 struct ubsec_q2 *q;
2107
2108                 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2109                 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2110                 ubsec_kfree(sc, q);
2111         }
2112
2113         switch (krp->krp_op) {
2114         case CRK_MOD_EXP:
2115                 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2116                         r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2117                 else
2118                         r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2119                 break;
2120         case CRK_MOD_EXP_CRT:
2121                 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2122         default:
2123                 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2124                     krp->krp_op);
2125                 krp->krp_status = EOPNOTSUPP;
2126                 crypto_kdone(krp);
2127                 return (0);
2128         }
2129         return (0);                     /* silence compiler */
2130 }
2131
2132 /*
2133  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2134  */
2135 static int
2136 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2137 {
2138         struct ubsec_q2_modexp *me;
2139         struct ubsec_mcr *mcr;
2140         struct ubsec_ctx_modexp *ctx;
2141         struct ubsec_pktbuf *epb;
2142         int err = 0;
2143         u_int nbits, normbits, mbits, shiftbits, ebits;
2144
2145         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2146         if (me == NULL) {
2147                 err = ENOMEM;
2148                 goto errout;
2149         }
2150         bzero(me, sizeof *me);
2151         me->me_krp = krp;
2152         me->me_q.q_type = UBS_CTXOP_MODEXP;
2153
2154         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2155         if (nbits <= 512)
2156                 normbits = 512;
2157         else if (nbits <= 768)
2158                 normbits = 768;
2159         else if (nbits <= 1024)
2160                 normbits = 1024;
2161         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2162                 normbits = 1536;
2163         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2164                 normbits = 2048;
2165         else {
2166                 err = E2BIG;
2167                 goto errout;
2168         }
2169
2170         shiftbits = normbits - nbits;
2171
2172         me->me_modbits = nbits;
2173         me->me_shiftbits = shiftbits;
2174         me->me_normbits = normbits;
2175
2176         /* Sanity check: result bits must be >= true modulus bits. */
2177         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2178                 err = ERANGE;
2179                 goto errout;
2180         }
2181
2182         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2183             &me->me_q.q_mcr, 0)) {
2184                 err = ENOMEM;
2185                 goto errout;
2186         }
2187         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2188
2189         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2190             &me->me_q.q_ctx, 0)) {
2191                 err = ENOMEM;
2192                 goto errout;
2193         }
2194
2195         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2196         if (mbits > nbits) {
2197                 err = E2BIG;
2198                 goto errout;
2199         }
2200         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2201                 err = ENOMEM;
2202                 goto errout;
2203         }
2204         ubsec_kshift_r(shiftbits,
2205             krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2206             me->me_M.dma_vaddr, normbits);
2207
2208         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2209                 err = ENOMEM;
2210                 goto errout;
2211         }
2212         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2213
2214         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2215         if (ebits > nbits) {
2216                 err = E2BIG;
2217                 goto errout;
2218         }
2219         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2220                 err = ENOMEM;
2221                 goto errout;
2222         }
2223         ubsec_kshift_r(shiftbits,
2224             krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2225             me->me_E.dma_vaddr, normbits);
2226
2227         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2228             &me->me_epb, 0)) {
2229                 err = ENOMEM;
2230                 goto errout;
2231         }
2232         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2233         epb->pb_addr = htole32(me->me_E.dma_paddr);
2234         epb->pb_next = 0;
2235         epb->pb_len = htole32(normbits / 8);
2236
2237 #ifdef UBSEC_DEBUG
2238         if (ubsec_debug) {
2239                 printf("Epb ");
2240                 ubsec_dump_pb(epb);
2241         }
2242 #endif
2243
2244         mcr->mcr_pkts = htole16(1);
2245         mcr->mcr_flags = 0;
2246         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2247         mcr->mcr_reserved = 0;
2248         mcr->mcr_pktlen = 0;
2249
2250         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2251         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2252         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2253
2254         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2255         mcr->mcr_opktbuf.pb_next = 0;
2256         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2257
2258 #ifdef DIAGNOSTIC
2259         /* Misaligned output buffer will hang the chip. */
2260         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2261                 panic("%s: modexp invalid addr 0x%x\n",
2262                     device_get_nameunit(sc->sc_dev),
2263                     letoh32(mcr->mcr_opktbuf.pb_addr));
2264         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2265                 panic("%s: modexp invalid len 0x%x\n",
2266                     device_get_nameunit(sc->sc_dev),
2267                     letoh32(mcr->mcr_opktbuf.pb_len));
2268 #endif
2269
2270         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2271         bzero(ctx, sizeof(*ctx));
2272         ubsec_kshift_r(shiftbits,
2273             krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2274             ctx->me_N, normbits);
2275         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2276         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2277         ctx->me_E_len = htole16(nbits);
2278         ctx->me_N_len = htole16(nbits);
2279
2280 #ifdef UBSEC_DEBUG
2281         if (ubsec_debug) {
2282                 ubsec_dump_mcr(mcr);
2283                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2284         }
2285 #endif
2286
2287         /*
2288          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2289          * everything else.
2290          */
2291         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2292         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2293         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2294         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2295
2296         /* Enqueue and we're done... */
2297         mtx_lock(&sc->sc_mcr2lock);
2298         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2299         ubsec_feed2(sc);
2300         ubsecstats.hst_modexp++;
2301         mtx_unlock(&sc->sc_mcr2lock);
2302
2303         return (0);
2304
2305 errout:
2306         if (me != NULL) {
2307                 if (me->me_q.q_mcr.dma_tag != NULL)
2308                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2309                 if (me->me_q.q_ctx.dma_tag != NULL) {
2310                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2311                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2312                 }
2313                 if (me->me_M.dma_tag != NULL) {
2314                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2315                         ubsec_dma_free(sc, &me->me_M);
2316                 }
2317                 if (me->me_E.dma_tag != NULL) {
2318                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2319                         ubsec_dma_free(sc, &me->me_E);
2320                 }
2321                 if (me->me_C.dma_tag != NULL) {
2322                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2323                         ubsec_dma_free(sc, &me->me_C);
2324                 }
2325                 if (me->me_epb.dma_tag != NULL)
2326                         ubsec_dma_free(sc, &me->me_epb);
2327                 free(me, M_DEVBUF);
2328         }
2329         krp->krp_status = err;
2330         crypto_kdone(krp);
2331         return (0);
2332 }
2333
2334 /*
2335  * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2336  */
2337 static int
2338 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2339 {
2340         struct ubsec_q2_modexp *me;
2341         struct ubsec_mcr *mcr;
2342         struct ubsec_ctx_modexp *ctx;
2343         struct ubsec_pktbuf *epb;
2344         int err = 0;
2345         u_int nbits, normbits, mbits, shiftbits, ebits;
2346
2347         me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2348         if (me == NULL) {
2349                 err = ENOMEM;
2350                 goto errout;
2351         }
2352         bzero(me, sizeof *me);
2353         me->me_krp = krp;
2354         me->me_q.q_type = UBS_CTXOP_MODEXP;
2355
2356         nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2357         if (nbits <= 512)
2358                 normbits = 512;
2359         else if (nbits <= 768)
2360                 normbits = 768;
2361         else if (nbits <= 1024)
2362                 normbits = 1024;
2363         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2364                 normbits = 1536;
2365         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2366                 normbits = 2048;
2367         else {
2368                 err = E2BIG;
2369                 goto errout;
2370         }
2371
2372         shiftbits = normbits - nbits;
2373
2374         /* XXX ??? */
2375         me->me_modbits = nbits;
2376         me->me_shiftbits = shiftbits;
2377         me->me_normbits = normbits;
2378
2379         /* Sanity check: result bits must be >= true modulus bits. */
2380         if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2381                 err = ERANGE;
2382                 goto errout;
2383         }
2384
2385         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2386             &me->me_q.q_mcr, 0)) {
2387                 err = ENOMEM;
2388                 goto errout;
2389         }
2390         mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2391
2392         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2393             &me->me_q.q_ctx, 0)) {
2394                 err = ENOMEM;
2395                 goto errout;
2396         }
2397
2398         mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2399         if (mbits > nbits) {
2400                 err = E2BIG;
2401                 goto errout;
2402         }
2403         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2404                 err = ENOMEM;
2405                 goto errout;
2406         }
2407         bzero(me->me_M.dma_vaddr, normbits / 8);
2408         bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2409             me->me_M.dma_vaddr, (mbits + 7) / 8);
2410
2411         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2412                 err = ENOMEM;
2413                 goto errout;
2414         }
2415         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2416
2417         ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2418         if (ebits > nbits) {
2419                 err = E2BIG;
2420                 goto errout;
2421         }
2422         if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2423                 err = ENOMEM;
2424                 goto errout;
2425         }
2426         bzero(me->me_E.dma_vaddr, normbits / 8);
2427         bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2428             me->me_E.dma_vaddr, (ebits + 7) / 8);
2429
2430         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2431             &me->me_epb, 0)) {
2432                 err = ENOMEM;
2433                 goto errout;
2434         }
2435         epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2436         epb->pb_addr = htole32(me->me_E.dma_paddr);
2437         epb->pb_next = 0;
2438         epb->pb_len = htole32((ebits + 7) / 8);
2439
2440 #ifdef UBSEC_DEBUG
2441         if (ubsec_debug) {
2442                 printf("Epb ");
2443                 ubsec_dump_pb(epb);
2444         }
2445 #endif
2446
2447         mcr->mcr_pkts = htole16(1);
2448         mcr->mcr_flags = 0;
2449         mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2450         mcr->mcr_reserved = 0;
2451         mcr->mcr_pktlen = 0;
2452
2453         mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2454         mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2455         mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2456
2457         mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2458         mcr->mcr_opktbuf.pb_next = 0;
2459         mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2460
2461 #ifdef DIAGNOSTIC
2462         /* Misaligned output buffer will hang the chip. */
2463         if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2464                 panic("%s: modexp invalid addr 0x%x\n",
2465                     device_get_nameunit(sc->sc_dev),
2466                     letoh32(mcr->mcr_opktbuf.pb_addr));
2467         if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2468                 panic("%s: modexp invalid len 0x%x\n",
2469                     device_get_nameunit(sc->sc_dev),
2470                     letoh32(mcr->mcr_opktbuf.pb_len));
2471 #endif
2472
2473         ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2474         bzero(ctx, sizeof(*ctx));
2475         bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2476             (nbits + 7) / 8);
2477         ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2478         ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2479         ctx->me_E_len = htole16(ebits);
2480         ctx->me_N_len = htole16(nbits);
2481
2482 #ifdef UBSEC_DEBUG
2483         if (ubsec_debug) {
2484                 ubsec_dump_mcr(mcr);
2485                 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2486         }
2487 #endif
2488
2489         /*
2490          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2491          * everything else.
2492          */
2493         ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2494         ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2495         ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2496         ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2497
2498         /* Enqueue and we're done... */
2499         mtx_lock(&sc->sc_mcr2lock);
2500         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2501         ubsec_feed2(sc);
2502         mtx_unlock(&sc->sc_mcr2lock);
2503
2504         return (0);
2505
2506 errout:
2507         if (me != NULL) {
2508                 if (me->me_q.q_mcr.dma_tag != NULL)
2509                         ubsec_dma_free(sc, &me->me_q.q_mcr);
2510                 if (me->me_q.q_ctx.dma_tag != NULL) {
2511                         bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2512                         ubsec_dma_free(sc, &me->me_q.q_ctx);
2513                 }
2514                 if (me->me_M.dma_tag != NULL) {
2515                         bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2516                         ubsec_dma_free(sc, &me->me_M);
2517                 }
2518                 if (me->me_E.dma_tag != NULL) {
2519                         bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2520                         ubsec_dma_free(sc, &me->me_E);
2521                 }
2522                 if (me->me_C.dma_tag != NULL) {
2523                         bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2524                         ubsec_dma_free(sc, &me->me_C);
2525                 }
2526                 if (me->me_epb.dma_tag != NULL)
2527                         ubsec_dma_free(sc, &me->me_epb);
2528                 free(me, M_DEVBUF);
2529         }
2530         krp->krp_status = err;
2531         crypto_kdone(krp);
2532         return (0);
2533 }
2534
2535 static int
2536 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2537 {
2538         struct ubsec_q2_rsapriv *rp = NULL;
2539         struct ubsec_mcr *mcr;
2540         struct ubsec_ctx_rsapriv *ctx;
2541         int err = 0;
2542         u_int padlen, msglen;
2543
2544         msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2545         padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2546         if (msglen > padlen)
2547                 padlen = msglen;
2548
2549         if (padlen <= 256)
2550                 padlen = 256;
2551         else if (padlen <= 384)
2552                 padlen = 384;
2553         else if (padlen <= 512)
2554                 padlen = 512;
2555         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2556                 padlen = 768;
2557         else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2558                 padlen = 1024;
2559         else {
2560                 err = E2BIG;
2561                 goto errout;
2562         }
2563
2564         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2565                 err = E2BIG;
2566                 goto errout;
2567         }
2568
2569         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2570                 err = E2BIG;
2571                 goto errout;
2572         }
2573
2574         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2575                 err = E2BIG;
2576                 goto errout;
2577         }
2578
2579         rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2580         if (rp == NULL)
2581                 return (ENOMEM);
2582         bzero(rp, sizeof *rp);
2583         rp->rpr_krp = krp;
2584         rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2585
2586         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2587             &rp->rpr_q.q_mcr, 0)) {
2588                 err = ENOMEM;
2589                 goto errout;
2590         }
2591         mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2592
2593         if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2594             &rp->rpr_q.q_ctx, 0)) {
2595                 err = ENOMEM;
2596                 goto errout;
2597         }
2598         ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2599         bzero(ctx, sizeof *ctx);
2600
2601         /* Copy in p */
2602         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2603             &ctx->rpr_buf[0 * (padlen / 8)],
2604             (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2605
2606         /* Copy in q */
2607         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2608             &ctx->rpr_buf[1 * (padlen / 8)],
2609             (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2610
2611         /* Copy in dp */
2612         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2613             &ctx->rpr_buf[2 * (padlen / 8)],
2614             (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2615
2616         /* Copy in dq */
2617         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2618             &ctx->rpr_buf[3 * (padlen / 8)],
2619             (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2620
2621         /* Copy in pinv */
2622         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2623             &ctx->rpr_buf[4 * (padlen / 8)],
2624             (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2625
2626         msglen = padlen * 2;
2627
2628         /* Copy in input message (aligned buffer/length). */
2629         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2630                 /* Is this likely? */
2631                 err = E2BIG;
2632                 goto errout;
2633         }
2634         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2635                 err = ENOMEM;
2636                 goto errout;
2637         }
2638         bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2639         bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2640             rp->rpr_msgin.dma_vaddr,
2641             (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2642
2643         /* Prepare space for output message (aligned buffer/length). */
2644         if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2645                 /* Is this likely? */
2646                 err = E2BIG;
2647                 goto errout;
2648         }
2649         if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2650                 err = ENOMEM;
2651                 goto errout;
2652         }
2653         bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2654
2655         mcr->mcr_pkts = htole16(1);
2656         mcr->mcr_flags = 0;
2657         mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2658         mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2659         mcr->mcr_ipktbuf.pb_next = 0;
2660         mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2661         mcr->mcr_reserved = 0;
2662         mcr->mcr_pktlen = htole16(msglen);
2663         mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2664         mcr->mcr_opktbuf.pb_next = 0;
2665         mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2666
2667 #ifdef DIAGNOSTIC
2668         if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2669                 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2670                     device_get_nameunit(sc->sc_dev),
2671                     rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size);
2672         }
2673         if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2674                 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2675                     device_get_nameunit(sc->sc_dev),
2676                     rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size);
2677         }
2678 #endif
2679
2680         ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2681         ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2682         ctx->rpr_q_len = htole16(padlen);
2683         ctx->rpr_p_len = htole16(padlen);
2684
2685         /*
2686          * ubsec_feed2 will sync mcr and ctx, we just need to sync
2687          * everything else.
2688          */
2689         ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2690         ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2691
2692         /* Enqueue and we're done... */
2693         mtx_lock(&sc->sc_mcr2lock);
2694         SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2695         ubsec_feed2(sc);
2696         ubsecstats.hst_modexpcrt++;
2697         mtx_unlock(&sc->sc_mcr2lock);
2698         return (0);
2699
2700 errout:
2701         if (rp != NULL) {
2702                 if (rp->rpr_q.q_mcr.dma_tag != NULL)
2703                         ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2704                 if (rp->rpr_msgin.dma_tag != NULL) {
2705                         bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2706                         ubsec_dma_free(sc, &rp->rpr_msgin);
2707                 }
2708                 if (rp->rpr_msgout.dma_tag != NULL) {
2709                         bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2710                         ubsec_dma_free(sc, &rp->rpr_msgout);
2711                 }
2712                 free(rp, M_DEVBUF);
2713         }
2714         krp->krp_status = err;
2715         crypto_kdone(krp);
2716         return (0);
2717 }
2718
2719 #ifdef UBSEC_DEBUG
2720 static void
2721 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2722 {
2723         printf("addr 0x%x (0x%x) next 0x%x\n",
2724             pb->pb_addr, pb->pb_len, pb->pb_next);
2725 }
2726
2727 static void
2728 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2729 {
2730         printf("CTX (0x%x):\n", c->ctx_len);
2731         switch (letoh16(c->ctx_op)) {
2732         case UBS_CTXOP_RNGBYPASS:
2733         case UBS_CTXOP_RNGSHA1:
2734                 break;
2735         case UBS_CTXOP_MODEXP:
2736         {
2737                 struct ubsec_ctx_modexp *cx = (void *)c;
2738                 int i, len;
2739
2740                 printf(" Elen %u, Nlen %u\n",
2741                     letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2742                 len = (cx->me_N_len + 7)/8;
2743                 for (i = 0; i < len; i++)
2744                         printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2745                 printf("\n");
2746                 break;
2747         }
2748         default:
2749                 printf("unknown context: %x\n", c->ctx_op);
2750         }
2751         printf("END CTX\n");
2752 }
2753
2754 static void
2755 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2756 {
2757         volatile struct ubsec_mcr_add *ma;
2758         int i;
2759
2760         printf("MCR:\n");
2761         printf(" pkts: %u, flags 0x%x\n",
2762             letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2763         ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2764         for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2765                 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2766                     letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2767                     letoh16(ma->mcr_reserved));
2768                 printf(" %d: ipkt ", i);
2769                 ubsec_dump_pb(&ma->mcr_ipktbuf);
2770                 printf(" %d: opkt ", i);
2771                 ubsec_dump_pb(&ma->mcr_opktbuf);
2772                 ma++;
2773         }
2774         printf("END MCR\n");
2775 }
2776 #endif /* UBSEC_DEBUG */
2777
2778 /*
2779  * Return the number of significant bits of a big number.
2780  */
2781 static int
2782 ubsec_ksigbits(struct crparam *cr)
2783 {
2784         u_int plen = (cr->crp_nbits + 7) / 8;
2785         int i, sig = plen * 8;
2786         u_int8_t c, *p = cr->crp_p;
2787
2788         for (i = plen - 1; i >= 0; i--) {
2789                 c = p[i];
2790                 if (c != 0) {
2791                         while ((c & 0x80) == 0) {
2792                                 sig--;
2793                                 c <<= 1;
2794                         }
2795                         break;
2796                 }
2797                 sig -= 8;
2798         }
2799         return (sig);
2800 }
2801
2802 static void
2803 ubsec_kshift_r(
2804         u_int shiftbits,
2805         u_int8_t *src, u_int srcbits,
2806         u_int8_t *dst, u_int dstbits)
2807 {
2808         u_int slen, dlen;
2809         int i, si, di, n;
2810
2811         slen = (srcbits + 7) / 8;
2812         dlen = (dstbits + 7) / 8;
2813
2814         for (i = 0; i < slen; i++)
2815                 dst[i] = src[i];
2816         for (i = 0; i < dlen - slen; i++)
2817                 dst[slen + i] = 0;
2818
2819         n = shiftbits / 8;
2820         if (n != 0) {
2821                 si = dlen - n - 1;
2822                 di = dlen - 1;
2823                 while (si >= 0)
2824                         dst[di--] = dst[si--];
2825                 while (di >= 0)
2826                         dst[di--] = 0;
2827         }
2828
2829         n = shiftbits % 8;
2830         if (n != 0) {
2831                 for (i = dlen - 1; i > 0; i--)
2832                         dst[i] = (dst[i] << n) |
2833                             (dst[i - 1] >> (8 - n));
2834                 dst[0] = dst[0] << n;
2835         }
2836 }
2837
2838 static void
2839 ubsec_kshift_l(
2840         u_int shiftbits,
2841         u_int8_t *src, u_int srcbits,
2842         u_int8_t *dst, u_int dstbits)
2843 {
2844         int slen, dlen, i, n;
2845
2846         slen = (srcbits + 7) / 8;
2847         dlen = (dstbits + 7) / 8;
2848
2849         n = shiftbits / 8;
2850         for (i = 0; i < slen; i++)
2851                 dst[i] = src[i + n];
2852         for (i = 0; i < dlen - slen; i++)
2853                 dst[slen + i] = 0;
2854
2855         n = shiftbits % 8;
2856         if (n != 0) {
2857                 for (i = 0; i < (dlen - 1); i++)
2858                         dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2859                 dst[dlen - 1] = dst[dlen - 1] >> n;
2860         }
2861 }