2 /* $OpenBSD: ubsecreg.h,v 1.27 2002/09/11 22:40:31 jason Exp $ */
5 * SPDX-License-Identifier: BSD-3-Clause
7 * Copyright (c) 2000 Theo de Raadt
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * Effort sponsored in part by the Defense Advanced Research Projects
34 * Agency (DARPA) and Air Force Research Laboratory, Air Force
35 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
40 * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband
41 * Security "uBSec" chip. Definitions from revision 2.8 of the product
45 #define BS_BAR 0x10 /* DMA base address register */
46 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
47 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
49 #define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */
50 #define PCI_VENDOR_BLUESTEEL 0x15ab /* Bluesteel Networks */
51 #define PCI_VENDOR_SUN 0x108e /* Sun Microsystems */
53 /* Bluesteel Networks */
54 #define PCI_PRODUCT_BLUESTEEL_5501 0x0000 /* 5501 */
55 #define PCI_PRODUCT_BLUESTEEL_5601 0x5601 /* 5601 */
58 #define PCI_PRODUCT_BROADCOM_BCM5700 0x1644 /* BCM5700 */
59 #define PCI_PRODUCT_BROADCOM_BCM5701 0x1645 /* BCM5701 */
60 #define PCI_PRODUCT_BROADCOM_5801 0x5801 /* 5801 */
61 #define PCI_PRODUCT_BROADCOM_5802 0x5802 /* 5802 */
62 #define PCI_PRODUCT_BROADCOM_5805 0x5805 /* 5805 */
63 #define PCI_PRODUCT_BROADCOM_5820 0x5820 /* 5820 */
64 #define PCI_PRODUCT_BROADCOM_5821 0x5821 /* 5821 */
65 #define PCI_PRODUCT_BROADCOM_5822 0x5822 /* 5822 */
66 #define PCI_PRODUCT_BROADCOM_5823 0x5823 /* 5823 */
67 #define PCI_PRODUCT_BROADCOM_5825 0x5825 /* 5825 */
69 /* Sun Microsystems */
70 #define PCI_PRODUCT_SUN_5821 0x5454 /* Crypto 5821 */
71 #define PCI_PRODUCT_SUN_SCA1K 0x5455 /* Crypto 1K */
73 #define UBS_PCI_RTY_SHIFT 8
74 #define UBS_PCI_RTY_MASK 0xff
75 #define UBS_PCI_RTY(misc) \
76 (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK)
78 #define UBS_PCI_TOUT_SHIFT 0
79 #define UBS_PCI_TOUT_MASK 0xff
80 #define UBS_PCI_TOUT(misc) \
81 (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK)
84 * DMA Control & Status Registers (offset from BS_BAR)
86 #define BS_MCR1 0x00 /* DMA Master Command Record 1 */
87 #define BS_CTRL 0x04 /* DMA Control */
88 #define BS_STAT 0x08 /* DMA Status */
89 #define BS_ERR 0x0c /* DMA Error Address */
90 #define BS_MCR2 0x10 /* DMA Master Command Record 2 */
92 /* BS_CTRL - DMA Control */
93 #define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */
94 #define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */
95 #define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */
96 #define BS_CTRL_OFM 0x10000000 /* Output fragment mode */
97 #define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */
98 #define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */
99 #define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */
100 #define BS_CTRL_RNG_M 0x01800000 /* RNG mode */
101 #define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */
102 #define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */
103 #define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */
104 #define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */
105 #define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */
106 #define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */
107 #define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64)
109 /* BS_STAT - DMA Status */
110 #define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */
111 #define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */
112 #define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */
113 #define BS_STAT_DMAERR 0x10000000 /* DMA error */
114 #define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */
115 #define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */
116 #define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */
117 #define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */
119 /* BS_ERR - DMA Error Address */
120 #define BS_ERR_ADDR 0xfffffffc /* error address mask */
121 #define BS_ERR_READ 0x00000002 /* fault was on read */
123 struct ubsec_pktctx {
124 u_int32_t pc_deskey[6]; /* 3DES key */
125 u_int32_t pc_hminner[5]; /* hmac inner state */
126 u_int32_t pc_hmouter[5]; /* hmac outer state */
127 u_int32_t pc_iv[2]; /* [3]DES iv */
128 u_int16_t pc_flags; /* flags, below */
129 u_int16_t pc_offset; /* crypto offset */
131 #define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */
132 #define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */
133 #define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */
134 #define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */
135 #define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */
136 #define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */
137 #define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */
139 struct ubsec_pktctx_long {
140 volatile u_int16_t pc_len; /* length of ctx struct */
141 volatile u_int16_t pc_type; /* context type, 0 */
142 volatile u_int16_t pc_flags; /* flags, same as above */
143 volatile u_int16_t pc_offset; /* crypto/auth offset */
144 volatile u_int32_t pc_deskey[6]; /* 3DES key */
145 volatile u_int32_t pc_iv[2]; /* [3]DES iv */
146 volatile u_int32_t pc_hminner[5]; /* hmac inner state */
147 volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
149 #define UBS_PKTCTX_TYPE_IPSEC 0x0000
151 struct ubsec_pktbuf {
152 volatile u_int32_t pb_addr; /* address of buffer start */
153 volatile u_int32_t pb_next; /* pointer to next pktbuf */
154 volatile u_int32_t pb_len; /* packet length */
156 #define UBS_PKTBUF_LEN 0x0000ffff /* length mask */
159 volatile u_int16_t mcr_pkts; /* #pkts in this mcr */
160 volatile u_int16_t mcr_flags; /* mcr flags (below) */
161 volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
162 struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
163 volatile u_int16_t mcr_reserved;
164 volatile u_int16_t mcr_pktlen;
165 struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
168 struct ubsec_mcr_add {
169 volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
170 struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
171 volatile u_int16_t mcr_reserved;
172 volatile u_int16_t mcr_pktlen;
173 struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
176 #define UBS_MCR_DONE 0x0001 /* mcr has been processed */
177 #define UBS_MCR_ERROR 0x0002 /* error in processing */
178 #define UBS_MCR_ERRORCODE 0xff00 /* error type */
180 struct ubsec_ctx_keyop {
181 volatile u_int16_t ctx_len; /* command length */
182 volatile u_int16_t ctx_op; /* operation code */
183 volatile u_int8_t ctx_pad[60]; /* padding */
185 #define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */
186 #define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */
187 #define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */
188 #define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */
189 #define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */
190 #define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */
191 #define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */
192 #define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */
193 #define UBS_CTXOP_MODADD 0x43 /* modular addition */
194 #define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */
195 #define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */
196 #define UBS_CTXOP_MODRED 0x46 /* modular reduction */
197 #define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */
198 #define UBS_CTXOP_MODINV 0x48 /* modular inverse */
200 struct ubsec_ctx_rngbypass {
201 volatile u_int16_t rbp_len; /* command length, 64 */
202 volatile u_int16_t rbp_op; /* rng bypass, 0x41 */
203 volatile u_int8_t rbp_pad[60]; /* padding */
206 /* modexp: C = (M ^ E) mod N */
207 struct ubsec_ctx_modexp {
208 volatile u_int16_t me_len; /* command length */
209 volatile u_int16_t me_op; /* modexp, 0x47 */
210 volatile u_int16_t me_E_len; /* E (bits) */
211 volatile u_int16_t me_N_len; /* N (bits) */
212 u_int8_t me_N[2048/8]; /* N */
215 struct ubsec_ctx_rsapriv {
216 volatile u_int16_t rpr_len; /* command length */
217 volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */
218 volatile u_int16_t rpr_q_len; /* q (bits) */
219 volatile u_int16_t rpr_p_len; /* p (bits) */
220 u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */
221 /* p, q, dp, dq, pinv */