2 /* $OpenBSD: ubsecvar.h,v 1.35 2002/09/24 18:33:26 jason Exp $ */
5 * SPDX-License-Identifier: BSD-3-Clause
7 * Copyright (c) 2000 Theo de Raadt
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * Effort sponsored in part by the Defense Advanced Research Projects
34 * Agency (DARPA) and Air Force Research Laboratory, Air Force
35 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
39 /* Maximum queue length */
40 #ifndef UBS_MAX_NQUEUE
41 #define UBS_MAX_NQUEUE 60
44 #define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */
47 #define UBS_MAX_AGGR 5 /* Maximum aggregation count */
50 #define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28)
51 #define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff)
52 #define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff))
54 #define UBS_DEF_RTY 0xff /* PCI Retry Timeout */
55 #define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */
56 #define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */
60 struct ubsec_dma_alloc {
63 bus_dma_tag_t dma_tag;
65 bus_dma_segment_t dma_seg;
71 SIMPLEQ_ENTRY(ubsec_q2) q_next;
72 struct ubsec_dma_alloc q_mcr;
73 struct ubsec_dma_alloc q_ctx;
78 struct ubsec_q2 rng_q;
79 struct ubsec_dma_alloc rng_buf;
83 /* C = (M ^ E) mod N */
84 #define UBS_MODEXP_PAR_M 0
85 #define UBS_MODEXP_PAR_E 1
86 #define UBS_MODEXP_PAR_N 2
87 #define UBS_MODEXP_PAR_C 3
88 struct ubsec_q2_modexp {
90 struct cryptkop * me_krp;
91 struct ubsec_dma_alloc me_M;
92 struct ubsec_dma_alloc me_E;
93 struct ubsec_dma_alloc me_C;
94 struct ubsec_dma_alloc me_epb;
100 #define UBS_RSAPRIV_PAR_P 0
101 #define UBS_RSAPRIV_PAR_Q 1
102 #define UBS_RSAPRIV_PAR_DP 2
103 #define UBS_RSAPRIV_PAR_DQ 3
104 #define UBS_RSAPRIV_PAR_PINV 4
105 #define UBS_RSAPRIV_PAR_MSGIN 5
106 #define UBS_RSAPRIV_PAR_MSGOUT 6
107 struct ubsec_q2_rsapriv {
108 struct ubsec_q2 rpr_q;
109 struct cryptkop * rpr_krp;
110 struct ubsec_dma_alloc rpr_msgin;
111 struct ubsec_dma_alloc rpr_msgout;
114 #define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */
116 struct ubsec_dmachunk {
117 struct ubsec_mcr d_mcr;
118 struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1];
119 struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1];
120 struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1];
121 u_int32_t d_macbuf[5];
123 struct ubsec_pktctx_long ctxl;
124 struct ubsec_pktctx ctx;
129 SIMPLEQ_ENTRY(ubsec_dma) d_next;
130 struct ubsec_dmachunk *d_dma;
131 struct ubsec_dma_alloc d_alloc;
134 #define UBS_FLAGS_KEY 0x01 /* has key accelerator */
135 #define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */
136 #define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */
137 #define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */
138 #define UBS_FLAGS_RNG 0x10 /* hardware rng */
140 struct ubsec_operand {
148 bus_dma_segment_t segs[UBS_MAX_SCATTER];
152 SIMPLEQ_ENTRY(ubsec_q) q_next;
154 struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1];
155 struct cryptop *q_crp;
156 struct ubsec_dma *q_dma;
158 struct ubsec_operand q_src;
159 struct ubsec_operand q_dst;
165 #define q_src_m q_src.u.m
166 #define q_src_io q_src.u.io
167 #define q_src_map q_src.map
168 #define q_src_nsegs q_src.nsegs
169 #define q_src_segs q_src.segs
170 #define q_src_mapsize q_src.mapsize
172 #define q_dst_m q_dst.u.m
173 #define q_dst_io q_dst.u.io
174 #define q_dst_map q_dst.map
175 #define q_dst_nsegs q_dst.nsegs
176 #define q_dst_segs q_dst.segs
177 #define q_dst_mapsize q_dst.mapsize
179 struct rndstate_test;
182 device_t sc_dev; /* device backpointer */
183 struct resource *sc_irq;
184 void *sc_ih; /* interrupt handler cookie */
185 bus_space_handle_t sc_sh; /* memory handle */
186 bus_space_tag_t sc_st; /* memory tag */
187 struct resource *sc_sr; /* memory resource */
188 bus_dma_tag_t sc_dmat; /* dma tag */
189 int sc_flags; /* device specific flags */
191 int sc_needwakeup; /* notify crypto layer */
192 u_int32_t sc_statmask; /* interrupt status mask */
193 int32_t sc_cid; /* crypto tag */
194 struct mtx sc_mcr1lock; /* mcr1 operation lock */
195 SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */
196 int sc_nqueue; /* count enqueued, mcr1 */
197 SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */
198 int sc_nqchip; /* count on chip, mcr1 */
199 struct mtx sc_freeqlock; /* freequeue lock */
200 SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */
201 struct mtx sc_mcr2lock; /* mcr2 operation lock */
202 SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */
203 int sc_nqueue2; /* count enqueued, mcr2 */
204 SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */
205 int sc_nsessions; /* # of sessions */
206 struct ubsec_session *sc_sessions; /* sessions */
207 struct callout sc_rngto; /* rng timeout */
208 int sc_rnghz; /* rng poll time */
209 struct ubsec_q2_rng sc_rng;
210 struct rndtest_state *sc_rndtest; /* RNG test state */
211 void (*sc_harvest)(struct rndtest_state *,
213 struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE];
214 struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE];
215 SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */
218 #define UBSEC_QFLAGS_COPYOUTIV 0x1
220 struct ubsec_session {
222 u_int32_t ses_deskey[6]; /* 3DES key */
223 u_int32_t ses_mlen; /* hmac length */
224 u_int32_t ses_hminner[5]; /* hmac inner state */
225 u_int32_t ses_hmouter[5]; /* hmac outer state */
226 u_int32_t ses_iv[2]; /* [3]DES iv */
231 u_int64_t hst_ibytes;
232 u_int64_t hst_obytes;
233 u_int32_t hst_ipackets;
234 u_int32_t hst_opackets;
235 u_int32_t hst_invalid; /* invalid argument */
236 u_int32_t hst_badsession; /* invalid session id */
237 u_int32_t hst_badflags; /* flags indicate !(mbuf | uio) */
238 u_int32_t hst_nodesc; /* op submitted w/o descriptors */
239 u_int32_t hst_badalg; /* unsupported algorithm */
241 u_int32_t hst_queuefull;
242 u_int32_t hst_dmaerr;
243 u_int32_t hst_mcrerr;
244 u_int32_t hst_nodmafree;
245 u_int32_t hst_lenmismatch; /* enc/auth lengths different */
246 u_int32_t hst_skipmismatch; /* enc part begins before auth part */
247 u_int32_t hst_iovmisaligned; /* iov op not aligned */
248 u_int32_t hst_noirq; /* IRQ for no reason */
249 u_int32_t hst_unaligned; /* unaligned src caused copy */
250 u_int32_t hst_nomap; /* bus_dmamap_create failed */
251 u_int32_t hst_noload; /* bus_dmamap_load_* failed */
252 u_int32_t hst_nombuf; /* MGET* failed */
253 u_int32_t hst_nomcl; /* MCLGET* failed */
254 u_int32_t hst_totbatch; /* ops submitted w/o interrupt */
255 u_int32_t hst_maxbatch; /* max ops submitted together */
256 u_int32_t hst_maxqueue; /* max ops queued for submission */
257 u_int32_t hst_maxqchip; /* max mcr1 ops out for processing */
258 u_int32_t hst_mcr1full; /* MCR1 too busy to take ops */
259 u_int32_t hst_rng; /* RNG requests */
260 u_int32_t hst_modexp; /* MOD EXP requests */
261 u_int32_t hst_modexpcrt; /* MOD EXP CRT requests */