sys/dev/usb/controller/at91dci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the AT91 series USB Device
  31  * Controller
  32  */
  33
  34 /*
  35  * Thanks to "David Brownell" for helping out regarding the hardware
  36  * endpoint profiles.
  37  */
  38
  39 /*
  40  * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is
  41  * reset.
  42  *
  43  * NOTE: When the chip detects BUS-reset it will also reset the
  44  * endpoints, Function-address and more.
  45  */
  46
  47 #ifdef USB_GLOBAL_INCLUDE_FILE
  48 #include USB_GLOBAL_INCLUDE_FILE
  49 #else
  50 #include <sys/stdint.h>
  51 #include <sys/stddef.h>
  52 #include <sys/param.h>
  53 #include <sys/queue.h>
  54 #include <sys/types.h>
  55 #include <sys/systm.h>
  56 #include <sys/kernel.h>
  57 #include <sys/bus.h>
  58 #include <sys/module.h>
  59 #include <sys/lock.h>
  60 #include <sys/mutex.h>
  61 #include <sys/condvar.h>
  62 #include <sys/sysctl.h>
  63 #include <sys/sx.h>
  64 #include <sys/unistd.h>
  65 #include <sys/callout.h>
  66 #include <sys/malloc.h>
  67 #include <sys/priv.h>
  68
  69 #include <dev/usb/usb.h>
  70 #include <dev/usb/usbdi.h>
  71
  72 #define USB_DEBUG_VAR at91dcidebug
  73
  74 #include <dev/usb/usb_core.h>
  75 #include <dev/usb/usb_debug.h>
  76 #include <dev/usb/usb_busdma.h>
  77 #include <dev/usb/usb_process.h>
  78 #include <dev/usb/usb_transfer.h>
  79 #include <dev/usb/usb_device.h>
  80 #include <dev/usb/usb_hub.h>
  81 #include <dev/usb/usb_util.h>
  82
  83 #include <dev/usb/usb_controller.h>
  84 #include <dev/usb/usb_bus.h>
  85 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  86
  87 #include <dev/usb/controller/at91dci.h>
  88
  89 #define AT9100_DCI_BUS2SC(bus) \
  90    ((struct at91dci_softc *)(((uint8_t *)(bus)) - \
  91     ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus))))
  92
  93 #define AT9100_DCI_PC2SC(pc) \
  94    AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  95
  96 #define AT9100_DCI_THREAD_IRQ \
  97   (AT91_UDP_INT_BUS | AT91_UDP_INT_END_BR | AT91_UDP_INT_RXRSM | AT91_UDP_INT_RXSUSP)
  98
  99 #ifdef USB_DEBUG
 100 static int at91dcidebug = 0;
 101
 102 static SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci");
 103 SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RWTUN,
 104     &at91dcidebug, 0, "at91dci debug level");
 105 #endif
 106
 107 #define AT9100_DCI_INTR_ENDPT 1
 108
 109 /* prototypes */
 110
 111 static const struct usb_bus_methods at91dci_bus_methods;
 112 static const struct usb_pipe_methods at91dci_device_bulk_methods;
 113 static const struct usb_pipe_methods at91dci_device_ctrl_methods;
 114 static const struct usb_pipe_methods at91dci_device_intr_methods;
 115 static const struct usb_pipe_methods at91dci_device_isoc_fs_methods;
 116
 117 static at91dci_cmd_t at91dci_setup_rx;
 118 static at91dci_cmd_t at91dci_data_rx;
 119 static at91dci_cmd_t at91dci_data_tx;
 120 static at91dci_cmd_t at91dci_data_tx_sync;
 121 static void     at91dci_device_done(struct usb_xfer *, usb_error_t);
 122 static void     at91dci_do_poll(struct usb_bus *);
 123 static void     at91dci_standard_done(struct usb_xfer *);
 124 static void     at91dci_root_intr(struct at91dci_softc *sc);
 125
 126 /*
 127  * NOTE: Some of the bits in the CSR register have inverse meaning so
 128  * we need a helper macro when acknowledging events:
 129  */
 130 #define AT91_CSR_ACK(csr, what) do {            \
 131   (csr) &= ~((AT91_UDP_CSR_FORCESTALL|          \
 132               AT91_UDP_CSR_TXPKTRDY|            \
 133               AT91_UDP_CSR_RXBYTECNT) ^ (what));\
 134   (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0|          \
 135              AT91_UDP_CSR_RX_DATA_BK1|          \
 136              AT91_UDP_CSR_TXCOMP|               \
 137              AT91_UDP_CSR_RXSETUP|              \
 138              AT91_UDP_CSR_STALLSENT) ^ (what)); \
 139 } while (0)
 140
 141 /*
 142  * Here is a list of what the chip supports.
 143  * Probably it supports more than listed here!
 144  */
 145 static const struct usb_hw_ep_profile
 146         at91dci_ep_profile[AT91_UDP_EP_MAX] = {
 147
 148         [0] = {
 149                 .max_in_frame_size = 8,
 150                 .max_out_frame_size = 8,
 151                 .is_simplex = 1,
 152                 .support_control = 1,
 153         },
 154         [1] = {
 155                 .max_in_frame_size = 64,
 156                 .max_out_frame_size = 64,
 157                 .is_simplex = 1,
 158                 .support_multi_buffer = 1,
 159                 .support_bulk = 1,
 160                 .support_interrupt = 1,
 161                 .support_isochronous = 1,
 162                 .support_in = 1,
 163                 .support_out = 1,
 164         },
 165         [2] = {
 166                 .max_in_frame_size = 64,
 167                 .max_out_frame_size = 64,
 168                 .is_simplex = 1,
 169                 .support_multi_buffer = 1,
 170                 .support_bulk = 1,
 171                 .support_interrupt = 1,
 172                 .support_isochronous = 1,
 173                 .support_in = 1,
 174                 .support_out = 1,
 175         },
 176         [3] = {
 177                 /* can also do BULK */
 178                 .max_in_frame_size = 8,
 179                 .max_out_frame_size = 8,
 180                 .is_simplex = 1,
 181                 .support_interrupt = 1,
 182                 .support_in = 1,
 183                 .support_out = 1,
 184         },
 185         [4] = {
 186                 .max_in_frame_size = 256,
 187                 .max_out_frame_size = 256,
 188                 .is_simplex = 1,
 189                 .support_multi_buffer = 1,
 190                 .support_bulk = 1,
 191                 .support_interrupt = 1,
 192                 .support_isochronous = 1,
 193                 .support_in = 1,
 194                 .support_out = 1,
 195         },
 196         [5] = {
 197                 .max_in_frame_size = 256,
 198                 .max_out_frame_size = 256,
 199                 .is_simplex = 1,
 200                 .support_multi_buffer = 1,
 201                 .support_bulk = 1,
 202                 .support_interrupt = 1,
 203                 .support_isochronous = 1,
 204                 .support_in = 1,
 205                 .support_out = 1,
 206         },
 207 };
 208
 209 static void
 210 at91dci_get_hw_ep_profile(struct usb_device *udev,
 211     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 212 {
 213         if (ep_addr < AT91_UDP_EP_MAX) {
 214                 *ppf = (at91dci_ep_profile + ep_addr);
 215         } else {
 216                 *ppf = NULL;
 217         }
 218 }
 219
 220 static void
 221 at91dci_clocks_on(struct at91dci_softc *sc)
 222 {
 223         if (sc->sc_flags.clocks_off &&
 224             sc->sc_flags.port_powered) {
 225
 226                 DPRINTFN(5, "\n");
 227
 228                 if (sc->sc_clocks_on) {
 229                         (sc->sc_clocks_on) (sc->sc_clocks_arg);
 230                 }
 231                 sc->sc_flags.clocks_off = 0;
 232
 233                 /* enable Transceiver */
 234                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0);
 235         }
 236 }
 237
 238 static void
 239 at91dci_clocks_off(struct at91dci_softc *sc)
 240 {
 241         if (!sc->sc_flags.clocks_off) {
 242
 243                 DPRINTFN(5, "\n");
 244
 245                 /* disable Transceiver */
 246                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
 247
 248                 if (sc->sc_clocks_off) {
 249                         (sc->sc_clocks_off) (sc->sc_clocks_arg);
 250                 }
 251                 sc->sc_flags.clocks_off = 1;
 252         }
 253 }
 254
 255 static void
 256 at91dci_pull_up(struct at91dci_softc *sc)
 257 {
 258         /* pullup D+, if possible */
 259
 260         if (!sc->sc_flags.d_pulled_up &&
 261             sc->sc_flags.port_powered) {
 262                 sc->sc_flags.d_pulled_up = 1;
 263                 (sc->sc_pull_up) (sc->sc_pull_arg);
 264         }
 265 }
 266
 267 static void
 268 at91dci_pull_down(struct at91dci_softc *sc)
 269 {
 270         /* pulldown D+, if possible */
 271
 272         if (sc->sc_flags.d_pulled_up) {
 273                 sc->sc_flags.d_pulled_up = 0;
 274                 (sc->sc_pull_down) (sc->sc_pull_arg);
 275         }
 276 }
 277
 278 static void
 279 at91dci_wakeup_peer(struct at91dci_softc *sc)
 280 {
 281         if (!(sc->sc_flags.status_suspend)) {
 282                 return;
 283         }
 284
 285         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR);
 286
 287         /* wait 8 milliseconds */
 288         /* Wait for reset to complete. */
 289         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 290
 291         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0);
 292 }
 293
 294 static void
 295 at91dci_set_address(struct at91dci_softc *sc, uint8_t addr)
 296 {
 297         DPRINTFN(5, "addr=%d\n", addr);
 298
 299         AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr |
 300             AT91_UDP_FADDR_EN);
 301 }
 302
 303 static uint8_t
 304 at91dci_setup_rx(struct at91dci_softc *sc, struct at91dci_td *td)
 305 {
 306         struct usb_device_request req;
 307         uint32_t csr;
 308         uint32_t temp;
 309         uint16_t count;
 310
 311         /* read out FIFO status */
 312         csr = AT91_UDP_READ_4(sc, td->status_reg);
 313
 314         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 315
 316         temp = csr;
 317         temp &= (AT91_UDP_CSR_RX_DATA_BK0 |
 318             AT91_UDP_CSR_RX_DATA_BK1 |
 319             AT91_UDP_CSR_STALLSENT |
 320             AT91_UDP_CSR_RXSETUP |
 321             AT91_UDP_CSR_TXCOMP);
 322
 323         if (!(csr & AT91_UDP_CSR_RXSETUP)) {
 324                 goto not_complete;
 325         }
 326         /* clear did stall */
 327         td->did_stall = 0;
 328
 329         /* get the packet byte count */
 330         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 331
 332         /* verify data length */
 333         if (count != td->remainder) {
 334                 DPRINTFN(0, "Invalid SETUP packet "
 335                     "length, %d bytes\n", count);
 336                 goto not_complete;
 337         }
 338         if (count != sizeof(req)) {
 339                 DPRINTFN(0, "Unsupported SETUP packet "
 340                     "length, %d bytes\n", count);
 341                 goto not_complete;
 342         }
 343         /* receive data */
 344         bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 345             td->fifo_reg, (void *)&req, sizeof(req));
 346
 347         /* copy data into real buffer */
 348         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 349
 350         td->offset = sizeof(req);
 351         td->remainder = 0;
 352
 353         /* sneak peek the set address */
 354         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 355             (req.bRequest == UR_SET_ADDRESS)) {
 356                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 357         } else {
 358                 sc->sc_dv_addr = 0xFF;
 359         }
 360
 361         /* sneak peek the endpoint direction */
 362         if (req.bmRequestType & UE_DIR_IN) {
 363                 csr |= AT91_UDP_CSR_DIR;
 364         } else {
 365                 csr &= ~AT91_UDP_CSR_DIR;
 366         }
 367
 368         /* write the direction of the control transfer */
 369         AT91_CSR_ACK(csr, temp);
 370         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 371         return (0);                     /* complete */
 372
 373 not_complete:
 374         /* abort any ongoing transfer */
 375         if (!td->did_stall) {
 376                 DPRINTFN(5, "stalling\n");
 377                 temp |= AT91_UDP_CSR_FORCESTALL;
 378                 td->did_stall = 1;
 379         }
 380
 381         /* clear interrupts, if any */
 382         if (temp) {
 383                 DPRINTFN(5, "clearing 0x%08x\n", temp);
 384                 AT91_CSR_ACK(csr, temp);
 385                 AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 386         }
 387         return (1);                     /* not complete */
 388 }
 389
 390 static uint8_t
 391 at91dci_data_rx(struct at91dci_softc *sc, struct at91dci_td *td)
 392 {
 393         struct usb_page_search buf_res;
 394         uint32_t csr;
 395         uint32_t temp;
 396         uint16_t count;
 397         uint8_t to;
 398         uint8_t got_short;
 399
 400         to = 2;                         /* don't loop forever! */
 401         got_short = 0;
 402
 403         /* check if any of the FIFO banks have data */
 404 repeat:
 405         /* read out FIFO status */
 406         csr = AT91_UDP_READ_4(sc, td->status_reg);
 407
 408         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 409
 410         if (csr & AT91_UDP_CSR_RXSETUP) {
 411                 if (td->remainder == 0) {
 412                         /*
 413                          * We are actually complete and have
 414                          * received the next SETUP
 415                          */
 416                         DPRINTFN(5, "faking complete\n");
 417                         return (0);     /* complete */
 418                 }
 419                 /*
 420                  * USB Host Aborted the transfer.
 421                  */
 422                 td->error = 1;
 423                 return (0);             /* complete */
 424         }
 425         /* Make sure that "STALLSENT" gets cleared */
 426         temp = csr;
 427         temp &= AT91_UDP_CSR_STALLSENT;
 428
 429         /* check status */
 430         if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 |
 431             AT91_UDP_CSR_RX_DATA_BK1))) {
 432                 if (temp) {
 433                         /* write command */
 434                         AT91_CSR_ACK(csr, temp);
 435                         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 436                 }
 437                 return (1);             /* not complete */
 438         }
 439         /* get the packet byte count */
 440         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 441
 442         /* verify the packet byte count */
 443         if (count != td->max_packet_size) {
 444                 if (count < td->max_packet_size) {
 445                         /* we have a short packet */
 446                         td->short_pkt = 1;
 447                         got_short = 1;
 448                 } else {
 449                         /* invalid USB packet */
 450                         td->error = 1;
 451                         return (0);     /* we are complete */
 452                 }
 453         }
 454         /* verify the packet byte count */
 455         if (count > td->remainder) {
 456                 /* invalid USB packet */
 457                 td->error = 1;
 458                 return (0);             /* we are complete */
 459         }
 460         while (count > 0) {
 461                 usbd_get_page(td->pc, td->offset, &buf_res);
 462
 463                 /* get correct length */
 464                 if (buf_res.length > count) {
 465                         buf_res.length = count;
 466                 }
 467                 /* receive data */
 468                 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 469                     td->fifo_reg, buf_res.buffer, buf_res.length);
 470
 471                 /* update counters */
 472                 count -= buf_res.length;
 473                 td->offset += buf_res.length;
 474                 td->remainder -= buf_res.length;
 475         }
 476
 477         /* clear status bits */
 478         if (td->support_multi_buffer) {
 479                 if (td->fifo_bank) {
 480                         td->fifo_bank = 0;
 481                         temp |= AT91_UDP_CSR_RX_DATA_BK1;
 482                 } else {
 483                         td->fifo_bank = 1;
 484                         temp |= AT91_UDP_CSR_RX_DATA_BK0;
 485                 }
 486         } else {
 487                 temp |= (AT91_UDP_CSR_RX_DATA_BK0 |
 488                     AT91_UDP_CSR_RX_DATA_BK1);
 489         }
 490
 491         /* write command */
 492         AT91_CSR_ACK(csr, temp);
 493         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 494
 495         /*
 496          * NOTE: We may have to delay a little bit before
 497          * proceeding after clearing the DATA_BK bits.
 498          */
 499
 500         /* check if we are complete */
 501         if ((td->remainder == 0) || got_short) {
 502                 if (td->short_pkt) {
 503                         /* we are complete */
 504                         return (0);
 505                 }
 506                 /* else need to receive a zero length packet */
 507         }
 508         if (--to) {
 509                 goto repeat;
 510         }
 511         return (1);                     /* not complete */
 512 }
 513
 514 static uint8_t
 515 at91dci_data_tx(struct at91dci_softc *sc, struct at91dci_td *td)
 516 {
 517         struct usb_page_search buf_res;
 518         uint32_t csr;
 519         uint32_t temp;
 520         uint16_t count;
 521         uint8_t to;
 522
 523         to = 2;                         /* don't loop forever! */
 524
 525 repeat:
 526
 527         /* read out FIFO status */
 528         csr = AT91_UDP_READ_4(sc, td->status_reg);
 529
 530         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 531
 532         if (csr & AT91_UDP_CSR_RXSETUP) {
 533                 /*
 534                  * The current transfer was aborted
 535                  * by the USB Host
 536                  */
 537                 td->error = 1;
 538                 return (0);             /* complete */
 539         }
 540         /* Make sure that "STALLSENT" gets cleared */
 541         temp = csr;
 542         temp &= AT91_UDP_CSR_STALLSENT;
 543
 544         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 545                 if (temp) {
 546                         /* write command */
 547                         AT91_CSR_ACK(csr, temp);
 548                         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 549                 }
 550                 return (1);             /* not complete */
 551         } else {
 552                 /* clear TXCOMP and set TXPKTRDY */
 553                 temp |= (AT91_UDP_CSR_TXCOMP |
 554                     AT91_UDP_CSR_TXPKTRDY);
 555         }
 556
 557         count = td->max_packet_size;
 558         if (td->remainder < count) {
 559                 /* we have a short packet */
 560                 td->short_pkt = 1;
 561                 count = td->remainder;
 562         }
 563         while (count > 0) {
 564                 usbd_get_page(td->pc, td->offset, &buf_res);
 565
 566                 /* get correct length */
 567                 if (buf_res.length > count) {
 568                         buf_res.length = count;
 569                 }
 570                 /* transmit data */
 571                 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 572                     td->fifo_reg, buf_res.buffer, buf_res.length);
 573
 574                 /* update counters */
 575                 count -= buf_res.length;
 576                 td->offset += buf_res.length;
 577                 td->remainder -= buf_res.length;
 578         }
 579
 580         /* write command */
 581         AT91_CSR_ACK(csr, temp);
 582         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 583
 584         /* check remainder */
 585         if (td->remainder == 0) {
 586                 if (td->short_pkt) {
 587                         return (0);     /* complete */
 588                 }
 589                 /* else we need to transmit a short packet */
 590         }
 591         if (--to) {
 592                 goto repeat;
 593         }
 594         return (1);                     /* not complete */
 595 }
 596
 597 static uint8_t
 598 at91dci_data_tx_sync(struct at91dci_softc *sc, struct at91dci_td *td)
 599 {
 600         uint32_t csr;
 601         uint32_t temp;
 602
 603         /* read out FIFO status */
 604         csr = AT91_UDP_READ_4(sc, td->status_reg);
 605
 606         DPRINTFN(5, "csr=0x%08x\n", csr);
 607
 608         if (csr & AT91_UDP_CSR_RXSETUP) {
 609                 DPRINTFN(5, "faking complete\n");
 610                 /* Race condition */
 611                 return (0);             /* complete */
 612         }
 613         temp = csr;
 614         temp &= (AT91_UDP_CSR_STALLSENT |
 615             AT91_UDP_CSR_TXCOMP);
 616
 617         /* check status */
 618         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 619                 goto not_complete;
 620         }
 621         if (!(csr & AT91_UDP_CSR_TXCOMP)) {
 622                 goto not_complete;
 623         }
 624         if (td->status_reg == AT91_UDP_CSR(0) && sc->sc_dv_addr != 0xFF) {
 625                 /*
 626                  * The AT91 has a special requirement with regard to
 627                  * setting the address and that is to write the new
 628                  * address before clearing TXCOMP:
 629                  */
 630                 at91dci_set_address(sc, sc->sc_dv_addr);
 631         }
 632         /* write command */
 633         AT91_CSR_ACK(csr, temp);
 634         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 635
 636         return (0);                     /* complete */
 637
 638 not_complete:
 639         if (temp) {
 640                 /* write command */
 641                 AT91_CSR_ACK(csr, temp);
 642                 AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 643         }
 644         return (1);                     /* not complete */
 645 }
 646
 647 static void
 648 at91dci_xfer_do_fifo(struct usb_xfer *xfer)
 649 {
 650         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 651         struct at91dci_td *td;
 652         uint8_t temp;
 653
 654         DPRINTFN(9, "\n");
 655
 656         td = xfer->td_transfer_cache;
 657         if (td == NULL)
 658                 return;
 659
 660         while (1) {
 661                 if ((td->func) (sc, td)) {
 662                         /* operation in progress */
 663                         break;
 664                 }
 665                 if (((void *)td) == xfer->td_transfer_last) {
 666                         goto done;
 667                 }
 668                 if (td->error) {
 669                         goto done;
 670                 } else if (td->remainder > 0) {
 671                         /*
 672                          * We had a short transfer. If there is no alternate
 673                          * next, stop processing !
 674                          */
 675                         if (!td->alt_next) {
 676                                 goto done;
 677                         }
 678                 }
 679                 /*
 680                  * Fetch the next transfer descriptor and transfer
 681                  * some flags to the next transfer descriptor
 682                  */
 683                 temp = 0;
 684                 if (td->fifo_bank)
 685                         temp |= 1;
 686                 td = td->obj_next;
 687                 xfer->td_transfer_cache = td;
 688                 if (temp & 1)
 689                         td->fifo_bank = 1;
 690         }
 691         return;
 692
 693 done:
 694         temp = (xfer->endpointno & UE_ADDR);
 695
 696         /* update FIFO bank flag and multi buffer */
 697         if (td->fifo_bank) {
 698                 sc->sc_ep_flags[temp].fifo_bank = 1;
 699         } else {
 700                 sc->sc_ep_flags[temp].fifo_bank = 0;
 701         }
 702
 703         /* compute all actual lengths */
 704         xfer->td_transfer_cache = NULL;
 705         sc->sc_xfer_complete = 1;
 706 }
 707
 708 static uint8_t
 709 at91dci_xfer_do_complete(struct usb_xfer *xfer)
 710 {
 711         struct at91dci_td *td;
 712
 713         DPRINTFN(9, "\n");
 714         td = xfer->td_transfer_cache;
 715         if (td == NULL) {
 716                 /* compute all actual lengths */
 717                 at91dci_standard_done(xfer);
 718                 return(1);
 719         }
 720         return (0);
 721 }
 722
 723 static void
 724 at91dci_interrupt_poll_locked(struct at91dci_softc *sc)
 725 {
 726         struct usb_xfer *xfer;
 727
 728         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
 729                 at91dci_xfer_do_fifo(xfer);
 730 }
 731
 732 static void
 733 at91dci_interrupt_complete_locked(struct at91dci_softc *sc)
 734 {
 735         struct usb_xfer *xfer;
 736 repeat:
 737         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 738                 if (at91dci_xfer_do_complete(xfer))
 739                         goto repeat;
 740         }
 741 }
 742
 743 void
 744 at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on)
 745 {
 746         DPRINTFN(5, "vbus = %u\n", is_on);
 747
 748         if (is_on) {
 749                 if (!sc->sc_flags.status_vbus) {
 750                         sc->sc_flags.status_vbus = 1;
 751
 752                         /* complete root HUB interrupt endpoint */
 753                         at91dci_root_intr(sc);
 754                 }
 755         } else {
 756                 if (sc->sc_flags.status_vbus) {
 757                         sc->sc_flags.status_vbus = 0;
 758                         sc->sc_flags.status_bus_reset = 0;
 759                         sc->sc_flags.status_suspend = 0;
 760                         sc->sc_flags.change_suspend = 0;
 761                         sc->sc_flags.change_connect = 1;
 762
 763                         /* complete root HUB interrupt endpoint */
 764                         at91dci_root_intr(sc);
 765                 }
 766         }
 767 }
 768
 769 int
 770 at91dci_filter_interrupt(void *arg)
 771 {
 772         struct at91dci_softc *sc = arg;
 773         int retval = FILTER_HANDLED;
 774         uint32_t status;
 775
 776         USB_BUS_SPIN_LOCK(&sc->sc_bus);
 777
 778         status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
 779         status &= AT91_UDP_INT_DEFAULT;
 780
 781         if (status & AT9100_DCI_THREAD_IRQ)
 782                 retval = FILTER_SCHEDULE_THREAD;
 783
 784         /* acknowledge interrupts */
 785         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status & ~AT9100_DCI_THREAD_IRQ);
 786
 787         /* poll FIFOs, if any */
 788         at91dci_interrupt_poll_locked(sc);
 789
 790         if (sc->sc_xfer_complete != 0)
 791                 retval = FILTER_SCHEDULE_THREAD;
 792
 793         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
 794
 795         return (retval);
 796 }
 797
 798 void
 799 at91dci_interrupt(void *arg)
 800 {
 801         struct at91dci_softc *sc = arg;
 802         uint32_t status;
 803
 804         USB_BUS_LOCK(&sc->sc_bus);
 805         USB_BUS_SPIN_LOCK(&sc->sc_bus);
 806
 807         status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
 808         status &= AT9100_DCI_THREAD_IRQ;
 809
 810         /* acknowledge interrupts */
 811
 812         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status);
 813
 814         /* check for any bus state change interrupts */
 815
 816         if (status & AT91_UDP_INT_BUS) {
 817
 818                 DPRINTFN(5, "real bus interrupt 0x%08x\n", status);
 819
 820                 if (status & AT91_UDP_INT_END_BR) {
 821
 822                         /* set correct state */
 823                         sc->sc_flags.status_bus_reset = 1;
 824                         sc->sc_flags.status_suspend = 0;
 825                         sc->sc_flags.change_suspend = 0;
 826                         sc->sc_flags.change_connect = 1;
 827
 828                         /* disable resume interrupt */
 829                         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 830                             AT91_UDP_INT_RXRSM);
 831                         /* enable suspend interrupt */
 832                         AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 833                             AT91_UDP_INT_RXSUSP);
 834                 }
 835                 /*
 836                  * If RXRSM and RXSUSP is set at the same time we interpret
 837                  * that like RESUME. Resume is set when there is at least 3
 838                  * milliseconds of inactivity on the USB BUS.
 839                  */
 840                 if (status & AT91_UDP_INT_RXRSM) {
 841                         if (sc->sc_flags.status_suspend) {
 842                                 sc->sc_flags.status_suspend = 0;
 843                                 sc->sc_flags.change_suspend = 1;
 844
 845                                 /* disable resume interrupt */
 846                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 847                                     AT91_UDP_INT_RXRSM);
 848                                 /* enable suspend interrupt */
 849                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 850                                     AT91_UDP_INT_RXSUSP);
 851                         }
 852                 } else if (status & AT91_UDP_INT_RXSUSP) {
 853                         if (!sc->sc_flags.status_suspend) {
 854                                 sc->sc_flags.status_suspend = 1;
 855                                 sc->sc_flags.change_suspend = 1;
 856
 857                                 /* disable suspend interrupt */
 858                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 859                                     AT91_UDP_INT_RXSUSP);
 860
 861                                 /* enable resume interrupt */
 862                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 863                                     AT91_UDP_INT_RXRSM);
 864                         }
 865                 }
 866                 /* complete root HUB interrupt endpoint */
 867                 at91dci_root_intr(sc);
 868         }
 869
 870         if (sc->sc_xfer_complete != 0) {
 871                 sc->sc_xfer_complete = 0;
 872                 at91dci_interrupt_complete_locked(sc);
 873         }
 874         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
 875         USB_BUS_UNLOCK(&sc->sc_bus);
 876 }
 877
 878 static void
 879 at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp)
 880 {
 881         struct at91dci_td *td;
 882
 883         /* get current Transfer Descriptor */
 884         td = temp->td_next;
 885         temp->td = td;
 886
 887         /* prepare for next TD */
 888         temp->td_next = td->obj_next;
 889
 890         /* fill out the Transfer Descriptor */
 891         td->func = temp->func;
 892         td->pc = temp->pc;
 893         td->offset = temp->offset;
 894         td->remainder = temp->len;
 895         td->fifo_bank = 0;
 896         td->error = 0;
 897         td->did_stall = temp->did_stall;
 898         td->short_pkt = temp->short_pkt;
 899         td->alt_next = temp->setup_alt_next;
 900 }
 901
 902 static void
 903 at91dci_setup_standard_chain(struct usb_xfer *xfer)
 904 {
 905         struct at91dci_std_temp temp;
 906         struct at91dci_softc *sc;
 907         struct at91dci_td *td;
 908         uint32_t x;
 909         uint8_t ep_no;
 910         uint8_t need_sync;
 911
 912         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 913             xfer->address, UE_GET_ADDR(xfer->endpointno),
 914             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 915
 916         temp.max_frame_size = xfer->max_frame_size;
 917
 918         td = xfer->td_start[0];
 919         xfer->td_transfer_first = td;
 920         xfer->td_transfer_cache = td;
 921
 922         /* setup temp */
 923
 924         temp.pc = NULL;
 925         temp.td = NULL;
 926         temp.td_next = xfer->td_start[0];
 927         temp.offset = 0;
 928         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
 929             xfer->flags_int.isochronous_xfr;
 930         temp.did_stall = !xfer->flags_int.control_stall;
 931
 932         sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 933         ep_no = (xfer->endpointno & UE_ADDR);
 934
 935         /* check if we should prepend a setup message */
 936
 937         if (xfer->flags_int.control_xfr) {
 938                 if (xfer->flags_int.control_hdr) {
 939
 940                         temp.func = &at91dci_setup_rx;
 941                         temp.len = xfer->frlengths[0];
 942                         temp.pc = xfer->frbuffers + 0;
 943                         temp.short_pkt = temp.len ? 1 : 0;
 944                         /* check for last frame */
 945                         if (xfer->nframes == 1) {
 946                                 /* no STATUS stage yet, SETUP is last */
 947                                 if (xfer->flags_int.control_act)
 948                                         temp.setup_alt_next = 0;
 949                         }
 950
 951                         at91dci_setup_standard_chain_sub(&temp);
 952                 }
 953                 x = 1;
 954         } else {
 955                 x = 0;
 956         }
 957
 958         if (x != xfer->nframes) {
 959                 if (xfer->endpointno & UE_DIR_IN) {
 960                         temp.func = &at91dci_data_tx;
 961                         need_sync = 1;
 962                 } else {
 963                         temp.func = &at91dci_data_rx;
 964                         need_sync = 0;
 965                 }
 966
 967                 /* setup "pc" pointer */
 968                 temp.pc = xfer->frbuffers + x;
 969         } else {
 970                 need_sync = 0;
 971         }
 972         while (x != xfer->nframes) {
 973
 974                 /* DATA0 / DATA1 message */
 975
 976                 temp.len = xfer->frlengths[x];
 977
 978                 x++;
 979
 980                 if (x == xfer->nframes) {
 981                         if (xfer->flags_int.control_xfr) {
 982                                 if (xfer->flags_int.control_act) {
 983                                         temp.setup_alt_next = 0;
 984                                 }
 985                         } else {
 986                                 temp.setup_alt_next = 0;
 987                         }
 988                 }
 989                 if (temp.len == 0) {
 990
 991                         /* make sure that we send an USB packet */
 992
 993                         temp.short_pkt = 0;
 994
 995                 } else {
 996
 997                         /* regular data transfer */
 998
 999                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1000                 }
1001
1002                 at91dci_setup_standard_chain_sub(&temp);
1003
1004                 if (xfer->flags_int.isochronous_xfr) {
1005                         temp.offset += temp.len;
1006                 } else {
1007                         /* get next Page Cache pointer */
1008                         temp.pc = xfer->frbuffers + x;
1009                 }
1010         }
1011
1012         /* check for control transfer */
1013         if (xfer->flags_int.control_xfr) {
1014
1015                 /* always setup a valid "pc" pointer for status and sync */
1016                 temp.pc = xfer->frbuffers + 0;
1017                 temp.len = 0;
1018                 temp.short_pkt = 0;
1019                 temp.setup_alt_next = 0;
1020
1021                 /* check if we need to sync */
1022                 if (need_sync) {
1023                         /* we need a SYNC point after TX */
1024                         temp.func = &at91dci_data_tx_sync;
1025                         at91dci_setup_standard_chain_sub(&temp);
1026                 }
1027
1028                 /* check if we should append a status stage */
1029                 if (!xfer->flags_int.control_act) {
1030
1031                         /*
1032                          * Send a DATA1 message and invert the current
1033                          * endpoint direction.
1034                          */
1035                         if (xfer->endpointno & UE_DIR_IN) {
1036                                 temp.func = &at91dci_data_rx;
1037                                 need_sync = 0;
1038                         } else {
1039                                 temp.func = &at91dci_data_tx;
1040                                 need_sync = 1;
1041                         }
1042
1043                         at91dci_setup_standard_chain_sub(&temp);
1044                         if (need_sync) {
1045                                 /* we need a SYNC point after TX */
1046                                 temp.func = &at91dci_data_tx_sync;
1047                                 at91dci_setup_standard_chain_sub(&temp);
1048                         }
1049                 }
1050         }
1051
1052         /* must have at least one frame! */
1053         td = temp.td;
1054         xfer->td_transfer_last = td;
1055
1056         /* setup the correct fifo bank */
1057         if (sc->sc_ep_flags[ep_no].fifo_bank) {
1058                 td = xfer->td_transfer_first;
1059                 td->fifo_bank = 1;
1060         }
1061 }
1062
1063 static void
1064 at91dci_timeout(void *arg)
1065 {
1066         struct usb_xfer *xfer = arg;
1067
1068         DPRINTF("xfer=%p\n", xfer);
1069
1070         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1071
1072         /* transfer is transferred */
1073         at91dci_device_done(xfer, USB_ERR_TIMEOUT);
1074 }
1075
1076 static void
1077 at91dci_start_standard_chain(struct usb_xfer *xfer)
1078 {
1079         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1080
1081         DPRINTFN(9, "\n");
1082
1083         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1084
1085         /* poll one time */
1086         at91dci_xfer_do_fifo(xfer);
1087
1088         if (at91dci_xfer_do_complete(xfer) == 0) {
1089
1090                 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1091
1092                 /*
1093                  * Only enable the endpoint interrupt when we are actually
1094                  * waiting for data, hence we are dealing with level
1095                  * triggered interrupts !
1096                  */
1097                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no));
1098
1099                 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no);
1100
1101                 /* put transfer on interrupt queue */
1102                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1103
1104                 /* start timeout, if any */
1105                 if (xfer->timeout != 0) {
1106                         usbd_transfer_timeout_ms(xfer,
1107                             &at91dci_timeout, xfer->timeout);
1108                 }
1109         }
1110         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1111 }
1112
1113 static void
1114 at91dci_root_intr(struct at91dci_softc *sc)
1115 {
1116         DPRINTFN(9, "\n");
1117
1118         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1119
1120         /* set port bit */
1121         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
1122
1123         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1124             sizeof(sc->sc_hub_idata));
1125 }
1126
1127 static usb_error_t
1128 at91dci_standard_done_sub(struct usb_xfer *xfer)
1129 {
1130         struct at91dci_td *td;
1131         uint32_t len;
1132         uint8_t error;
1133
1134         DPRINTFN(9, "\n");
1135
1136         td = xfer->td_transfer_cache;
1137
1138         do {
1139                 len = td->remainder;
1140
1141                 if (xfer->aframes != xfer->nframes) {
1142                         /*
1143                          * Verify the length and subtract
1144                          * the remainder from "frlengths[]":
1145                          */
1146                         if (len > xfer->frlengths[xfer->aframes]) {
1147                                 td->error = 1;
1148                         } else {
1149                                 xfer->frlengths[xfer->aframes] -= len;
1150                         }
1151                 }
1152                 /* Check for transfer error */
1153                 if (td->error) {
1154                         /* the transfer is finished */
1155                         error = 1;
1156                         td = NULL;
1157                         break;
1158                 }
1159                 /* Check for short transfer */
1160                 if (len > 0) {
1161                         if (xfer->flags_int.short_frames_ok ||
1162                             xfer->flags_int.isochronous_xfr) {
1163                                 /* follow alt next */
1164                                 if (td->alt_next) {
1165                                         td = td->obj_next;
1166                                 } else {
1167                                         td = NULL;
1168                                 }
1169                         } else {
1170                                 /* the transfer is finished */
1171                                 td = NULL;
1172                         }
1173                         error = 0;
1174                         break;
1175                 }
1176                 td = td->obj_next;
1177
1178                 /* this USB frame is complete */
1179                 error = 0;
1180                 break;
1181
1182         } while (0);
1183
1184         /* update transfer cache */
1185
1186         xfer->td_transfer_cache = td;
1187
1188         return (error ?
1189             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1190 }
1191
1192 static void
1193 at91dci_standard_done(struct usb_xfer *xfer)
1194 {
1195         usb_error_t err = 0;
1196
1197         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1198             xfer, xfer->endpoint);
1199
1200         /* reset scanner */
1201
1202         xfer->td_transfer_cache = xfer->td_transfer_first;
1203
1204         if (xfer->flags_int.control_xfr) {
1205
1206                 if (xfer->flags_int.control_hdr) {
1207
1208                         err = at91dci_standard_done_sub(xfer);
1209                 }
1210                 xfer->aframes = 1;
1211
1212                 if (xfer->td_transfer_cache == NULL) {
1213                         goto done;
1214                 }
1215         }
1216         while (xfer->aframes != xfer->nframes) {
1217
1218                 err = at91dci_standard_done_sub(xfer);
1219                 xfer->aframes++;
1220
1221                 if (xfer->td_transfer_cache == NULL) {
1222                         goto done;
1223                 }
1224         }
1225
1226         if (xfer->flags_int.control_xfr &&
1227             !xfer->flags_int.control_act) {
1228
1229                 err = at91dci_standard_done_sub(xfer);
1230         }
1231 done:
1232         at91dci_device_done(xfer, err);
1233 }
1234
1235 /*------------------------------------------------------------------------*
1236  *      at91dci_device_done
1237  *
1238  * NOTE: this function can be called more than one time on the
1239  * same USB transfer!
1240  *------------------------------------------------------------------------*/
1241 static void
1242 at91dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1243 {
1244         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1245         uint8_t ep_no;
1246
1247         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1248
1249         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1250             xfer, xfer->endpoint, error);
1251
1252         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1253
1254         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1255                 ep_no = (xfer->endpointno & UE_ADDR);
1256
1257                 /* disable endpoint interrupt */
1258                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no));
1259
1260                 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no);
1261         }
1262
1263         /* dequeue transfer and start next transfer */
1264         usbd_transfer_done(xfer, error);
1265
1266         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1267 }
1268
1269 static void
1270 at91dci_xfer_stall(struct usb_xfer *xfer)
1271 {
1272         at91dci_device_done(xfer, USB_ERR_STALLED);
1273 }
1274
1275 static void
1276 at91dci_set_stall(struct usb_device *udev,
1277     struct usb_endpoint *ep, uint8_t *did_stall)
1278 {
1279         struct at91dci_softc *sc;
1280         uint32_t csr_val;
1281         uint8_t csr_reg;
1282
1283         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1284
1285         DPRINTFN(5, "endpoint=%p\n", ep);
1286
1287         /* set FORCESTALL */
1288         sc = AT9100_DCI_BUS2SC(udev->bus);
1289
1290         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1291         csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR);
1292         csr_reg = AT91_UDP_CSR(csr_reg);
1293         csr_val = AT91_UDP_READ_4(sc, csr_reg);
1294         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL);
1295         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1296         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1297 }
1298
1299 static void
1300 at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no,
1301     uint8_t ep_type, uint8_t ep_dir)
1302 {
1303         const struct usb_hw_ep_profile *pf;
1304         uint32_t csr_val;
1305         uint32_t temp;
1306         uint8_t csr_reg;
1307         uint8_t to;
1308
1309         if (ep_type == UE_CONTROL) {
1310                 /* clearing stall is not needed */
1311                 return;
1312         }
1313
1314         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1315
1316         /* compute CSR register offset */
1317         csr_reg = AT91_UDP_CSR(ep_no);
1318
1319         /* compute default CSR value */
1320         csr_val = 0;
1321         AT91_CSR_ACK(csr_val, 0);
1322
1323         /* disable endpoint */
1324         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1325
1326         /* get endpoint profile */
1327         at91dci_get_hw_ep_profile(NULL, &pf, ep_no);
1328
1329         /* reset FIFO */
1330         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no));
1331         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0);
1332
1333         /*
1334          * NOTE: One would assume that a FIFO reset would release the
1335          * FIFO banks as well, but it doesn't! We have to do this
1336          * manually!
1337          */
1338
1339         /* release FIFO banks, if any */
1340         for (to = 0; to != 2; to++) {
1341
1342                 /* get csr value */
1343                 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1344
1345                 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 |
1346                     AT91_UDP_CSR_RX_DATA_BK1)) {
1347                         /* clear status bits */
1348                         if (pf->support_multi_buffer) {
1349                                 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1350                                         sc->sc_ep_flags[ep_no].fifo_bank = 0;
1351                                         temp = AT91_UDP_CSR_RX_DATA_BK1;
1352                                 } else {
1353                                         sc->sc_ep_flags[ep_no].fifo_bank = 1;
1354                                         temp = AT91_UDP_CSR_RX_DATA_BK0;
1355                                 }
1356                         } else {
1357                                 temp = (AT91_UDP_CSR_RX_DATA_BK0 |
1358                                     AT91_UDP_CSR_RX_DATA_BK1);
1359                         }
1360                 } else {
1361                         temp = 0;
1362                 }
1363
1364                 /* clear FORCESTALL */
1365                 temp |= AT91_UDP_CSR_STALLSENT;
1366
1367                 AT91_CSR_ACK(csr_val, temp);
1368                 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1369         }
1370
1371         /* compute default CSR value */
1372         csr_val = 0;
1373         AT91_CSR_ACK(csr_val, 0);
1374
1375         /* enable endpoint */
1376         csr_val &= ~AT91_UDP_CSR_ET_MASK;
1377         csr_val |= AT91_UDP_CSR_EPEDS;
1378
1379         if (ep_type == UE_CONTROL) {
1380                 csr_val |= AT91_UDP_CSR_ET_CTRL;
1381         } else {
1382                 if (ep_type == UE_BULK) {
1383                         csr_val |= AT91_UDP_CSR_ET_BULK;
1384                 } else if (ep_type == UE_INTERRUPT) {
1385                         csr_val |= AT91_UDP_CSR_ET_INT;
1386                 } else {
1387                         csr_val |= AT91_UDP_CSR_ET_ISO;
1388                 }
1389                 if (ep_dir & UE_DIR_IN) {
1390                         csr_val |= AT91_UDP_CSR_ET_DIR_IN;
1391                 }
1392         }
1393
1394         /* enable endpoint */
1395         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val);
1396
1397         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1398 }
1399
1400 static void
1401 at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1402 {
1403         struct at91dci_softc *sc;
1404         struct usb_endpoint_descriptor *ed;
1405
1406         DPRINTFN(5, "endpoint=%p\n", ep);
1407
1408         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1409
1410         /* check mode */
1411         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1412                 /* not supported */
1413                 return;
1414         }
1415         /* get softc */
1416         sc = AT9100_DCI_BUS2SC(udev->bus);
1417
1418         /* get endpoint descriptor */
1419         ed = ep->edesc;
1420
1421         /* reset endpoint */
1422         at91dci_clear_stall_sub(sc,
1423             (ed->bEndpointAddress & UE_ADDR),
1424             (ed->bmAttributes & UE_XFERTYPE),
1425             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1426 }
1427
1428 usb_error_t
1429 at91dci_init(struct at91dci_softc *sc)
1430 {
1431         uint32_t csr_val;
1432         uint8_t n;
1433
1434         DPRINTF("start\n");
1435
1436         /* set up the bus structure */
1437         sc->sc_bus.usbrev = USB_REV_1_1;
1438         sc->sc_bus.methods = &at91dci_bus_methods;
1439
1440         USB_BUS_LOCK(&sc->sc_bus);
1441
1442         /* turn on clocks */
1443
1444         if (sc->sc_clocks_on) {
1445                 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1446         }
1447         /* wait a little for things to stabilise */
1448         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1449
1450         /* disable and clear all interrupts */
1451
1452         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1453         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1454
1455         /* compute default CSR value */
1456
1457         csr_val = 0;
1458         AT91_CSR_ACK(csr_val, 0);
1459
1460         /* disable all endpoints */
1461
1462         for (n = 0; n != AT91_UDP_EP_MAX; n++) {
1463
1464                 /* disable endpoint */
1465                 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val);
1466         }
1467
1468         /* enable the control endpoint */
1469
1470         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL |
1471             AT91_UDP_CSR_EPEDS);
1472
1473         /* write to FIFO control register */
1474
1475         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val);
1476
1477         /* enable the interrupts we want */
1478
1479         AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS);
1480
1481         /* turn off clocks */
1482
1483         at91dci_clocks_off(sc);
1484
1485         USB_BUS_UNLOCK(&sc->sc_bus);
1486
1487         /* catch any lost interrupts */
1488
1489         at91dci_do_poll(&sc->sc_bus);
1490
1491         return (0);                     /* success */
1492 }
1493
1494 void
1495 at91dci_uninit(struct at91dci_softc *sc)
1496 {
1497         USB_BUS_LOCK(&sc->sc_bus);
1498
1499         /* disable and clear all interrupts */
1500         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1501         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1502
1503         sc->sc_flags.port_powered = 0;
1504         sc->sc_flags.status_vbus = 0;
1505         sc->sc_flags.status_bus_reset = 0;
1506         sc->sc_flags.status_suspend = 0;
1507         sc->sc_flags.change_suspend = 0;
1508         sc->sc_flags.change_connect = 1;
1509
1510         at91dci_pull_down(sc);
1511         at91dci_clocks_off(sc);
1512         USB_BUS_UNLOCK(&sc->sc_bus);
1513 }
1514
1515 static void
1516 at91dci_suspend(struct at91dci_softc *sc)
1517 {
1518         /* TODO */
1519 }
1520
1521 static void
1522 at91dci_resume(struct at91dci_softc *sc)
1523 {
1524         /* TODO */
1525 }
1526
1527 static void
1528 at91dci_do_poll(struct usb_bus *bus)
1529 {
1530         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
1531
1532         USB_BUS_LOCK(&sc->sc_bus);
1533         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1534         at91dci_interrupt_poll_locked(sc);
1535         at91dci_interrupt_complete_locked(sc);
1536         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1537         USB_BUS_UNLOCK(&sc->sc_bus);
1538 }
1539
1540 /*------------------------------------------------------------------------*
1541  * at91dci bulk support
1542  *------------------------------------------------------------------------*/
1543 static void
1544 at91dci_device_bulk_open(struct usb_xfer *xfer)
1545 {
1546         return;
1547 }
1548
1549 static void
1550 at91dci_device_bulk_close(struct usb_xfer *xfer)
1551 {
1552         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1553 }
1554
1555 static void
1556 at91dci_device_bulk_enter(struct usb_xfer *xfer)
1557 {
1558         return;
1559 }
1560
1561 static void
1562 at91dci_device_bulk_start(struct usb_xfer *xfer)
1563 {
1564         /* setup TDs */
1565         at91dci_setup_standard_chain(xfer);
1566         at91dci_start_standard_chain(xfer);
1567 }
1568
1569 static const struct usb_pipe_methods at91dci_device_bulk_methods =
1570 {
1571         .open = at91dci_device_bulk_open,
1572         .close = at91dci_device_bulk_close,
1573         .enter = at91dci_device_bulk_enter,
1574         .start = at91dci_device_bulk_start,
1575 };
1576
1577 /*------------------------------------------------------------------------*
1578  * at91dci control support
1579  *------------------------------------------------------------------------*/
1580 static void
1581 at91dci_device_ctrl_open(struct usb_xfer *xfer)
1582 {
1583         return;
1584 }
1585
1586 static void
1587 at91dci_device_ctrl_close(struct usb_xfer *xfer)
1588 {
1589         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1590 }
1591
1592 static void
1593 at91dci_device_ctrl_enter(struct usb_xfer *xfer)
1594 {
1595         return;
1596 }
1597
1598 static void
1599 at91dci_device_ctrl_start(struct usb_xfer *xfer)
1600 {
1601         /* setup TDs */
1602         at91dci_setup_standard_chain(xfer);
1603         at91dci_start_standard_chain(xfer);
1604 }
1605
1606 static const struct usb_pipe_methods at91dci_device_ctrl_methods =
1607 {
1608         .open = at91dci_device_ctrl_open,
1609         .close = at91dci_device_ctrl_close,
1610         .enter = at91dci_device_ctrl_enter,
1611         .start = at91dci_device_ctrl_start,
1612 };
1613
1614 /*------------------------------------------------------------------------*
1615  * at91dci interrupt support
1616  *------------------------------------------------------------------------*/
1617 static void
1618 at91dci_device_intr_open(struct usb_xfer *xfer)
1619 {
1620         return;
1621 }
1622
1623 static void
1624 at91dci_device_intr_close(struct usb_xfer *xfer)
1625 {
1626         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1627 }
1628
1629 static void
1630 at91dci_device_intr_enter(struct usb_xfer *xfer)
1631 {
1632         return;
1633 }
1634
1635 static void
1636 at91dci_device_intr_start(struct usb_xfer *xfer)
1637 {
1638         /* setup TDs */
1639         at91dci_setup_standard_chain(xfer);
1640         at91dci_start_standard_chain(xfer);
1641 }
1642
1643 static const struct usb_pipe_methods at91dci_device_intr_methods =
1644 {
1645         .open = at91dci_device_intr_open,
1646         .close = at91dci_device_intr_close,
1647         .enter = at91dci_device_intr_enter,
1648         .start = at91dci_device_intr_start,
1649 };
1650
1651 /*------------------------------------------------------------------------*
1652  * at91dci full speed isochronous support
1653  *------------------------------------------------------------------------*/
1654 static void
1655 at91dci_device_isoc_fs_open(struct usb_xfer *xfer)
1656 {
1657         return;
1658 }
1659
1660 static void
1661 at91dci_device_isoc_fs_close(struct usb_xfer *xfer)
1662 {
1663         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1664 }
1665
1666 static void
1667 at91dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1668 {
1669         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1670         uint32_t temp;
1671         uint32_t nframes;
1672
1673         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1674             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1675
1676         /* get the current frame index */
1677
1678         nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM);
1679
1680         /*
1681          * check if the frame index is within the window where the frames
1682          * will be inserted
1683          */
1684         temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK;
1685
1686         if ((xfer->endpoint->is_synced == 0) ||
1687             (temp < xfer->nframes)) {
1688                 /*
1689                  * If there is data underflow or the endpoint queue is
1690                  * empty we schedule the transfer a few frames ahead
1691                  * of the current frame position. Else two isochronous
1692                  * transfers might overlap.
1693                  */
1694                 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK;
1695                 xfer->endpoint->is_synced = 1;
1696                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1697         }
1698         /*
1699          * compute how many milliseconds the insertion is ahead of the
1700          * current frame position:
1701          */
1702         temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK;
1703
1704         /*
1705          * pre-compute when the isochronous transfer will be finished:
1706          */
1707         xfer->isoc_time_complete =
1708             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1709             xfer->nframes;
1710
1711         /* compute frame number for next insertion */
1712         xfer->endpoint->isoc_next += xfer->nframes;
1713
1714         /* setup TDs */
1715         at91dci_setup_standard_chain(xfer);
1716 }
1717
1718 static void
1719 at91dci_device_isoc_fs_start(struct usb_xfer *xfer)
1720 {
1721         /* start TD chain */
1722         at91dci_start_standard_chain(xfer);
1723 }
1724
1725 static const struct usb_pipe_methods at91dci_device_isoc_fs_methods =
1726 {
1727         .open = at91dci_device_isoc_fs_open,
1728         .close = at91dci_device_isoc_fs_close,
1729         .enter = at91dci_device_isoc_fs_enter,
1730         .start = at91dci_device_isoc_fs_start,
1731 };
1732
1733 /*------------------------------------------------------------------------*
1734  * at91dci root control support
1735  *------------------------------------------------------------------------*
1736  * Simulate a hardware HUB by handling all the necessary requests.
1737  *------------------------------------------------------------------------*/
1738
1739 static const struct usb_device_descriptor at91dci_devd = {
1740         .bLength = sizeof(struct usb_device_descriptor),
1741         .bDescriptorType = UDESC_DEVICE,
1742         .bcdUSB = {0x00, 0x02},
1743         .bDeviceClass = UDCLASS_HUB,
1744         .bDeviceSubClass = UDSUBCLASS_HUB,
1745         .bDeviceProtocol = UDPROTO_FSHUB,
1746         .bMaxPacketSize = 64,
1747         .bcdDevice = {0x00, 0x01},
1748         .iManufacturer = 1,
1749         .iProduct = 2,
1750         .bNumConfigurations = 1,
1751 };
1752
1753 static const struct at91dci_config_desc at91dci_confd = {
1754         .confd = {
1755                 .bLength = sizeof(struct usb_config_descriptor),
1756                 .bDescriptorType = UDESC_CONFIG,
1757                 .wTotalLength[0] = sizeof(at91dci_confd),
1758                 .bNumInterface = 1,
1759                 .bConfigurationValue = 1,
1760                 .iConfiguration = 0,
1761                 .bmAttributes = UC_SELF_POWERED,
1762                 .bMaxPower = 0,
1763         },
1764         .ifcd = {
1765                 .bLength = sizeof(struct usb_interface_descriptor),
1766                 .bDescriptorType = UDESC_INTERFACE,
1767                 .bNumEndpoints = 1,
1768                 .bInterfaceClass = UICLASS_HUB,
1769                 .bInterfaceSubClass = UISUBCLASS_HUB,
1770                 .bInterfaceProtocol = 0,
1771         },
1772         .endpd = {
1773                 .bLength = sizeof(struct usb_endpoint_descriptor),
1774                 .bDescriptorType = UDESC_ENDPOINT,
1775                 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT),
1776                 .bmAttributes = UE_INTERRUPT,
1777                 .wMaxPacketSize[0] = 8,
1778                 .bInterval = 255,
1779         },
1780 };
1781
1782 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1783
1784 static const struct usb_hub_descriptor_min at91dci_hubd = {
1785         .bDescLength = sizeof(at91dci_hubd),
1786         .bDescriptorType = UDESC_HUB,
1787         .bNbrPorts = 1,
1788         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1789         .bPwrOn2PwrGood = 50,
1790         .bHubContrCurrent = 0,
1791         .DeviceRemovable = {0},         /* port is removable */
1792 };
1793
1794 #define STRING_VENDOR \
1795   "A\0T\0M\0E\0L"
1796
1797 #define STRING_PRODUCT \
1798   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1799
1800 USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor);
1801 USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product);
1802
1803 static usb_error_t
1804 at91dci_roothub_exec(struct usb_device *udev,
1805     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1806 {
1807         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
1808         const void *ptr;
1809         uint16_t len;
1810         uint16_t value;
1811         uint16_t index;
1812         usb_error_t err;
1813
1814         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1815
1816         /* buffer reset */
1817         ptr = (const void *)&sc->sc_hub_temp;
1818         len = 0;
1819         err = 0;
1820
1821         value = UGETW(req->wValue);
1822         index = UGETW(req->wIndex);
1823
1824         /* demultiplex the control request */
1825
1826         switch (req->bmRequestType) {
1827         case UT_READ_DEVICE:
1828                 switch (req->bRequest) {
1829                 case UR_GET_DESCRIPTOR:
1830                         goto tr_handle_get_descriptor;
1831                 case UR_GET_CONFIG:
1832                         goto tr_handle_get_config;
1833                 case UR_GET_STATUS:
1834                         goto tr_handle_get_status;
1835                 default:
1836                         goto tr_stalled;
1837                 }
1838                 break;
1839
1840         case UT_WRITE_DEVICE:
1841                 switch (req->bRequest) {
1842                 case UR_SET_ADDRESS:
1843                         goto tr_handle_set_address;
1844                 case UR_SET_CONFIG:
1845                         goto tr_handle_set_config;
1846                 case UR_CLEAR_FEATURE:
1847                         goto tr_valid;  /* nop */
1848                 case UR_SET_DESCRIPTOR:
1849                         goto tr_valid;  /* nop */
1850                 case UR_SET_FEATURE:
1851                 default:
1852                         goto tr_stalled;
1853                 }
1854                 break;
1855
1856         case UT_WRITE_ENDPOINT:
1857                 switch (req->bRequest) {
1858                 case UR_CLEAR_FEATURE:
1859                         switch (UGETW(req->wValue)) {
1860                         case UF_ENDPOINT_HALT:
1861                                 goto tr_handle_clear_halt;
1862                         case UF_DEVICE_REMOTE_WAKEUP:
1863                                 goto tr_handle_clear_wakeup;
1864                         default:
1865                                 goto tr_stalled;
1866                         }
1867                         break;
1868                 case UR_SET_FEATURE:
1869                         switch (UGETW(req->wValue)) {
1870                         case UF_ENDPOINT_HALT:
1871                                 goto tr_handle_set_halt;
1872                         case UF_DEVICE_REMOTE_WAKEUP:
1873                                 goto tr_handle_set_wakeup;
1874                         default:
1875                                 goto tr_stalled;
1876                         }
1877                         break;
1878                 case UR_SYNCH_FRAME:
1879                         goto tr_valid;  /* nop */
1880                 default:
1881                         goto tr_stalled;
1882                 }
1883                 break;
1884
1885         case UT_READ_ENDPOINT:
1886                 switch (req->bRequest) {
1887                 case UR_GET_STATUS:
1888                         goto tr_handle_get_ep_status;
1889                 default:
1890                         goto tr_stalled;
1891                 }
1892                 break;
1893
1894         case UT_WRITE_INTERFACE:
1895                 switch (req->bRequest) {
1896                 case UR_SET_INTERFACE:
1897                         goto tr_handle_set_interface;
1898                 case UR_CLEAR_FEATURE:
1899                         goto tr_valid;  /* nop */
1900                 case UR_SET_FEATURE:
1901                 default:
1902                         goto tr_stalled;
1903                 }
1904                 break;
1905
1906         case UT_READ_INTERFACE:
1907                 switch (req->bRequest) {
1908                 case UR_GET_INTERFACE:
1909                         goto tr_handle_get_interface;
1910                 case UR_GET_STATUS:
1911                         goto tr_handle_get_iface_status;
1912                 default:
1913                         goto tr_stalled;
1914                 }
1915                 break;
1916
1917         case UT_WRITE_CLASS_INTERFACE:
1918         case UT_WRITE_VENDOR_INTERFACE:
1919                 /* XXX forward */
1920                 break;
1921
1922         case UT_READ_CLASS_INTERFACE:
1923         case UT_READ_VENDOR_INTERFACE:
1924                 /* XXX forward */
1925                 break;
1926
1927         case UT_WRITE_CLASS_DEVICE:
1928                 switch (req->bRequest) {
1929                 case UR_CLEAR_FEATURE:
1930                         goto tr_valid;
1931                 case UR_SET_DESCRIPTOR:
1932                 case UR_SET_FEATURE:
1933                         break;
1934                 default:
1935                         goto tr_stalled;
1936                 }
1937                 break;
1938
1939         case UT_WRITE_CLASS_OTHER:
1940                 switch (req->bRequest) {
1941                 case UR_CLEAR_FEATURE:
1942                         goto tr_handle_clear_port_feature;
1943                 case UR_SET_FEATURE:
1944                         goto tr_handle_set_port_feature;
1945                 case UR_CLEAR_TT_BUFFER:
1946                 case UR_RESET_TT:
1947                 case UR_STOP_TT:
1948                         goto tr_valid;
1949
1950                 default:
1951                         goto tr_stalled;
1952                 }
1953                 break;
1954
1955         case UT_READ_CLASS_OTHER:
1956                 switch (req->bRequest) {
1957                 case UR_GET_TT_STATE:
1958                         goto tr_handle_get_tt_state;
1959                 case UR_GET_STATUS:
1960                         goto tr_handle_get_port_status;
1961                 default:
1962                         goto tr_stalled;
1963                 }
1964                 break;
1965
1966         case UT_READ_CLASS_DEVICE:
1967                 switch (req->bRequest) {
1968                 case UR_GET_DESCRIPTOR:
1969                         goto tr_handle_get_class_descriptor;
1970                 case UR_GET_STATUS:
1971                         goto tr_handle_get_class_status;
1972
1973                 default:
1974                         goto tr_stalled;
1975                 }
1976                 break;
1977         default:
1978                 goto tr_stalled;
1979         }
1980         goto tr_valid;
1981
1982 tr_handle_get_descriptor:
1983         switch (value >> 8) {
1984         case UDESC_DEVICE:
1985                 if (value & 0xff) {
1986                         goto tr_stalled;
1987                 }
1988                 len = sizeof(at91dci_devd);
1989                 ptr = (const void *)&at91dci_devd;
1990                 goto tr_valid;
1991         case UDESC_CONFIG:
1992                 if (value & 0xff) {
1993                         goto tr_stalled;
1994                 }
1995                 len = sizeof(at91dci_confd);
1996                 ptr = (const void *)&at91dci_confd;
1997                 goto tr_valid;
1998         case UDESC_STRING:
1999                 switch (value & 0xff) {
2000                 case 0:         /* Language table */
2001                         len = sizeof(usb_string_lang_en);
2002                         ptr = (const void *)&usb_string_lang_en;
2003                         goto tr_valid;
2004
2005                 case 1:         /* Vendor */
2006                         len = sizeof(at91dci_vendor);
2007                         ptr = (const void *)&at91dci_vendor;
2008                         goto tr_valid;
2009
2010                 case 2:         /* Product */
2011                         len = sizeof(at91dci_product);
2012                         ptr = (const void *)&at91dci_product;
2013                         goto tr_valid;
2014                 default:
2015                         break;
2016                 }
2017                 break;
2018         default:
2019                 goto tr_stalled;
2020         }
2021         goto tr_stalled;
2022
2023 tr_handle_get_config:
2024         len = 1;
2025         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2026         goto tr_valid;
2027
2028 tr_handle_get_status:
2029         len = 2;
2030         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2031         goto tr_valid;
2032
2033 tr_handle_set_address:
2034         if (value & 0xFF00) {
2035                 goto tr_stalled;
2036         }
2037         sc->sc_rt_addr = value;
2038         goto tr_valid;
2039
2040 tr_handle_set_config:
2041         if (value >= 2) {
2042                 goto tr_stalled;
2043         }
2044         sc->sc_conf = value;
2045         goto tr_valid;
2046
2047 tr_handle_get_interface:
2048         len = 1;
2049         sc->sc_hub_temp.wValue[0] = 0;
2050         goto tr_valid;
2051
2052 tr_handle_get_tt_state:
2053 tr_handle_get_class_status:
2054 tr_handle_get_iface_status:
2055 tr_handle_get_ep_status:
2056         len = 2;
2057         USETW(sc->sc_hub_temp.wValue, 0);
2058         goto tr_valid;
2059
2060 tr_handle_set_halt:
2061 tr_handle_set_interface:
2062 tr_handle_set_wakeup:
2063 tr_handle_clear_wakeup:
2064 tr_handle_clear_halt:
2065         goto tr_valid;
2066
2067 tr_handle_clear_port_feature:
2068         if (index != 1) {
2069                 goto tr_stalled;
2070         }
2071         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2072
2073         switch (value) {
2074         case UHF_PORT_SUSPEND:
2075                 at91dci_wakeup_peer(sc);
2076                 break;
2077
2078         case UHF_PORT_ENABLE:
2079                 sc->sc_flags.port_enabled = 0;
2080                 break;
2081
2082         case UHF_PORT_TEST:
2083         case UHF_PORT_INDICATOR:
2084         case UHF_C_PORT_ENABLE:
2085         case UHF_C_PORT_OVER_CURRENT:
2086         case UHF_C_PORT_RESET:
2087                 /* nops */
2088                 break;
2089         case UHF_PORT_POWER:
2090                 sc->sc_flags.port_powered = 0;
2091                 at91dci_pull_down(sc);
2092                 at91dci_clocks_off(sc);
2093                 break;
2094         case UHF_C_PORT_CONNECTION:
2095                 sc->sc_flags.change_connect = 0;
2096                 break;
2097         case UHF_C_PORT_SUSPEND:
2098                 sc->sc_flags.change_suspend = 0;
2099                 break;
2100         default:
2101                 err = USB_ERR_IOERROR;
2102                 goto done;
2103         }
2104         goto tr_valid;
2105
2106 tr_handle_set_port_feature:
2107         if (index != 1) {
2108                 goto tr_stalled;
2109         }
2110         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2111
2112         switch (value) {
2113         case UHF_PORT_ENABLE:
2114                 sc->sc_flags.port_enabled = 1;
2115                 break;
2116         case UHF_PORT_SUSPEND:
2117         case UHF_PORT_RESET:
2118         case UHF_PORT_TEST:
2119         case UHF_PORT_INDICATOR:
2120                 /* nops */
2121                 break;
2122         case UHF_PORT_POWER:
2123                 sc->sc_flags.port_powered = 1;
2124                 break;
2125         default:
2126                 err = USB_ERR_IOERROR;
2127                 goto done;
2128         }
2129         goto tr_valid;
2130
2131 tr_handle_get_port_status:
2132
2133         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2134
2135         if (index != 1) {
2136                 goto tr_stalled;
2137         }
2138         if (sc->sc_flags.status_vbus) {
2139                 at91dci_clocks_on(sc);
2140                 at91dci_pull_up(sc);
2141         } else {
2142                 at91dci_pull_down(sc);
2143                 at91dci_clocks_off(sc);
2144         }
2145
2146         /* Select FULL-speed and Device Side Mode */
2147
2148         value = UPS_PORT_MODE_DEVICE;
2149
2150         if (sc->sc_flags.port_powered) {
2151                 value |= UPS_PORT_POWER;
2152         }
2153         if (sc->sc_flags.port_enabled) {
2154                 value |= UPS_PORT_ENABLED;
2155         }
2156         if (sc->sc_flags.status_vbus &&
2157             sc->sc_flags.status_bus_reset) {
2158                 value |= UPS_CURRENT_CONNECT_STATUS;
2159         }
2160         if (sc->sc_flags.status_suspend) {
2161                 value |= UPS_SUSPEND;
2162         }
2163         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2164
2165         value = 0;
2166
2167         if (sc->sc_flags.change_connect) {
2168                 value |= UPS_C_CONNECT_STATUS;
2169
2170                 if (sc->sc_flags.status_vbus &&
2171                     sc->sc_flags.status_bus_reset) {
2172                         /* reset endpoint flags */
2173                         memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags));
2174                 }
2175         }
2176         if (sc->sc_flags.change_suspend) {
2177                 value |= UPS_C_SUSPEND;
2178         }
2179         USETW(sc->sc_hub_temp.ps.wPortChange, value);
2180         len = sizeof(sc->sc_hub_temp.ps);
2181         goto tr_valid;
2182
2183 tr_handle_get_class_descriptor:
2184         if (value & 0xFF) {
2185                 goto tr_stalled;
2186         }
2187         ptr = (const void *)&at91dci_hubd;
2188         len = sizeof(at91dci_hubd);
2189         goto tr_valid;
2190
2191 tr_stalled:
2192         err = USB_ERR_STALLED;
2193 tr_valid:
2194 done:
2195         *plength = len;
2196         *pptr = ptr;
2197         return (err);
2198 }
2199
2200 static void
2201 at91dci_xfer_setup(struct usb_setup_params *parm)
2202 {
2203         const struct usb_hw_ep_profile *pf;
2204         struct at91dci_softc *sc;
2205         struct usb_xfer *xfer;
2206         void *last_obj;
2207         uint32_t ntd;
2208         uint32_t n;
2209         uint8_t ep_no;
2210
2211         sc = AT9100_DCI_BUS2SC(parm->udev->bus);
2212         xfer = parm->curr_xfer;
2213
2214         /*
2215          * NOTE: This driver does not use any of the parameters that
2216          * are computed from the following values. Just set some
2217          * reasonable dummies:
2218          */
2219         parm->hc_max_packet_size = 0x500;
2220         parm->hc_max_packet_count = 1;
2221         parm->hc_max_frame_size = 0x500;
2222
2223         usbd_transfer_setup_sub(parm);
2224
2225         /*
2226          * compute maximum number of TDs
2227          */
2228         if (parm->methods == &at91dci_device_ctrl_methods) {
2229
2230                 ntd = xfer->nframes + 1 /* STATUS */ + 1        /* SYNC 1 */
2231                     + 1 /* SYNC 2 */ ;
2232
2233         } else if (parm->methods == &at91dci_device_bulk_methods) {
2234
2235                 ntd = xfer->nframes + 1 /* SYNC */ ;
2236
2237         } else if (parm->methods == &at91dci_device_intr_methods) {
2238
2239                 ntd = xfer->nframes + 1 /* SYNC */ ;
2240
2241         } else if (parm->methods == &at91dci_device_isoc_fs_methods) {
2242
2243                 ntd = xfer->nframes + 1 /* SYNC */ ;
2244
2245         } else {
2246
2247                 ntd = 0;
2248         }
2249
2250         /*
2251          * check if "usbd_transfer_setup_sub" set an error
2252          */
2253         if (parm->err) {
2254                 return;
2255         }
2256         /*
2257          * allocate transfer descriptors
2258          */
2259         last_obj = NULL;
2260
2261         /*
2262          * get profile stuff
2263          */
2264         if (ntd) {
2265
2266                 ep_no = xfer->endpointno & UE_ADDR;
2267                 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2268
2269                 if (pf == NULL) {
2270                         /* should not happen */
2271                         parm->err = USB_ERR_INVAL;
2272                         return;
2273                 }
2274         } else {
2275                 ep_no = 0;
2276                 pf = NULL;
2277         }
2278
2279         /* align data */
2280         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2281
2282         for (n = 0; n != ntd; n++) {
2283
2284                 struct at91dci_td *td;
2285
2286                 if (parm->buf) {
2287
2288                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2289
2290                         /* init TD */
2291                         td->max_packet_size = xfer->max_packet_size;
2292                         td->status_reg = AT91_UDP_CSR(ep_no);
2293                         td->fifo_reg = AT91_UDP_FDR(ep_no);
2294                         if (pf->support_multi_buffer) {
2295                                 td->support_multi_buffer = 1;
2296                         }
2297                         td->obj_next = last_obj;
2298
2299                         last_obj = td;
2300                 }
2301                 parm->size[0] += sizeof(*td);
2302         }
2303
2304         xfer->td_start[0] = last_obj;
2305 }
2306
2307 static void
2308 at91dci_xfer_unsetup(struct usb_xfer *xfer)
2309 {
2310         return;
2311 }
2312
2313 static void
2314 at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2315     struct usb_endpoint *ep)
2316 {
2317         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
2318
2319         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2320             ep, udev->address,
2321             edesc->bEndpointAddress, udev->flags.usb_mode,
2322             sc->sc_rt_addr);
2323
2324         if (udev->device_index != sc->sc_rt_addr) {
2325
2326                 if (udev->speed != USB_SPEED_FULL) {
2327                         /* not supported */
2328                         return;
2329                 }
2330                 switch (edesc->bmAttributes & UE_XFERTYPE) {
2331                 case UE_CONTROL:
2332                         ep->methods = &at91dci_device_ctrl_methods;
2333                         break;
2334                 case UE_INTERRUPT:
2335                         ep->methods = &at91dci_device_intr_methods;
2336                         break;
2337                 case UE_ISOCHRONOUS:
2338                         ep->methods = &at91dci_device_isoc_fs_methods;
2339                         break;
2340                 case UE_BULK:
2341                         ep->methods = &at91dci_device_bulk_methods;
2342                         break;
2343                 default:
2344                         /* do nothing */
2345                         break;
2346                 }
2347         }
2348 }
2349
2350 static void
2351 at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2352 {
2353         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
2354
2355         switch (state) {
2356         case USB_HW_POWER_SUSPEND:
2357                 at91dci_suspend(sc);
2358                 break;
2359         case USB_HW_POWER_SHUTDOWN:
2360                 at91dci_uninit(sc);
2361                 break;
2362         case USB_HW_POWER_RESUME:
2363                 at91dci_resume(sc);
2364                 break;
2365         default:
2366                 break;
2367         }
2368 }
2369
2370 static const struct usb_bus_methods at91dci_bus_methods =
2371 {
2372         .endpoint_init = &at91dci_ep_init,
2373         .xfer_setup = &at91dci_xfer_setup,
2374         .xfer_unsetup = &at91dci_xfer_unsetup,
2375         .get_hw_ep_profile = &at91dci_get_hw_ep_profile,
2376         .set_stall = &at91dci_set_stall,
2377         .xfer_stall = &at91dci_xfer_stall,
2378         .clear_stall = &at91dci_clear_stall,
2379         .roothub_exec = &at91dci_roothub_exec,
2380         .xfer_poll = &at91dci_do_poll,
2381         .set_hw_power_sleep = &at91dci_set_hw_power_sleep,
2382 };