3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This file contains the driver for the ATMEGA series USB OTG Controller. This
31 * driver currently only supports the DCI mode of the USB hardware.
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
64 #define USB_DEBUG_VAR atmegadci_debug
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
79 #include <dev/usb/controller/atmegadci.h>
81 #define ATMEGA_BUS2SC(bus) \
82 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
83 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
85 #define ATMEGA_PC2SC(pc) \
86 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
89 static int atmegadci_debug = 0;
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0,
93 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN,
94 &atmegadci_debug, 0, "ATMEGA DCI debug level");
97 #define ATMEGA_INTR_ENDPT 1
101 static const struct usb_bus_methods atmegadci_bus_methods;
102 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods;
103 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
105 static atmegadci_cmd_t atmegadci_setup_rx;
106 static atmegadci_cmd_t atmegadci_data_rx;
107 static atmegadci_cmd_t atmegadci_data_tx;
108 static atmegadci_cmd_t atmegadci_data_tx_sync;
109 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
110 static void atmegadci_do_poll(struct usb_bus *);
111 static void atmegadci_standard_done(struct usb_xfer *);
112 static void atmegadci_root_intr(struct atmegadci_softc *sc);
115 * Here is a list of what the chip supports:
117 static const struct usb_hw_ep_profile
118 atmegadci_ep_profile[2] = {
121 .max_in_frame_size = 64,
122 .max_out_frame_size = 64,
124 .support_control = 1,
127 .max_in_frame_size = 64,
128 .max_out_frame_size = 64,
131 .support_interrupt = 1,
132 .support_isochronous = 1,
139 atmegadci_get_hw_ep_profile(struct usb_device *udev,
140 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
143 *ppf = atmegadci_ep_profile;
144 else if (ep_addr < ATMEGA_EP_MAX)
145 *ppf = atmegadci_ep_profile + 1;
151 atmegadci_clocks_on(struct atmegadci_softc *sc)
153 if (sc->sc_flags.clocks_off &&
154 sc->sc_flags.port_powered) {
159 (sc->sc_clocks_on) (&sc->sc_bus);
161 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
163 ATMEGA_USBCON_OTGPADE |
164 ATMEGA_USBCON_VBUSTE);
166 sc->sc_flags.clocks_off = 0;
168 /* enable transceiver ? */
173 atmegadci_clocks_off(struct atmegadci_softc *sc)
175 if (!sc->sc_flags.clocks_off) {
179 /* disable Transceiver ? */
181 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
183 ATMEGA_USBCON_OTGPADE |
184 ATMEGA_USBCON_FRZCLK |
185 ATMEGA_USBCON_VBUSTE);
187 /* turn clocks off */
188 (sc->sc_clocks_off) (&sc->sc_bus);
190 sc->sc_flags.clocks_off = 1;
195 atmegadci_pull_up(struct atmegadci_softc *sc)
197 /* pullup D+, if possible */
199 if (!sc->sc_flags.d_pulled_up &&
200 sc->sc_flags.port_powered) {
201 sc->sc_flags.d_pulled_up = 1;
202 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
207 atmegadci_pull_down(struct atmegadci_softc *sc)
209 /* pulldown D+, if possible */
211 if (sc->sc_flags.d_pulled_up) {
212 sc->sc_flags.d_pulled_up = 0;
213 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
218 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
222 if (!sc->sc_flags.status_suspend) {
226 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
227 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
229 /* wait 8 milliseconds */
230 /* Wait for reset to complete. */
231 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
233 /* hardware should have cleared RMWKUP bit */
237 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
239 DPRINTFN(5, "addr=%d\n", addr);
241 addr |= ATMEGA_UDADDR_ADDEN;
243 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
247 atmegadci_setup_rx(struct atmegadci_td *td)
249 struct atmegadci_softc *sc;
250 struct usb_device_request req;
254 /* get pointer to softc */
255 sc = ATMEGA_PC2SC(td->pc);
257 /* select endpoint number */
258 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
260 /* check endpoint status */
261 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
263 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
265 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
268 /* clear did stall */
270 /* get the packet byte count */
272 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
273 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
275 /* mask away undefined bits */
278 /* verify data length */
279 if (count != td->remainder) {
280 DPRINTFN(0, "Invalid SETUP packet "
281 "length, %d bytes\n", count);
284 if (count != sizeof(req)) {
285 DPRINTFN(0, "Unsupported SETUP packet "
286 "length, %d bytes\n", count);
290 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
291 (void *)&req, sizeof(req));
293 /* copy data into real buffer */
294 usbd_copy_in(td->pc, 0, &req, sizeof(req));
296 td->offset = sizeof(req);
299 /* sneak peek the set address */
300 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
301 (req.bRequest == UR_SET_ADDRESS)) {
302 sc->sc_dv_addr = req.wValue[0] & 0x7F;
303 /* must write address before ZLP */
304 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
306 sc->sc_dv_addr = 0xFF;
309 /* Clear SETUP packet interrupt and all other previous interrupts */
310 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
311 return (0); /* complete */
314 /* abort any ongoing transfer */
315 if (!td->did_stall) {
316 DPRINTFN(5, "stalling\n");
317 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
319 ATMEGA_UECONX_STALLRQ);
322 if (temp & ATMEGA_UEINTX_RXSTPI) {
323 /* clear SETUP packet interrupt */
324 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
326 /* we only want to know if there is a SETUP packet */
327 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
328 return (1); /* not complete */
332 atmegadci_data_rx(struct atmegadci_td *td)
334 struct atmegadci_softc *sc;
335 struct usb_page_search buf_res;
341 to = 3; /* don't loop forever! */
344 /* get pointer to softc */
345 sc = ATMEGA_PC2SC(td->pc);
347 /* select endpoint number */
348 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
351 /* check if any of the FIFO banks have data */
352 /* check endpoint status */
353 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
355 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
357 if (temp & ATMEGA_UEINTX_RXSTPI) {
358 if (td->remainder == 0) {
360 * We are actually complete and have
361 * received the next SETUP
363 DPRINTFN(5, "faking complete\n");
364 return (0); /* complete */
367 * USB Host Aborted the transfer.
370 return (0); /* complete */
373 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
374 ATMEGA_UEINTX_RXOUTI))) {
378 /* get the packet byte count */
380 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
381 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
383 /* mask away undefined bits */
386 /* verify the packet byte count */
387 if (count != td->max_packet_size) {
388 if (count < td->max_packet_size) {
389 /* we have a short packet */
393 /* invalid USB packet */
395 return (0); /* we are complete */
398 /* verify the packet byte count */
399 if (count > td->remainder) {
400 /* invalid USB packet */
402 return (0); /* we are complete */
405 usbd_get_page(td->pc, td->offset, &buf_res);
407 /* get correct length */
408 if (buf_res.length > count) {
409 buf_res.length = count;
412 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
413 buf_res.buffer, buf_res.length);
415 /* update counters */
416 count -= buf_res.length;
417 td->offset += buf_res.length;
418 td->remainder -= buf_res.length;
421 /* clear OUT packet interrupt */
422 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
424 /* release FIFO bank */
425 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
427 /* check if we are complete */
428 if ((td->remainder == 0) || got_short) {
430 /* we are complete */
433 /* else need to receive a zero length packet */
439 /* we only want to know if there is a SETUP packet or OUT packet */
440 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
441 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
442 return (1); /* not complete */
446 atmegadci_data_tx(struct atmegadci_td *td)
448 struct atmegadci_softc *sc;
449 struct usb_page_search buf_res;
454 to = 3; /* don't loop forever! */
456 /* get pointer to softc */
457 sc = ATMEGA_PC2SC(td->pc);
459 /* select endpoint number */
460 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
464 /* check endpoint status */
465 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
467 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
469 if (temp & ATMEGA_UEINTX_RXSTPI) {
471 * The current transfer was aborted
475 return (0); /* complete */
478 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
480 /* cannot write any data - a bank is busy */
484 count = td->max_packet_size;
485 if (td->remainder < count) {
486 /* we have a short packet */
488 count = td->remainder;
492 usbd_get_page(td->pc, td->offset, &buf_res);
494 /* get correct length */
495 if (buf_res.length > count) {
496 buf_res.length = count;
499 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
500 buf_res.buffer, buf_res.length);
502 /* update counters */
503 count -= buf_res.length;
504 td->offset += buf_res.length;
505 td->remainder -= buf_res.length;
508 /* clear IN packet interrupt */
509 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
511 /* allocate FIFO bank */
512 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
514 /* check remainder */
515 if (td->remainder == 0) {
517 return (0); /* complete */
519 /* else we need to transmit a short packet */
525 /* we only want to know if there is a SETUP packet or free IN packet */
526 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
527 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
528 return (1); /* not complete */
532 atmegadci_data_tx_sync(struct atmegadci_td *td)
534 struct atmegadci_softc *sc;
537 /* get pointer to softc */
538 sc = ATMEGA_PC2SC(td->pc);
540 /* select endpoint number */
541 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
543 /* check endpoint status */
544 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
546 DPRINTFN(5, "temp=0x%02x\n", temp);
548 if (temp & ATMEGA_UEINTX_RXSTPI) {
549 DPRINTFN(5, "faking complete\n");
551 return (0); /* complete */
554 * The control endpoint has only got one bank, so if that bank
555 * is free the packet has been transferred!
557 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
559 /* cannot write any data - a bank is busy */
562 if (sc->sc_dv_addr != 0xFF) {
563 /* set new address */
564 atmegadci_set_address(sc, sc->sc_dv_addr);
566 return (0); /* complete */
569 /* we only want to know if there is a SETUP packet or free IN packet */
570 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
571 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
572 return (1); /* not complete */
576 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
578 struct atmegadci_td *td;
582 td = xfer->td_transfer_cache;
584 if ((td->func) (td)) {
585 /* operation in progress */
588 if (((void *)td) == xfer->td_transfer_last) {
593 } else if (td->remainder > 0) {
595 * We had a short transfer. If there is no alternate
596 * next, stop processing !
603 * Fetch the next transfer descriptor and transfer
604 * some flags to the next transfer descriptor
607 xfer->td_transfer_cache = td;
609 return (1); /* not complete */
612 /* compute all actual lengths */
614 atmegadci_standard_done(xfer);
615 return (0); /* complete */
619 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
621 struct usb_xfer *xfer;
624 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
625 if (!atmegadci_xfer_do_fifo(xfer)) {
626 /* queue has been modified */
633 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
635 DPRINTFN(5, "vbus = %u\n", is_on);
638 if (!sc->sc_flags.status_vbus) {
639 sc->sc_flags.status_vbus = 1;
641 /* complete root HUB interrupt endpoint */
643 atmegadci_root_intr(sc);
646 if (sc->sc_flags.status_vbus) {
647 sc->sc_flags.status_vbus = 0;
648 sc->sc_flags.status_bus_reset = 0;
649 sc->sc_flags.status_suspend = 0;
650 sc->sc_flags.change_suspend = 0;
651 sc->sc_flags.change_connect = 1;
653 /* complete root HUB interrupt endpoint */
655 atmegadci_root_intr(sc);
661 atmegadci_interrupt(struct atmegadci_softc *sc)
665 USB_BUS_LOCK(&sc->sc_bus);
667 /* read interrupt status */
668 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
670 /* clear all set interrupts */
671 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
673 DPRINTFN(14, "UDINT=0x%02x\n", status);
675 /* check for any bus state change interrupts */
676 if (status & ATMEGA_UDINT_EORSTI) {
678 DPRINTFN(5, "end of reset\n");
680 /* set correct state */
681 sc->sc_flags.status_bus_reset = 1;
682 sc->sc_flags.status_suspend = 0;
683 sc->sc_flags.change_suspend = 0;
684 sc->sc_flags.change_connect = 1;
686 /* disable resume interrupt */
687 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
689 ATMEGA_UDINT_EORSTE);
691 /* complete root HUB interrupt endpoint */
692 atmegadci_root_intr(sc);
695 * If resume and suspend is set at the same time we interpret
696 * that like RESUME. Resume is set when there is at least 3
697 * milliseconds of inactivity on the USB BUS.
699 if (status & ATMEGA_UDINT_WAKEUPI) {
701 DPRINTFN(5, "resume interrupt\n");
703 if (sc->sc_flags.status_suspend) {
704 /* update status bits */
705 sc->sc_flags.status_suspend = 0;
706 sc->sc_flags.change_suspend = 1;
708 /* disable resume interrupt */
709 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
711 ATMEGA_UDINT_EORSTE);
713 /* complete root HUB interrupt endpoint */
714 atmegadci_root_intr(sc);
716 } else if (status & ATMEGA_UDINT_SUSPI) {
718 DPRINTFN(5, "suspend interrupt\n");
720 if (!sc->sc_flags.status_suspend) {
721 /* update status bits */
722 sc->sc_flags.status_suspend = 1;
723 sc->sc_flags.change_suspend = 1;
725 /* disable suspend interrupt */
726 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
727 ATMEGA_UDINT_WAKEUPE |
728 ATMEGA_UDINT_EORSTE);
730 /* complete root HUB interrupt endpoint */
731 atmegadci_root_intr(sc);
735 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
737 /* clear all set interrupts */
738 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
740 if (status & ATMEGA_USBINT_VBUSTI) {
743 DPRINTFN(5, "USBINT=0x%02x\n", status);
745 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
746 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
748 /* check for any endpoint interrupts */
749 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
750 /* the hardware will clear the UEINT bits automatically */
753 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
755 atmegadci_interrupt_poll(sc);
757 USB_BUS_UNLOCK(&sc->sc_bus);
761 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
763 struct atmegadci_td *td;
765 /* get current Transfer Descriptor */
769 /* prepare for next TD */
770 temp->td_next = td->obj_next;
772 /* fill out the Transfer Descriptor */
773 td->func = temp->func;
775 td->offset = temp->offset;
776 td->remainder = temp->len;
778 td->did_stall = temp->did_stall;
779 td->short_pkt = temp->short_pkt;
780 td->alt_next = temp->setup_alt_next;
784 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
786 struct atmegadci_std_temp temp;
787 struct atmegadci_softc *sc;
788 struct atmegadci_td *td;
793 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
794 xfer->address, UE_GET_ADDR(xfer->endpointno),
795 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
797 temp.max_frame_size = xfer->max_frame_size;
799 td = xfer->td_start[0];
800 xfer->td_transfer_first = td;
801 xfer->td_transfer_cache = td;
807 temp.td_next = xfer->td_start[0];
809 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
810 xfer->flags_int.isochronous_xfr;
811 temp.did_stall = !xfer->flags_int.control_stall;
813 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
814 ep_no = (xfer->endpointno & UE_ADDR);
816 /* check if we should prepend a setup message */
818 if (xfer->flags_int.control_xfr) {
819 if (xfer->flags_int.control_hdr) {
821 temp.func = &atmegadci_setup_rx;
822 temp.len = xfer->frlengths[0];
823 temp.pc = xfer->frbuffers + 0;
824 temp.short_pkt = temp.len ? 1 : 0;
825 /* check for last frame */
826 if (xfer->nframes == 1) {
827 /* no STATUS stage yet, SETUP is last */
828 if (xfer->flags_int.control_act)
829 temp.setup_alt_next = 0;
832 atmegadci_setup_standard_chain_sub(&temp);
839 if (x != xfer->nframes) {
840 if (xfer->endpointno & UE_DIR_IN) {
841 temp.func = &atmegadci_data_tx;
844 temp.func = &atmegadci_data_rx;
848 /* setup "pc" pointer */
849 temp.pc = xfer->frbuffers + x;
853 while (x != xfer->nframes) {
855 /* DATA0 / DATA1 message */
857 temp.len = xfer->frlengths[x];
861 if (x == xfer->nframes) {
862 if (xfer->flags_int.control_xfr) {
863 if (xfer->flags_int.control_act) {
864 temp.setup_alt_next = 0;
867 temp.setup_alt_next = 0;
872 /* make sure that we send an USB packet */
878 /* regular data transfer */
880 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
883 atmegadci_setup_standard_chain_sub(&temp);
885 if (xfer->flags_int.isochronous_xfr) {
886 temp.offset += temp.len;
888 /* get next Page Cache pointer */
889 temp.pc = xfer->frbuffers + x;
893 if (xfer->flags_int.control_xfr) {
895 /* always setup a valid "pc" pointer for status and sync */
896 temp.pc = xfer->frbuffers + 0;
899 temp.setup_alt_next = 0;
901 /* check if we need to sync */
903 /* we need a SYNC point after TX */
904 temp.func = &atmegadci_data_tx_sync;
905 atmegadci_setup_standard_chain_sub(&temp);
908 /* check if we should append a status stage */
909 if (!xfer->flags_int.control_act) {
912 * Send a DATA1 message and invert the current
913 * endpoint direction.
915 if (xfer->endpointno & UE_DIR_IN) {
916 temp.func = &atmegadci_data_rx;
919 temp.func = &atmegadci_data_tx;
923 atmegadci_setup_standard_chain_sub(&temp);
925 /* we need a SYNC point after TX */
926 temp.func = &atmegadci_data_tx_sync;
927 atmegadci_setup_standard_chain_sub(&temp);
931 /* must have at least one frame! */
933 xfer->td_transfer_last = td;
937 atmegadci_timeout(void *arg)
939 struct usb_xfer *xfer = arg;
941 DPRINTF("xfer=%p\n", xfer);
943 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
945 /* transfer is transferred */
946 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
950 atmegadci_start_standard_chain(struct usb_xfer *xfer)
954 /* poll one time - will turn on interrupts */
955 if (atmegadci_xfer_do_fifo(xfer)) {
957 /* put transfer on interrupt queue */
958 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
960 /* start timeout, if any */
961 if (xfer->timeout != 0) {
962 usbd_transfer_timeout_ms(xfer,
963 &atmegadci_timeout, xfer->timeout);
969 atmegadci_root_intr(struct atmegadci_softc *sc)
973 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
976 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
978 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
979 sizeof(sc->sc_hub_idata));
983 atmegadci_standard_done_sub(struct usb_xfer *xfer)
985 struct atmegadci_td *td;
991 td = xfer->td_transfer_cache;
996 if (xfer->aframes != xfer->nframes) {
998 * Verify the length and subtract
999 * the remainder from "frlengths[]":
1001 if (len > xfer->frlengths[xfer->aframes]) {
1004 xfer->frlengths[xfer->aframes] -= len;
1007 /* Check for transfer error */
1009 /* the transfer is finished */
1014 /* Check for short transfer */
1016 if (xfer->flags_int.short_frames_ok ||
1017 xfer->flags_int.isochronous_xfr) {
1018 /* follow alt next */
1025 /* the transfer is finished */
1033 /* this USB frame is complete */
1039 /* update transfer cache */
1041 xfer->td_transfer_cache = td;
1044 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1048 atmegadci_standard_done(struct usb_xfer *xfer)
1050 usb_error_t err = 0;
1052 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1053 xfer, xfer->endpoint);
1057 xfer->td_transfer_cache = xfer->td_transfer_first;
1059 if (xfer->flags_int.control_xfr) {
1061 if (xfer->flags_int.control_hdr) {
1063 err = atmegadci_standard_done_sub(xfer);
1067 if (xfer->td_transfer_cache == NULL) {
1071 while (xfer->aframes != xfer->nframes) {
1073 err = atmegadci_standard_done_sub(xfer);
1076 if (xfer->td_transfer_cache == NULL) {
1081 if (xfer->flags_int.control_xfr &&
1082 !xfer->flags_int.control_act) {
1084 err = atmegadci_standard_done_sub(xfer);
1087 atmegadci_device_done(xfer, err);
1090 /*------------------------------------------------------------------------*
1091 * atmegadci_device_done
1093 * NOTE: this function can be called more than one time on the
1094 * same USB transfer!
1095 *------------------------------------------------------------------------*/
1097 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1099 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1102 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1104 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1105 xfer, xfer->endpoint, error);
1107 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1108 ep_no = (xfer->endpointno & UE_ADDR);
1110 /* select endpoint number */
1111 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1113 /* disable endpoint interrupt */
1114 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1116 DPRINTFN(15, "disabled interrupts!\n");
1118 /* dequeue transfer and start next transfer */
1119 usbd_transfer_done(xfer, error);
1123 atmegadci_xfer_stall(struct usb_xfer *xfer)
1125 atmegadci_device_done(xfer, USB_ERR_STALLED);
1129 atmegadci_set_stall(struct usb_device *udev,
1130 struct usb_endpoint *ep, uint8_t *did_stall)
1132 struct atmegadci_softc *sc;
1135 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1137 DPRINTFN(5, "endpoint=%p\n", ep);
1139 sc = ATMEGA_BUS2SC(udev->bus);
1140 /* get endpoint number */
1141 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1142 /* select endpoint number */
1143 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1145 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1146 ATMEGA_UECONX_EPEN |
1147 ATMEGA_UECONX_STALLRQ);
1151 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1152 uint8_t ep_type, uint8_t ep_dir)
1156 if (ep_type == UE_CONTROL) {
1157 /* clearing stall is not needed */
1160 /* select endpoint number */
1161 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1163 /* set endpoint reset */
1164 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1166 /* clear endpoint reset */
1167 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1170 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1171 ATMEGA_UECONX_EPEN |
1172 ATMEGA_UECONX_STALLRQ);
1174 /* reset data toggle */
1175 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1176 ATMEGA_UECONX_EPEN |
1177 ATMEGA_UECONX_RSTDT);
1180 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1181 ATMEGA_UECONX_EPEN |
1182 ATMEGA_UECONX_STALLRQC);
1185 if (ep_type == UE_BULK) {
1186 temp = ATMEGA_UECFG0X_EPTYPE2;
1187 } else if (ep_type == UE_INTERRUPT) {
1188 temp = ATMEGA_UECFG0X_EPTYPE3;
1190 temp = ATMEGA_UECFG0X_EPTYPE1;
1192 if (ep_dir & UE_DIR_IN) {
1193 temp |= ATMEGA_UECFG0X_EPDIR;
1195 /* two banks, 64-bytes wMaxPacket */
1196 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1197 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1198 ATMEGA_UECFG1X_ALLOC |
1199 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1200 ATMEGA_UECFG1X_EPSIZE(3));
1202 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1203 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1204 device_printf(sc->sc_bus.bdev,
1205 "Chip rejected configuration\n");
1211 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1213 struct atmegadci_softc *sc;
1214 struct usb_endpoint_descriptor *ed;
1216 DPRINTFN(5, "endpoint=%p\n", ep);
1218 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1221 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1226 sc = ATMEGA_BUS2SC(udev->bus);
1228 /* get endpoint descriptor */
1231 /* reset endpoint */
1232 atmegadci_clear_stall_sub(sc,
1233 (ed->bEndpointAddress & UE_ADDR),
1234 (ed->bmAttributes & UE_XFERTYPE),
1235 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1239 atmegadci_init(struct atmegadci_softc *sc)
1245 /* set up the bus structure */
1246 sc->sc_bus.usbrev = USB_REV_1_1;
1247 sc->sc_bus.methods = &atmegadci_bus_methods;
1249 USB_BUS_LOCK(&sc->sc_bus);
1251 /* make sure USB is enabled */
1252 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1253 ATMEGA_USBCON_USBE |
1254 ATMEGA_USBCON_FRZCLK);
1256 /* enable USB PAD regulator */
1257 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1258 ATMEGA_UHWCON_UVREGE |
1259 ATMEGA_UHWCON_UIMOD);
1261 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1262 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1264 /* wait for PLL to lock */
1265 for (n = 0; n != 20; n++) {
1266 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1268 /* wait a little bit for PLL to start */
1269 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1272 /* make sure USB is enabled */
1273 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1274 ATMEGA_USBCON_USBE |
1275 ATMEGA_USBCON_OTGPADE |
1276 ATMEGA_USBCON_VBUSTE);
1278 /* turn on clocks */
1279 (sc->sc_clocks_on) (&sc->sc_bus);
1281 /* make sure device is re-enumerated */
1282 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1284 /* wait a little for things to stabilise */
1285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1287 /* enable interrupts */
1288 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1289 ATMEGA_UDINT_SUSPE |
1290 ATMEGA_UDINT_EORSTE);
1292 /* reset all endpoints */
1293 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1294 (1 << ATMEGA_EP_MAX) - 1);
1297 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1299 /* disable all endpoints */
1300 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1302 /* select endpoint */
1303 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1305 /* disable endpoint interrupt */
1306 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1308 /* disable endpoint */
1309 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1312 /* turn off clocks */
1314 atmegadci_clocks_off(sc);
1316 /* read initial VBUS state */
1318 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1319 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1321 USB_BUS_UNLOCK(&sc->sc_bus);
1323 /* catch any lost interrupts */
1325 atmegadci_do_poll(&sc->sc_bus);
1327 return (0); /* success */
1331 atmegadci_uninit(struct atmegadci_softc *sc)
1333 USB_BUS_LOCK(&sc->sc_bus);
1335 /* turn on clocks */
1336 (sc->sc_clocks_on) (&sc->sc_bus);
1338 /* disable interrupts */
1339 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1341 /* reset all endpoints */
1342 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1343 (1 << ATMEGA_EP_MAX) - 1);
1346 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1348 sc->sc_flags.port_powered = 0;
1349 sc->sc_flags.status_vbus = 0;
1350 sc->sc_flags.status_bus_reset = 0;
1351 sc->sc_flags.status_suspend = 0;
1352 sc->sc_flags.change_suspend = 0;
1353 sc->sc_flags.change_connect = 1;
1355 atmegadci_pull_down(sc);
1356 atmegadci_clocks_off(sc);
1358 /* disable USB PAD regulator */
1359 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1361 USB_BUS_UNLOCK(&sc->sc_bus);
1365 atmegadci_suspend(struct atmegadci_softc *sc)
1371 atmegadci_resume(struct atmegadci_softc *sc)
1377 atmegadci_do_poll(struct usb_bus *bus)
1379 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1381 USB_BUS_LOCK(&sc->sc_bus);
1382 atmegadci_interrupt_poll(sc);
1383 USB_BUS_UNLOCK(&sc->sc_bus);
1386 /*------------------------------------------------------------------------*
1387 * atmegadci bulk support
1388 * atmegadci control support
1389 * atmegadci interrupt support
1390 *------------------------------------------------------------------------*/
1392 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1398 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1400 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1404 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1410 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1413 atmegadci_setup_standard_chain(xfer);
1414 atmegadci_start_standard_chain(xfer);
1417 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1419 .open = atmegadci_device_non_isoc_open,
1420 .close = atmegadci_device_non_isoc_close,
1421 .enter = atmegadci_device_non_isoc_enter,
1422 .start = atmegadci_device_non_isoc_start,
1425 /*------------------------------------------------------------------------*
1426 * atmegadci full speed isochronous support
1427 *------------------------------------------------------------------------*/
1429 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1435 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1437 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1441 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1443 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1447 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1448 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1450 /* get the current frame index */
1453 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1454 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1456 nframes &= ATMEGA_FRAME_MASK;
1459 * check if the frame index is within the window where the frames
1462 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1464 if ((xfer->endpoint->is_synced == 0) ||
1465 (temp < xfer->nframes)) {
1467 * If there is data underflow or the pipe queue is
1468 * empty we schedule the transfer a few frames ahead
1469 * of the current frame position. Else two isochronous
1470 * transfers might overlap.
1472 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1473 xfer->endpoint->is_synced = 1;
1474 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1477 * compute how many milliseconds the insertion is ahead of the
1478 * current frame position:
1480 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1483 * pre-compute when the isochronous transfer will be finished:
1485 xfer->isoc_time_complete =
1486 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1489 /* compute frame number for next insertion */
1490 xfer->endpoint->isoc_next += xfer->nframes;
1493 atmegadci_setup_standard_chain(xfer);
1497 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1499 /* start TD chain */
1500 atmegadci_start_standard_chain(xfer);
1503 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1505 .open = atmegadci_device_isoc_fs_open,
1506 .close = atmegadci_device_isoc_fs_close,
1507 .enter = atmegadci_device_isoc_fs_enter,
1508 .start = atmegadci_device_isoc_fs_start,
1511 /*------------------------------------------------------------------------*
1512 * atmegadci root control support
1513 *------------------------------------------------------------------------*
1514 * Simulate a hardware HUB by handling all the necessary requests.
1515 *------------------------------------------------------------------------*/
1517 static const struct usb_device_descriptor atmegadci_devd = {
1518 .bLength = sizeof(struct usb_device_descriptor),
1519 .bDescriptorType = UDESC_DEVICE,
1520 .bcdUSB = {0x00, 0x02},
1521 .bDeviceClass = UDCLASS_HUB,
1522 .bDeviceSubClass = UDSUBCLASS_HUB,
1523 .bDeviceProtocol = UDPROTO_FSHUB,
1524 .bMaxPacketSize = 64,
1525 .bcdDevice = {0x00, 0x01},
1528 .bNumConfigurations = 1,
1531 static const struct atmegadci_config_desc atmegadci_confd = {
1533 .bLength = sizeof(struct usb_config_descriptor),
1534 .bDescriptorType = UDESC_CONFIG,
1535 .wTotalLength[0] = sizeof(atmegadci_confd),
1537 .bConfigurationValue = 1,
1538 .iConfiguration = 0,
1539 .bmAttributes = UC_SELF_POWERED,
1543 .bLength = sizeof(struct usb_interface_descriptor),
1544 .bDescriptorType = UDESC_INTERFACE,
1546 .bInterfaceClass = UICLASS_HUB,
1547 .bInterfaceSubClass = UISUBCLASS_HUB,
1548 .bInterfaceProtocol = 0,
1551 .bLength = sizeof(struct usb_endpoint_descriptor),
1552 .bDescriptorType = UDESC_ENDPOINT,
1553 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1554 .bmAttributes = UE_INTERRUPT,
1555 .wMaxPacketSize[0] = 8,
1560 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1562 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1563 .bDescLength = sizeof(atmegadci_hubd),
1564 .bDescriptorType = UDESC_HUB,
1566 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1567 .bPwrOn2PwrGood = 50,
1568 .bHubContrCurrent = 0,
1569 .DeviceRemovable = {0}, /* port is removable */
1572 #define STRING_VENDOR \
1575 #define STRING_PRODUCT \
1576 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1578 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1579 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1582 atmegadci_roothub_exec(struct usb_device *udev,
1583 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1585 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1593 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1596 ptr = (const void *)&sc->sc_hub_temp;
1600 value = UGETW(req->wValue);
1601 index = UGETW(req->wIndex);
1603 /* demultiplex the control request */
1605 switch (req->bmRequestType) {
1606 case UT_READ_DEVICE:
1607 switch (req->bRequest) {
1608 case UR_GET_DESCRIPTOR:
1609 goto tr_handle_get_descriptor;
1611 goto tr_handle_get_config;
1613 goto tr_handle_get_status;
1619 case UT_WRITE_DEVICE:
1620 switch (req->bRequest) {
1621 case UR_SET_ADDRESS:
1622 goto tr_handle_set_address;
1624 goto tr_handle_set_config;
1625 case UR_CLEAR_FEATURE:
1626 goto tr_valid; /* nop */
1627 case UR_SET_DESCRIPTOR:
1628 goto tr_valid; /* nop */
1629 case UR_SET_FEATURE:
1635 case UT_WRITE_ENDPOINT:
1636 switch (req->bRequest) {
1637 case UR_CLEAR_FEATURE:
1638 switch (UGETW(req->wValue)) {
1639 case UF_ENDPOINT_HALT:
1640 goto tr_handle_clear_halt;
1641 case UF_DEVICE_REMOTE_WAKEUP:
1642 goto tr_handle_clear_wakeup;
1647 case UR_SET_FEATURE:
1648 switch (UGETW(req->wValue)) {
1649 case UF_ENDPOINT_HALT:
1650 goto tr_handle_set_halt;
1651 case UF_DEVICE_REMOTE_WAKEUP:
1652 goto tr_handle_set_wakeup;
1657 case UR_SYNCH_FRAME:
1658 goto tr_valid; /* nop */
1664 case UT_READ_ENDPOINT:
1665 switch (req->bRequest) {
1667 goto tr_handle_get_ep_status;
1673 case UT_WRITE_INTERFACE:
1674 switch (req->bRequest) {
1675 case UR_SET_INTERFACE:
1676 goto tr_handle_set_interface;
1677 case UR_CLEAR_FEATURE:
1678 goto tr_valid; /* nop */
1679 case UR_SET_FEATURE:
1685 case UT_READ_INTERFACE:
1686 switch (req->bRequest) {
1687 case UR_GET_INTERFACE:
1688 goto tr_handle_get_interface;
1690 goto tr_handle_get_iface_status;
1696 case UT_WRITE_CLASS_INTERFACE:
1697 case UT_WRITE_VENDOR_INTERFACE:
1701 case UT_READ_CLASS_INTERFACE:
1702 case UT_READ_VENDOR_INTERFACE:
1706 case UT_WRITE_CLASS_DEVICE:
1707 switch (req->bRequest) {
1708 case UR_CLEAR_FEATURE:
1710 case UR_SET_DESCRIPTOR:
1711 case UR_SET_FEATURE:
1718 case UT_WRITE_CLASS_OTHER:
1719 switch (req->bRequest) {
1720 case UR_CLEAR_FEATURE:
1721 goto tr_handle_clear_port_feature;
1722 case UR_SET_FEATURE:
1723 goto tr_handle_set_port_feature;
1724 case UR_CLEAR_TT_BUFFER:
1734 case UT_READ_CLASS_OTHER:
1735 switch (req->bRequest) {
1736 case UR_GET_TT_STATE:
1737 goto tr_handle_get_tt_state;
1739 goto tr_handle_get_port_status;
1745 case UT_READ_CLASS_DEVICE:
1746 switch (req->bRequest) {
1747 case UR_GET_DESCRIPTOR:
1748 goto tr_handle_get_class_descriptor;
1750 goto tr_handle_get_class_status;
1761 tr_handle_get_descriptor:
1762 switch (value >> 8) {
1767 len = sizeof(atmegadci_devd);
1768 ptr = (const void *)&atmegadci_devd;
1774 len = sizeof(atmegadci_confd);
1775 ptr = (const void *)&atmegadci_confd;
1778 switch (value & 0xff) {
1779 case 0: /* Language table */
1780 len = sizeof(usb_string_lang_en);
1781 ptr = (const void *)&usb_string_lang_en;
1784 case 1: /* Vendor */
1785 len = sizeof(atmegadci_vendor);
1786 ptr = (const void *)&atmegadci_vendor;
1789 case 2: /* Product */
1790 len = sizeof(atmegadci_product);
1791 ptr = (const void *)&atmegadci_product;
1802 tr_handle_get_config:
1804 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1807 tr_handle_get_status:
1809 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1812 tr_handle_set_address:
1813 if (value & 0xFF00) {
1816 sc->sc_rt_addr = value;
1819 tr_handle_set_config:
1823 sc->sc_conf = value;
1826 tr_handle_get_interface:
1828 sc->sc_hub_temp.wValue[0] = 0;
1831 tr_handle_get_tt_state:
1832 tr_handle_get_class_status:
1833 tr_handle_get_iface_status:
1834 tr_handle_get_ep_status:
1836 USETW(sc->sc_hub_temp.wValue, 0);
1840 tr_handle_set_interface:
1841 tr_handle_set_wakeup:
1842 tr_handle_clear_wakeup:
1843 tr_handle_clear_halt:
1846 tr_handle_clear_port_feature:
1850 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1853 case UHF_PORT_SUSPEND:
1854 atmegadci_wakeup_peer(sc);
1857 case UHF_PORT_ENABLE:
1858 sc->sc_flags.port_enabled = 0;
1862 case UHF_PORT_INDICATOR:
1863 case UHF_C_PORT_ENABLE:
1864 case UHF_C_PORT_OVER_CURRENT:
1865 case UHF_C_PORT_RESET:
1868 case UHF_PORT_POWER:
1869 sc->sc_flags.port_powered = 0;
1870 atmegadci_pull_down(sc);
1871 atmegadci_clocks_off(sc);
1873 case UHF_C_PORT_CONNECTION:
1874 /* clear connect change flag */
1875 sc->sc_flags.change_connect = 0;
1877 if (!sc->sc_flags.status_bus_reset) {
1878 /* we are not connected */
1882 /* configure the control endpoint */
1884 /* select endpoint number */
1885 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1887 /* set endpoint reset */
1888 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1890 /* clear endpoint reset */
1891 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1893 /* enable and stall endpoint */
1894 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1895 ATMEGA_UECONX_EPEN |
1896 ATMEGA_UECONX_STALLRQ);
1898 /* one bank, 64-bytes wMaxPacket */
1899 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1900 ATMEGA_UECFG0X_EPTYPE0);
1901 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1902 ATMEGA_UECFG1X_ALLOC |
1903 ATMEGA_UECFG1X_EPBK0 |
1904 ATMEGA_UECFG1X_EPSIZE(3));
1906 /* check valid config */
1907 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1908 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1909 device_printf(sc->sc_bus.bdev,
1910 "Chip rejected EP0 configuration\n");
1913 case UHF_C_PORT_SUSPEND:
1914 sc->sc_flags.change_suspend = 0;
1917 err = USB_ERR_IOERROR;
1922 tr_handle_set_port_feature:
1926 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1929 case UHF_PORT_ENABLE:
1930 sc->sc_flags.port_enabled = 1;
1932 case UHF_PORT_SUSPEND:
1933 case UHF_PORT_RESET:
1935 case UHF_PORT_INDICATOR:
1938 case UHF_PORT_POWER:
1939 sc->sc_flags.port_powered = 1;
1942 err = USB_ERR_IOERROR;
1947 tr_handle_get_port_status:
1949 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1954 if (sc->sc_flags.status_vbus) {
1955 atmegadci_clocks_on(sc);
1956 atmegadci_pull_up(sc);
1958 atmegadci_pull_down(sc);
1959 atmegadci_clocks_off(sc);
1962 /* Select FULL-speed and Device Side Mode */
1964 value = UPS_PORT_MODE_DEVICE;
1966 if (sc->sc_flags.port_powered) {
1967 value |= UPS_PORT_POWER;
1969 if (sc->sc_flags.port_enabled) {
1970 value |= UPS_PORT_ENABLED;
1972 if (sc->sc_flags.status_vbus &&
1973 sc->sc_flags.status_bus_reset) {
1974 value |= UPS_CURRENT_CONNECT_STATUS;
1976 if (sc->sc_flags.status_suspend) {
1977 value |= UPS_SUSPEND;
1979 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1983 if (sc->sc_flags.change_connect) {
1984 value |= UPS_C_CONNECT_STATUS;
1986 if (sc->sc_flags.change_suspend) {
1987 value |= UPS_C_SUSPEND;
1989 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1990 len = sizeof(sc->sc_hub_temp.ps);
1993 tr_handle_get_class_descriptor:
1997 ptr = (const void *)&atmegadci_hubd;
1998 len = sizeof(atmegadci_hubd);
2002 err = USB_ERR_STALLED;
2011 atmegadci_xfer_setup(struct usb_setup_params *parm)
2013 const struct usb_hw_ep_profile *pf;
2014 struct atmegadci_softc *sc;
2015 struct usb_xfer *xfer;
2021 sc = ATMEGA_BUS2SC(parm->udev->bus);
2022 xfer = parm->curr_xfer;
2025 * NOTE: This driver does not use any of the parameters that
2026 * are computed from the following values. Just set some
2027 * reasonable dummies:
2029 parm->hc_max_packet_size = 0x500;
2030 parm->hc_max_packet_count = 1;
2031 parm->hc_max_frame_size = 0x500;
2033 usbd_transfer_setup_sub(parm);
2036 * compute maximum number of TDs
2038 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2040 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2044 ntd = xfer->nframes + 1 /* SYNC */ ;
2048 * check if "usbd_transfer_setup_sub" set an error
2054 * allocate transfer descriptors
2061 ep_no = xfer->endpointno & UE_ADDR;
2062 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2065 /* should not happen */
2066 parm->err = USB_ERR_INVAL;
2071 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2073 for (n = 0; n != ntd; n++) {
2075 struct atmegadci_td *td;
2079 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2082 td->max_packet_size = xfer->max_packet_size;
2084 if (pf->support_multi_buffer) {
2085 td->support_multi_buffer = 1;
2087 td->obj_next = last_obj;
2091 parm->size[0] += sizeof(*td);
2094 xfer->td_start[0] = last_obj;
2098 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2104 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2105 struct usb_endpoint *ep)
2107 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2109 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2111 edesc->bEndpointAddress, udev->flags.usb_mode,
2112 sc->sc_rt_addr, udev->device_index);
2114 if (udev->device_index != sc->sc_rt_addr) {
2116 if (udev->speed != USB_SPEED_FULL) {
2120 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2121 ep->methods = &atmegadci_device_isoc_fs_methods;
2123 ep->methods = &atmegadci_device_non_isoc_methods;
2128 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2130 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2133 case USB_HW_POWER_SUSPEND:
2134 atmegadci_suspend(sc);
2136 case USB_HW_POWER_SHUTDOWN:
2137 atmegadci_uninit(sc);
2139 case USB_HW_POWER_RESUME:
2140 atmegadci_resume(sc);
2147 static const struct usb_bus_methods atmegadci_bus_methods =
2149 .endpoint_init = &atmegadci_ep_init,
2150 .xfer_setup = &atmegadci_xfer_setup,
2151 .xfer_unsetup = &atmegadci_xfer_unsetup,
2152 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2153 .xfer_stall = &atmegadci_xfer_stall,
2154 .set_stall = &atmegadci_set_stall,
2155 .clear_stall = &atmegadci_clear_stall,
2156 .roothub_exec = &atmegadci_roothub_exec,
2157 .xfer_poll = &atmegadci_do_poll,
2158 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,